MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c

   1 /** @file
   2
   3   The XHCI register operation routines.
   4
   5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include "Xhci.h"
  17
  18 /**
  19   Read 1-byte width XHCI capability register.
  20
  21   @param  Xhc          The XHCI device.
  22   @param  Offset       The offset of the 1-byte width capability register.
  23
  24   @return The register content read.
  25   @retval If err, return 0xFF.
  26
  27 **/
  28 UINT8
  29 XhcReadCapReg8 (
  30   IN  USB_XHCI_DEV        *Xhc,
  31   IN  UINT32              Offset
  32   )
  33 {
  34   UINT8                   Data;
  35   EFI_STATUS              Status;
  36
  37   Status = Xhc->PciIo->Mem.Read (
  38                              Xhc->PciIo,
  39                              EfiPciIoWidthUint8,
  40                              XHC_BAR_INDEX,
  41                              (UINT64) Offset,
  42                              1,
  43                              &Data
  44                              );
  45
  46   if (EFI_ERROR (Status)) {
  47     DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
  48     Data = 0xFF;
  49   }
  50
  51   return Data;
  52 }
  53
  54 /**
  55   Read 4-bytes width XHCI capability register.
  56
  57   @param  Xhc          The XHCI device.
  58   @param  Offset       The offset of the 4-bytes width capability register.
  59
  60   @return The register content read.
  61   @retval If err, return 0xFFFFFFFF.
  62
  63 **/
  64 UINT32
  65 XhcReadCapReg (
  66   IN  USB_XHCI_DEV        *Xhc,
  67   IN  UINT32              Offset
  68   )
  69 {
  70   UINT32                  Data;
  71   EFI_STATUS              Status;
  72
  73   Status = Xhc->PciIo->Mem.Read (
  74                              Xhc->PciIo,
  75                              EfiPciIoWidthUint32,
  76                              XHC_BAR_INDEX,
  77                              (UINT64) Offset,
  78                              1,
  79                              &Data
  80                              );
  81
  82   if (EFI_ERROR (Status)) {
  83     DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
  84     Data = 0xFFFFFFFF;
  85   }
  86
  87   return Data;
  88 }
  89
  90 /**
  91   Read 4-bytes width XHCI Operational register.
  92
  93   @param  Xhc          The XHCI device.
  94   @param  Offset       The offset of the 4-bytes width operational register.
  95
  96   @return The register content read.
  97   @retval If err, return 0xFFFFFFFF.
  98
  99 **/
 100 UINT32
 101 XhcReadOpReg (
 102   IN  USB_XHCI_DEV        *Xhc,
 103   IN  UINT32              Offset
 104   )
 105 {
 106   UINT32                  Data;
 107   EFI_STATUS              Status;
 108
 109   ASSERT (Xhc->CapLength != 0);
 110
 111   Status = Xhc->PciIo->Mem.Read (
 112                              Xhc->PciIo,
 113                              EfiPciIoWidthUint32,
 114                              XHC_BAR_INDEX,
 115                              (UINT64) (Xhc->CapLength + Offset),
 116                              1,
 117                              &Data
 118                              );
 119
 120   if (EFI_ERROR (Status)) {
 121     DEBUG ((EFI_D_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
 122     Data = 0xFFFFFFFF;
 123   }
 124
 125   return Data;
 126 }
 127
 128 /**
 129   Write the data to the 4-bytes width XHCI operational register.
 130
 131   @param  Xhc      The XHCI device.
 132   @param  Offset   The offset of the 4-bytes width operational register.
 133   @param  Data     The data to write.
 134
 135 **/
 136 VOID
 137 XhcWriteOpReg (
 138   IN USB_XHCI_DEV         *Xhc,
 139   IN UINT32               Offset,
 140   IN UINT32               Data
 141   )
 142 {
 143   EFI_STATUS              Status;
 144
 145   ASSERT (Xhc->CapLength != 0);
 146
 147   Status = Xhc->PciIo->Mem.Write (
 148                              Xhc->PciIo,
 149                              EfiPciIoWidthUint32,
 150                              XHC_BAR_INDEX,
 151                              (UINT64) (Xhc->CapLength + Offset),
 152                              1,
 153                              &Data
 154                              );
 155
 156   if (EFI_ERROR (Status)) {
 157     DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
 158   }
 159 }
 160
 161 /**
 162   Write the data to the 2-bytes width XHCI operational register.
 163
 164   @param  Xhc          The XHCI device.
 165   @param  Offset       The offset of the 2-bytes width operational register.
 166   @param  Data         The data to write.
 167
 168 **/
 169 VOID
 170 XhcWriteOpReg16 (
 171   IN USB_XHCI_DEV         *Xhc,
 172   IN UINT32               Offset,
 173   IN UINT16               Data
 174   )
 175 {
 176   EFI_STATUS              Status;
 177
 178   ASSERT (Xhc->CapLength != 0);
 179
 180   Status = Xhc->PciIo->Mem.Write (
 181                              Xhc->PciIo,
 182                              EfiPciIoWidthUint16,
 183                              XHC_BAR_INDEX,
 184                              (UINT64) (Xhc->CapLength + Offset),
 185                              1,
 186                              &Data
 187                              );
 188
 189   if (EFI_ERROR (Status)) {
 190     DEBUG ((EFI_D_ERROR, "XhcWriteOpReg16: Pci Io Write error: %r at %d\n", Status, Offset));
 191   }
 192 }
 193
 194 /**
 195   Write the data to the 8-bytes width XHCI operational register.
 196
 197   @param  Xhc          The XHCI device.
 198   @param  Offset       The offset of the 8-bytes width operational register.
 199   @param  Data         The data to write.
 200
 201 **/
 202 VOID
 203 XhcWriteOpReg64 (
 204   IN USB_XHCI_DEV         *Xhc,
 205   IN UINT32               Offset,
 206   IN UINT64               Data
 207   )
 208 {
 209   EFI_STATUS              Status;
 210
 211   ASSERT (Xhc->CapLength != 0);
 212
 213   Status = Xhc->PciIo->Mem.Write (
 214                              Xhc->PciIo,
 215                              EfiPciIoWidthUint64,
 216                              XHC_BAR_INDEX,
 217                              (UINT64) (Xhc->CapLength + Offset),
 218                              1,
 219                              &Data
 220                              );
 221
 222   if (EFI_ERROR (Status)) {
 223     DEBUG ((EFI_D_ERROR, "XhcWriteOpReg64: Pci Io Write error: %r at %d\n", Status, Offset));
 224   }
 225 }
 226
 227 /**
 228   Read XHCI door bell register.
 229
 230   @param  Xhc          The XHCI device.
 231   @param  Offset       The offset of the door bell register.
 232
 233   @return The register content read
 234
 235 **/
 236 UINT32
 237 XhcReadDoorBellReg (
 238   IN  USB_XHCI_DEV        *Xhc,
 239   IN  UINT32              Offset
 240   )
 241 {
 242   UINT32                  Data;
 243   EFI_STATUS              Status;
 244
 245   ASSERT (Xhc->DBOff != 0);
 246
 247   Status = Xhc->PciIo->Mem.Read (
 248                              Xhc->PciIo,
 249                              EfiPciIoWidthUint32,
 250                              XHC_BAR_INDEX,
 251                              (UINT64) (Xhc->DBOff + Offset),
 252                              1,
 253                              &Data
 254                              );
 255
 256   if (EFI_ERROR (Status)) {
 257     DEBUG ((EFI_D_ERROR, "XhcReadDoorBellReg: Pci Io Read error - %r at %d\n", Status, Offset));
 258     Data = 0xFFFFFFFF;
 259   }
 260
 261   return Data;
 262 }
 263
 264 /**
 265   Write the data to the XHCI door bell register.
 266
 267   @param  Xhc          The XHCI device.
 268   @param  Offset       The offset of the door bell register.
 269   @param  Data         The data to write.
 270
 271 **/
 272 VOID
 273 XhcWriteDoorBellReg (
 274   IN USB_XHCI_DEV         *Xhc,
 275   IN UINT32               Offset,
 276   IN UINT32               Data
 277   )
 278 {
 279   EFI_STATUS              Status;
 280
 281   ASSERT (Xhc->DBOff != 0);
 282
 283   Status = Xhc->PciIo->Mem.Write (
 284                              Xhc->PciIo,
 285                              EfiPciIoWidthUint32,
 286                              XHC_BAR_INDEX,
 287                              (UINT64) (Xhc->DBOff + Offset),
 288                              1,
 289                              &Data
 290                              );
 291
 292   if (EFI_ERROR (Status)) {
 293     DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
 294   }
 295 }
 296
 297 /**
 298   Read XHCI runtime register.
 299
 300   @param  Xhc          The XHCI device.
 301   @param  Offset       The offset of the runtime register.
 302
 303   @return The register content read
 304
 305 **/
 306 UINT32
 307 XhcReadRuntimeReg (
 308   IN  USB_XHCI_DEV        *Xhc,
 309   IN  UINT32              Offset
 310   )
 311 {
 312   UINT32                  Data;
 313   EFI_STATUS              Status;
 314
 315   ASSERT (Xhc->RTSOff != 0);
 316
 317   Status = Xhc->PciIo->Mem.Read (
 318                              Xhc->PciIo,
 319                              EfiPciIoWidthUint32,
 320                              XHC_BAR_INDEX,
 321                              (UINT64) (Xhc->RTSOff + Offset),
 322                              1,
 323                              &Data
 324                              );
 325
 326   if (EFI_ERROR (Status)) {
 327     DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
 328     Data = 0xFFFFFFFF;
 329   }
 330
 331   return Data;
 332 }
 333
 334 /**
 335   Read 8-bytes width XHCI runtime register.
 336
 337   @param  Xhc          The XHCI device.
 338   @param  Offset       The offset of the 8-bytes width runtime register.
 339
 340   @return The register content read
 341
 342 **/
 343 UINT64
 344 XhcReadRuntimeReg64 (
 345   IN  USB_XHCI_DEV        *Xhc,
 346   IN  UINT32              Offset
 347   )
 348 {
 349   UINT64                  Data;
 350   EFI_STATUS              Status;
 351
 352   ASSERT (Xhc->RTSOff != 0);
 353
 354   Status = Xhc->PciIo->Mem.Read (
 355                              Xhc->PciIo,
 356                              EfiPciIoWidthUint64,
 357                              XHC_BAR_INDEX,
 358                              (UINT64) (Xhc->RTSOff + Offset),
 359                              1,
 360                              &Data
 361                              );
 362
 363   if (EFI_ERROR (Status)) {
 364     DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg64: Pci Io Read error - %r at %d\n", Status, Offset));
 365     Data = 0xFFFFFFFFFFFFFFFF;
 366   }
 367
 368   return Data;
 369 }
 370
 371 /**
 372   Write the data to the XHCI runtime register.
 373
 374   @param  Xhc          The XHCI device.
 375   @param  Offset       The offset of the runtime register.
 376   @param  Data         The data to write.
 377
 378 **/
 379 VOID
 380 XhcWriteRuntimeReg (
 381   IN USB_XHCI_DEV         *Xhc,
 382   IN UINT32               Offset,
 383   IN UINT32               Data
 384   )
 385 {
 386   EFI_STATUS              Status;
 387
 388   ASSERT (Xhc->RTSOff != 0);
 389
 390   Status = Xhc->PciIo->Mem.Write (
 391                              Xhc->PciIo,
 392                              EfiPciIoWidthUint32,
 393                              XHC_BAR_INDEX,
 394                              (UINT64) (Xhc->RTSOff + Offset),
 395                              1,
 396                              &Data
 397                              );
 398
 399   if (EFI_ERROR (Status)) {
 400     DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
 401   }
 402 }
 403
 404 /**
 405   Write the data to the 8-bytes width XHCI runtime register.
 406
 407   @param  Xhc          The XHCI device.
 408   @param  Offset       The offset of the 8-bytes width runtime register.
 409   @param  Data         The data to write.
 410
 411 **/
 412 VOID
 413 XhcWriteRuntimeReg64 (
 414   IN USB_XHCI_DEV         *Xhc,
 415   IN UINT32               Offset,
 416   IN UINT64               Data
 417   )
 418 {
 419   EFI_STATUS              Status;
 420
 421   ASSERT (Xhc->RTSOff != 0);
 422
 423   Status = Xhc->PciIo->Mem.Write (
 424                              Xhc->PciIo,
 425                              EfiPciIoWidthUint64,
 426                              XHC_BAR_INDEX,
 427                              (UINT64) (Xhc->RTSOff + Offset),
 428                              1,
 429                              &Data
 430                              );
 431
 432   if (EFI_ERROR (Status)) {
 433     DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg64: Pci Io Write error: %r at %d\n", Status, Offset));
 434   }
 435 }
 436
 437 /**
 438   Read XHCI extended capability register.
 439
 440   @param  Xhc          The XHCI device.
 441   @param  Offset       The offset of the extended capability register.
 442
 443   @return The register content read
 444
 445 **/
 446 UINT32
 447 XhcReadExtCapReg (
 448   IN  USB_XHCI_DEV        *Xhc,
 449   IN  UINT32              Offset
 450   )
 451 {
 452   UINT32                  Data;
 453   EFI_STATUS              Status;
 454
 455   ASSERT (Xhc->ExtCapRegBase != 0);
 456
 457   Status = Xhc->PciIo->Mem.Read (
 458                              Xhc->PciIo,
 459                              EfiPciIoWidthUint32,
 460                              XHC_BAR_INDEX,
 461                              (UINT64) (Xhc->ExtCapRegBase + Offset),
 462                              1,
 463                              &Data
 464                              );
 465
 466   if (EFI_ERROR (Status)) {
 467     DEBUG ((EFI_D_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
 468     Data = 0xFFFFFFFF;
 469   }
 470
 471   return Data;
 472 }
 473
 474 /**
 475   Write the data to the XHCI extended capability register.
 476
 477   @param  Xhc          The XHCI device.
 478   @param  Offset       The offset of the extended capability register.
 479   @param  Data         The data to write.
 480
 481 **/
 482 VOID
 483 XhcWriteExtCapReg (
 484   IN USB_XHCI_DEV         *Xhc,
 485   IN UINT32               Offset,
 486   IN UINT32               Data
 487   )
 488 {
 489   EFI_STATUS              Status;
 490
 491   ASSERT (Xhc->ExtCapRegBase != 0);
 492
 493   Status = Xhc->PciIo->Mem.Write (
 494                              Xhc->PciIo,
 495                              EfiPciIoWidthUint32,
 496                              XHC_BAR_INDEX,
 497                              (UINT64) (Xhc->ExtCapRegBase + Offset),
 498                              1,
 499                              &Data
 500                              );
 501
 502   if (EFI_ERROR (Status)) {
 503     DEBUG ((EFI_D_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
 504   }
 505 }
 506
 507
 508 /**
 509   Set one bit of the runtime register while keeping other bits.
 510
 511   @param  Xhc          The XHCI device.
 512   @param  Offset       The offset of the runtime register.
 513   @param  Bit          The bit mask of the register to set.
 514
 515 **/
 516 VOID
 517 XhcSetRuntimeRegBit (
 518   IN USB_XHCI_DEV         *Xhc,
 519   IN UINT32               Offset,
 520   IN UINT32               Bit
 521   )
 522 {
 523   UINT32                  Data;
 524
 525   Data  = XhcReadRuntimeReg (Xhc, Offset);
 526   Data |= Bit;
 527   XhcWriteRuntimeReg (Xhc, Offset, Data);
 528 }
 529
 530 /**
 531   Clear one bit of the runtime register while keeping other bits.
 532
 533   @param  Xhc          The XHCI device.
 534   @param  Offset       The offset of the runtime register.
 535   @param  Bit          The bit mask of the register to set.
 536
 537 **/
 538 VOID
 539 XhcClearRuntimeRegBit (
 540   IN USB_XHCI_DEV         *Xhc,
 541   IN UINT32               Offset,
 542   IN UINT32               Bit
 543   )
 544 {
 545   UINT32                  Data;
 546
 547   Data  = XhcReadRuntimeReg (Xhc, Offset);
 548   Data &= ~Bit;
 549   XhcWriteRuntimeReg (Xhc, Offset, Data);
 550 }
 551
 552 /**
 553   Set one bit of the operational register while keeping other bits.
 554
 555   @param  Xhc          The XHCI device.
 556   @param  Offset       The offset of the operational register.
 557   @param  Bit          The bit mask of the register to set.
 558
 559 **/
 560 VOID
 561 XhcSetOpRegBit (
 562   IN USB_XHCI_DEV         *Xhc,
 563   IN UINT32               Offset,
 564   IN UINT32               Bit
 565   )
 566 {
 567   UINT32                  Data;
 568
 569   Data  = XhcReadOpReg (Xhc, Offset);
 570   Data |= Bit;
 571   XhcWriteOpReg (Xhc, Offset, Data);
 572 }
 573
 574
 575 /**
 576   Clear one bit of the operational register while keeping other bits.
 577
 578   @param  Xhc          The XHCI device.
 579   @param  Offset       The offset of the operational register.
 580   @param  Bit          The bit mask of the register to clear.
 581
 582 **/
 583 VOID
 584 XhcClearOpRegBit (
 585   IN USB_XHCI_DEV         *Xhc,
 586   IN UINT32               Offset,
 587   IN UINT32               Bit
 588   )
 589 {
 590   UINT32                  Data;
 591
 592   Data  = XhcReadOpReg (Xhc, Offset);
 593   Data &= ~Bit;
 594   XhcWriteOpReg (Xhc, Offset, Data);
 595 }
 596
 597 /**
 598   Wait the operation register's bit as specified by Bit
 599   to become set (or clear).
 600
 601   @param  Xhc          The XHCI device.
 602   @param  Offset       The offset of the operation register.
 603   @param  Bit          The bit of the register to wait for.
 604   @param  WaitToSet    Wait the bit to set or clear.
 605   @param  Timeout      The time to wait before abort (in millisecond, ms).
 606
 607   @retval EFI_SUCCESS  The bit successfully changed by host controller.
 608   @retval EFI_TIMEOUT  The time out occurred.
 609
 610 **/
 611 EFI_STATUS
 612 XhcWaitOpRegBit (
 613   IN USB_XHCI_DEV         *Xhc,
 614   IN UINT32               Offset,
 615   IN UINT32               Bit,
 616   IN BOOLEAN              WaitToSet,
 617   IN UINT32               Timeout
 618   )
 619 {
 620   UINT32                  Index;
 621
 622   for (Index = 0; Index < Timeout / XHC_SYNC_POLL_INTERVAL + 1; Index++) {
 623     if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {
 624       return EFI_SUCCESS;
 625     }
 626
 627     gBS->Stall (XHC_SYNC_POLL_INTERVAL);
 628   }
 629
 630   return EFI_TIMEOUT;
 631 }
 632
 633 /**
 634   Set Bios Ownership
 635
 636   @param  Xhc          The XHCI device.
 637
 638 **/
 639 VOID
 640 XhcSetBiosOwnership (
 641   IN USB_XHCI_DEV         *Xhc
 642   )
 643 {
 644   UINT32                    Buffer;
 645
 646   DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
 647
 648   Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
 649   Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);
 650   XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);
 651 }
 652
 653 /**
 654   Clear Bios Ownership
 655
 656   @param  Xhc       The XHCI device.
 657
 658 **/
 659 VOID
 660 XhcClearBiosOwnership (
 661   IN USB_XHCI_DEV         *Xhc
 662   )
 663 {
 664   UINT32                    Buffer;
 665
 666   DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
 667
 668   Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
 669   Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);
 670   XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);
 671 }
 672
 673 /**
 674   Calculate the XHCI legacy support capability register offset.
 675
 676   @param  Xhc     The XHCI device.
 677
 678   @return The offset of XHCI legacy support capability register.
 679
 680 **/
 681 UINT32
 682 XhcGetLegSupCapAddr (
 683   IN USB_XHCI_DEV         *Xhc
 684   )
 685 {
 686   UINT32 ExtCapOffset;
 687   UINT8  NextExtCapReg;
 688   UINT32 Data;
 689
 690   ExtCapOffset = 0;
 691
 692   do {
 693     //
 694     // Check if the extended capability register's capability id is USB Legacy Support.
 695     //
 696     Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
 697     if ((Data & 0xFF) == 0x1) {
 698       return ExtCapOffset;
 699     }
 700     //
 701     // If not, then traverse all of the ext capability registers till finding out it.
 702     //
 703     NextExtCapReg = (Data >> 8) & 0xFF;
 704     ExtCapOffset += (NextExtCapReg << 2);
 705   } while (NextExtCapReg != 0);
 706
 707   return 0;
 708 }
 709
 710 /**
 711   Whether the XHCI host controller is halted.
 712
 713   @param  Xhc     The XHCI device.
 714
 715   @retval TRUE    The controller is halted.
 716   @retval FALSE   It isn't halted.
 717
 718 **/
 719 BOOLEAN
 720 XhcIsHalt (
 721   IN USB_XHCI_DEV         *Xhc
 722   )
 723 {
 724   return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
 725 }
 726
 727
 728 /**
 729   Whether system error occurred.
 730
 731   @param  Xhc      The XHCI device.
 732
 733   @retval TRUE     System error happened.
 734   @retval FALSE    No system error.
 735
 736 **/
 737 BOOLEAN
 738 XhcIsSysError (
 739   IN USB_XHCI_DEV         *Xhc
 740   )
 741 {
 742   return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
 743 }
 744
 745 /**
 746   Reset the XHCI host controller.
 747
 748   @param  Xhc          The XHCI device.
 749   @param  Timeout      Time to wait before abort (in millisecond, ms).
 750
 751   @retval EFI_SUCCESS  The XHCI host controller is reset.
 752   @return Others       Failed to reset the XHCI before Timeout.
 753
 754 **/
 755 EFI_STATUS
 756 XhcResetHC (
 757   IN USB_XHCI_DEV         *Xhc,
 758   IN UINT32               Timeout
 759   )
 760 {
 761   EFI_STATUS              Status;
 762
 763   DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
 764   //
 765   // Host can only be reset when it is halt. If not so, halt it
 766   //
 767   if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
 768     Status = XhcHaltHC (Xhc, Timeout);
 769
 770     if (EFI_ERROR (Status)) {
 771       return Status;
 772     }
 773   }
 774
 775   XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
 776   Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
 777   return Status;
 778 }
 779
 780
 781 /**
 782   Halt the XHCI host controller.
 783
 784   @param  Xhc          The XHCI device.
 785   @param  Timeout      Time to wait before abort (in millisecond, ms).
 786
 787   @return EFI_SUCCESS  The XHCI host controller is halt.
 788   @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.
 789
 790 **/
 791 EFI_STATUS
 792 XhcHaltHC (
 793   IN USB_XHCI_DEV        *Xhc,
 794   IN UINT32              Timeout
 795   )
 796 {
 797   EFI_STATUS              Status;
 798
 799   XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
 800   Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
 801   return Status;
 802 }
 803
 804
 805 /**
 806   Set the XHCI host controller to run.
 807
 808   @param  Xhc          The XHCI device.
 809   @param  Timeout      Time to wait before abort (in millisecond, ms).
 810
 811   @return EFI_SUCCESS  The XHCI host controller is running.
 812   @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.
 813
 814 **/
 815 EFI_STATUS
 816 XhcRunHC (
 817   IN USB_XHCI_DEV         *Xhc,
 818   IN UINT32               Timeout
 819   )
 820 {
 821   EFI_STATUS              Status;
 822
 823   XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
 824   Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
 825   return Status;
 826 }
 827