3 XHCI transfer scheduling routines.
5 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Create a command transfer TRB to support XHCI command interfaces.
21 @param Xhc The XHCI Instance.
22 @param CmdTrb The cmd TRB to be executed.
24 @return Created URB or NULL.
29 IN USB_XHCI_INSTANCE
*Xhc
,
30 IN TRB_TEMPLATE
*CmdTrb
35 Urb
= AllocateZeroPool (sizeof (URB
));
40 Urb
->Signature
= XHC_URB_SIG
;
42 Urb
->Ring
= &Xhc
->CmdRing
;
43 XhcSyncTrsRing (Xhc
, Urb
->Ring
);
45 Urb
->TrbStart
= Urb
->Ring
->RingEnqueue
;
46 CopyMem (Urb
->TrbStart
, CmdTrb
, sizeof (TRB_TEMPLATE
));
47 Urb
->TrbStart
->CycleBit
= Urb
->Ring
->RingPCS
& BIT0
;
48 Urb
->TrbEnd
= Urb
->TrbStart
;
54 Execute a XHCI cmd TRB pointed by CmdTrb.
56 @param Xhc The XHCI Instance.
57 @param CmdTrb The cmd TRB to be executed.
58 @param Timeout Indicates the maximum time, in millisecond, which the
59 transfer is allowed to complete.
60 @param EvtTrb The event TRB corresponding to the cmd TRB.
62 @retval EFI_SUCCESS The transfer was completed successfully.
63 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
64 @retval EFI_TIMEOUT The transfer failed due to timeout.
65 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
71 IN USB_XHCI_INSTANCE
*Xhc
,
72 IN TRB_TEMPLATE
*CmdTrb
,
74 OUT TRB_TEMPLATE
**EvtTrb
81 // Validate the parameters
83 if ((Xhc
== NULL
) || (CmdTrb
== NULL
)) {
84 return EFI_INVALID_PARAMETER
;
87 Status
= EFI_DEVICE_ERROR
;
89 if (XhcIsHalt (Xhc
) || XhcIsSysError (Xhc
)) {
90 DEBUG ((EFI_D_ERROR
, "XhcCmdTransfer: HC is halted\n"));
95 // Create a new URB, then poll the execution status.
97 Urb
= XhcCreateCmdTrb (Xhc
, CmdTrb
);
100 DEBUG ((EFI_D_ERROR
, "XhcCmdTransfer: failed to create URB\n"));
101 Status
= EFI_OUT_OF_RESOURCES
;
105 Status
= XhcExecTransfer (Xhc
, TRUE
, Urb
, Timeout
);
106 *EvtTrb
= Urb
->EvtTrb
;
108 if (Urb
->Result
== EFI_USB_NOERROR
) {
109 Status
= EFI_SUCCESS
;
112 XhcFreeUrb (Xhc
, Urb
);
119 Create a new URB for a new transaction.
121 @param Xhc The XHCI Instance
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
133 @return Created URB or NULL
138 IN USB_XHCI_INSTANCE
*Xhc
,
144 IN EFI_USB_DEVICE_REQUEST
*Request
,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,
155 Urb
= AllocateZeroPool (sizeof (URB
));
160 Urb
->Signature
= XHC_URB_SIG
;
161 InitializeListHead (&Urb
->UrbList
);
164 Ep
->BusAddr
= BusAddr
;
165 Ep
->EpAddr
= (UINT8
)(EpAddr
& 0x0F);
166 Ep
->Direction
= ((EpAddr
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
167 Ep
->DevSpeed
= DevSpeed
;
168 Ep
->MaxPacket
= MaxPacket
;
171 Urb
->Request
= Request
;
173 Urb
->DataLen
= DataLen
;
174 Urb
->Callback
= Callback
;
175 Urb
->Context
= Context
;
177 Status
= XhcCreateTransferTrb (Xhc
, Urb
);
178 ASSERT_EFI_ERROR (Status
);
179 if (EFI_ERROR (Status
)) {
180 DEBUG ((EFI_D_ERROR
, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status
));
189 Free an allocated URB.
191 @param Xhc The XHCI device.
192 @param Urb The URB to free.
197 IN USB_XHCI_INSTANCE
*Xhc
,
201 if ((Xhc
== NULL
) || (Urb
== NULL
)) {
205 if (Urb
->DataMap
!= NULL
) {
206 Xhc
->PciIo
->Unmap (Xhc
->PciIo
, Urb
->DataMap
);
213 Create a transfer TRB.
215 @param Xhc The XHCI Instance
216 @param Urb The urb used to construct the transfer TRB.
218 @return Created TRB or NULL
222 XhcCreateTransferTrb (
223 IN USB_XHCI_INSTANCE
*Xhc
,
228 TRANSFER_RING
*EPRing
;
236 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
237 EFI_PHYSICAL_ADDRESS PhyAddr
;
241 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
243 return EFI_DEVICE_ERROR
;
246 Urb
->Finished
= FALSE
;
247 Urb
->StartDone
= FALSE
;
248 Urb
->EndDone
= FALSE
;
250 Urb
->Result
= EFI_USB_NOERROR
;
252 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
254 EPRing
= (TRANSFER_RING
*)(UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1];
256 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
257 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
258 EPType
= (UINT8
) ((DEVICE_CONTEXT
*)OutputContext
)->EP
[Dci
-1].EPType
;
260 EPType
= (UINT8
) ((DEVICE_CONTEXT_64
*)OutputContext
)->EP
[Dci
-1].EPType
;
263 if (Urb
->Data
!= NULL
) {
264 if (((UINT8
) (Urb
->Ep
.Direction
)) == EfiUsbDataIn
) {
265 MapOp
= EfiPciIoOperationBusMasterWrite
;
267 MapOp
= EfiPciIoOperationBusMasterRead
;
271 Status
= Xhc
->PciIo
->Map (Xhc
->PciIo
, MapOp
, Urb
->Data
, &Len
, &PhyAddr
, &Map
);
273 if (EFI_ERROR (Status
) || (Len
!= Urb
->DataLen
)) {
274 DEBUG ((EFI_D_ERROR
, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
275 return EFI_OUT_OF_RESOURCES
;
278 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
285 XhcSyncTrsRing (Xhc
, EPRing
);
286 Urb
->TrbStart
= EPRing
->RingEnqueue
;
288 case ED_CONTROL_BIDIR
:
290 // For control transfer, create SETUP_STAGE_TRB first.
292 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
293 TrbStart
->TrbCtrSetup
.bmRequestType
= Urb
->Request
->RequestType
;
294 TrbStart
->TrbCtrSetup
.bRequest
= Urb
->Request
->Request
;
295 TrbStart
->TrbCtrSetup
.wValue
= Urb
->Request
->Value
;
296 TrbStart
->TrbCtrSetup
.wIndex
= Urb
->Request
->Index
;
297 TrbStart
->TrbCtrSetup
.wLength
= Urb
->Request
->Length
;
298 TrbStart
->TrbCtrSetup
.Length
= 8;
299 TrbStart
->TrbCtrSetup
.IntTarget
= 0;
300 TrbStart
->TrbCtrSetup
.IOC
= 1;
301 TrbStart
->TrbCtrSetup
.IDT
= 1;
302 TrbStart
->TrbCtrSetup
.Type
= TRB_TYPE_SETUP_STAGE
;
303 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
304 TrbStart
->TrbCtrSetup
.TRT
= 3;
305 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
306 TrbStart
->TrbCtrSetup
.TRT
= 2;
308 TrbStart
->TrbCtrSetup
.TRT
= 0;
311 // Update the cycle bit
313 TrbStart
->TrbCtrSetup
.CycleBit
= EPRing
->RingPCS
& BIT0
;
317 // For control transfer, create DATA_STAGE_TRB.
319 if (Urb
->DataLen
> 0) {
320 XhcSyncTrsRing (Xhc
, EPRing
);
321 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
322 TrbStart
->TrbCtrData
.TRBPtrLo
= XHC_LOW_32BIT(Urb
->DataPhy
);
323 TrbStart
->TrbCtrData
.TRBPtrHi
= XHC_HIGH_32BIT(Urb
->DataPhy
);
324 TrbStart
->TrbCtrData
.Length
= (UINT32
) Urb
->DataLen
;
325 TrbStart
->TrbCtrData
.TDSize
= 0;
326 TrbStart
->TrbCtrData
.IntTarget
= 0;
327 TrbStart
->TrbCtrData
.ISP
= 1;
328 TrbStart
->TrbCtrData
.IOC
= 1;
329 TrbStart
->TrbCtrData
.IDT
= 0;
330 TrbStart
->TrbCtrData
.CH
= 0;
331 TrbStart
->TrbCtrData
.Type
= TRB_TYPE_DATA_STAGE
;
332 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
333 TrbStart
->TrbCtrData
.DIR = 1;
334 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
335 TrbStart
->TrbCtrData
.DIR = 0;
337 TrbStart
->TrbCtrData
.DIR = 0;
340 // Update the cycle bit
342 TrbStart
->TrbCtrData
.CycleBit
= EPRing
->RingPCS
& BIT0
;
346 // For control transfer, create STATUS_STAGE_TRB.
347 // Get the pointer to next TRB for status stage use
349 XhcSyncTrsRing (Xhc
, EPRing
);
350 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
351 TrbStart
->TrbCtrStatus
.IntTarget
= 0;
352 TrbStart
->TrbCtrStatus
.IOC
= 1;
353 TrbStart
->TrbCtrStatus
.CH
= 0;
354 TrbStart
->TrbCtrStatus
.Type
= TRB_TYPE_STATUS_STAGE
;
355 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
356 TrbStart
->TrbCtrStatus
.DIR = 0;
357 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
358 TrbStart
->TrbCtrStatus
.DIR = 1;
360 TrbStart
->TrbCtrStatus
.DIR = 0;
363 // Update the cycle bit
365 TrbStart
->TrbCtrStatus
.CycleBit
= EPRing
->RingPCS
& BIT0
;
367 // Update the enqueue pointer
369 XhcSyncTrsRing (Xhc
, EPRing
);
371 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
380 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
381 while (TotalLen
< Urb
->DataLen
) {
382 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
383 Len
= Urb
->DataLen
- TotalLen
;
387 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
388 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
389 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
390 TrbStart
->TrbNormal
.Length
= (UINT32
) Len
;
391 TrbStart
->TrbNormal
.TDSize
= 0;
392 TrbStart
->TrbNormal
.IntTarget
= 0;
393 TrbStart
->TrbNormal
.ISP
= 1;
394 TrbStart
->TrbNormal
.IOC
= 1;
395 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
397 // Update the cycle bit
399 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
401 XhcSyncTrsRing (Xhc
, EPRing
);
406 Urb
->TrbNum
= TrbNum
;
407 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
410 case ED_INTERRUPT_OUT
:
411 case ED_INTERRUPT_IN
:
415 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
416 while (TotalLen
< Urb
->DataLen
) {
417 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
418 Len
= Urb
->DataLen
- TotalLen
;
422 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
423 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
424 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
425 TrbStart
->TrbNormal
.Length
= (UINT32
) Len
;
426 TrbStart
->TrbNormal
.TDSize
= 0;
427 TrbStart
->TrbNormal
.IntTarget
= 0;
428 TrbStart
->TrbNormal
.ISP
= 1;
429 TrbStart
->TrbNormal
.IOC
= 1;
430 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
432 // Update the cycle bit
434 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
436 XhcSyncTrsRing (Xhc
, EPRing
);
441 Urb
->TrbNum
= TrbNum
;
442 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
446 DEBUG ((EFI_D_INFO
, "Not supported EPType 0x%x!\n",EPType
));
456 Initialize the XHCI host controller for schedule.
458 @param Xhc The XHCI Instance to be initialized.
463 IN USB_XHCI_INSTANCE
*Xhc
467 EFI_PHYSICAL_ADDRESS DcbaaPhy
;
469 EFI_PHYSICAL_ADDRESS CmdRingPhy
;
471 UINT32 MaxScratchpadBufs
;
473 EFI_PHYSICAL_ADDRESS ScratchPhy
;
474 UINT64
*ScratchEntry
;
475 EFI_PHYSICAL_ADDRESS ScratchEntryPhy
;
477 UINTN
*ScratchEntryMap
;
481 // Initialize memory management.
483 Xhc
->MemPool
= UsbHcInitMemPool (Xhc
->PciIo
);
484 ASSERT (Xhc
->MemPool
!= NULL
);
487 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
488 // to enable the device slots that system software is going to use.
490 Xhc
->MaxSlotsEn
= Xhc
->HcSParams1
.Data
.MaxSlots
;
491 ASSERT (Xhc
->MaxSlotsEn
>= 1 && Xhc
->MaxSlotsEn
<= 255);
492 XhcWriteOpReg (Xhc
, XHC_CONFIG_OFFSET
, Xhc
->MaxSlotsEn
);
495 // The Device Context Base Address Array entry associated with each allocated Device Slot
496 // shall contain a 64-bit pointer to the base of the associated Device Context.
497 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
498 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
500 Entries
= (Xhc
->MaxSlotsEn
+ 1) * sizeof(UINT64
);
501 Dcbaa
= UsbHcAllocateMem (Xhc
->MemPool
, Entries
);
502 ASSERT (Dcbaa
!= NULL
);
503 ZeroMem (Dcbaa
, Entries
);
506 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
507 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
508 // mode (Run/Stop(R/S) ='1').
510 MaxScratchpadBufs
= ((Xhc
->HcSParams2
.Data
.ScratchBufHi
) << 5) | (Xhc
->HcSParams2
.Data
.ScratchBufLo
);
511 Xhc
->MaxScratchpadBufs
= MaxScratchpadBufs
;
512 ASSERT (MaxScratchpadBufs
<= 1023);
513 if (MaxScratchpadBufs
!= 0) {
515 // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
517 ScratchEntryMap
= AllocateZeroPool (sizeof (UINTN
) * MaxScratchpadBufs
);
518 ASSERT (ScratchEntryMap
!= NULL
);
519 Xhc
->ScratchEntryMap
= ScratchEntryMap
;
522 // Allocate the buffer to record the host address for each entry
524 ScratchEntry
= AllocateZeroPool (sizeof (UINT64
) * MaxScratchpadBufs
);
525 ASSERT (ScratchEntry
!= NULL
);
526 Xhc
->ScratchEntry
= ScratchEntry
;
529 Status
= UsbHcAllocateAlignedPages (
531 EFI_SIZE_TO_PAGES (MaxScratchpadBufs
* sizeof (UINT64
)),
533 (VOID
**) &ScratchBuf
,
537 ASSERT_EFI_ERROR (Status
);
539 ZeroMem (ScratchBuf
, MaxScratchpadBufs
* sizeof (UINT64
));
540 Xhc
->ScratchBuf
= ScratchBuf
;
543 // Allocate each scratch buffer
545 for (Index
= 0; Index
< MaxScratchpadBufs
; Index
++) {
547 Status
= UsbHcAllocateAlignedPages (
549 EFI_SIZE_TO_PAGES (Xhc
->PageSize
),
551 (VOID
**) &ScratchEntry
[Index
],
553 (VOID
**) &ScratchEntryMap
[Index
]
555 ASSERT_EFI_ERROR (Status
);
556 ZeroMem ((VOID
*)(UINTN
)ScratchEntry
[Index
], Xhc
->PageSize
);
558 // Fill with the PCI device address
560 *ScratchBuf
++ = ScratchEntryPhy
;
563 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
564 // Device Context Base Address Array points to the Scratchpad Buffer Array.
566 *(UINT64
*)Dcbaa
= (UINT64
)(UINTN
) ScratchPhy
;
570 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
571 // a 64-bit address pointing to where the Device Context Base Address Array is located.
573 Xhc
->DCBAA
= (UINT64
*)(UINTN
)Dcbaa
;
575 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
576 // So divide it to two 32-bytes width register access.
578 DcbaaPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Dcbaa
, Entries
);
579 XhcWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
, XHC_LOW_32BIT(DcbaaPhy
));
580 XhcWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
+ 4, XHC_HIGH_32BIT (DcbaaPhy
));
582 DEBUG ((EFI_D_INFO
, "XhcInitSched:DCBAA=0x%x\n", (UINT64
)(UINTN
)Xhc
->DCBAA
));
585 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
586 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
587 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
590 CreateTransferRing (Xhc
, CMD_RING_TRB_NUMBER
, &Xhc
->CmdRing
);
592 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
593 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
594 // So we set RCS as inverted PCS init value to let Command Ring empty
596 CmdRing
= (UINT64
)(UINTN
)Xhc
->CmdRing
.RingSeg0
;
597 CmdRingPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, (VOID
*)(UINTN
) CmdRing
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
598 ASSERT ((CmdRingPhy
& 0x3F) == 0);
599 CmdRingPhy
|= XHC_CRCR_RCS
;
601 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
602 // So divide it to two 32-bytes width register access.
604 XhcWriteOpReg (Xhc
, XHC_CRCR_OFFSET
, XHC_LOW_32BIT(CmdRingPhy
));
605 XhcWriteOpReg (Xhc
, XHC_CRCR_OFFSET
+ 4, XHC_HIGH_32BIT (CmdRingPhy
));
607 DEBUG ((EFI_D_INFO
, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc
->CmdRing
.RingSeg0
));
610 // Disable the 'interrupter enable' bit in USB_CMD
611 // and clear IE & IP bit in all Interrupter X Management Registers.
613 XhcClearOpRegBit (Xhc
, XHC_USBCMD_OFFSET
, XHC_USBCMD_INTE
);
614 for (Index
= 0; Index
< (UINT16
)(Xhc
->HcSParams1
.Data
.MaxIntrs
); Index
++) {
615 XhcClearRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IE
);
616 XhcSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IP
);
620 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
622 CreateEventRing (Xhc
, &Xhc
->EventRing
);
623 DEBUG ((EFI_D_INFO
, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc
->EventRing
.EventRingSeg0
));
627 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
628 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
629 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
630 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
631 Stopped to the Running state.
633 @param Xhc The XHCI Instance.
634 @param Urb The urb which makes the endpoint halted.
636 @retval EFI_SUCCESS The recovery is successful.
637 @retval Others Failed to recovery halted endpoint.
642 XhcRecoverHaltedEndpoint (
643 IN USB_XHCI_INSTANCE
*Xhc
,
651 Status
= EFI_SUCCESS
;
652 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
654 return EFI_DEVICE_ERROR
;
656 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
659 DEBUG ((EFI_D_INFO
, "Recovery Halted Slot = %x,Dci = %x\n", SlotId
, Dci
));
662 // 1) Send Reset endpoint command to transit from halt to stop state
664 Status
= XhcResetEndpoint(Xhc
, SlotId
, Dci
);
665 if (EFI_ERROR(Status
)) {
666 DEBUG ((EFI_D_ERROR
, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status
));
671 // 2)Set dequeue pointer
673 Status
= XhcSetTrDequeuePointer(Xhc
, SlotId
, Dci
, Urb
);
674 if (EFI_ERROR(Status
)) {
675 DEBUG ((EFI_D_ERROR
, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status
));
680 // 3)Ring the doorbell to transit from stop to active
682 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
689 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
690 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
691 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
694 @param Xhc The XHCI Instance.
695 @param Urb The urb which doesn't get completed in a specified timeout range.
697 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
698 @retval Others Failed to stop the endpoint and dequeue the TDs.
703 XhcDequeueTrbFromEndpoint (
704 IN USB_XHCI_INSTANCE
*Xhc
,
712 Status
= EFI_SUCCESS
;
713 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
715 return EFI_DEVICE_ERROR
;
717 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
720 DEBUG ((EFI_D_INFO
, "Stop Slot = %x,Dci = %x\n", SlotId
, Dci
));
723 // 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
725 Status
= XhcStopEndpoint(Xhc
, SlotId
, Dci
);
726 if (EFI_ERROR(Status
)) {
727 DEBUG ((EFI_D_ERROR
, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status
));
732 // 2)Set dequeue pointer
734 Status
= XhcSetTrDequeuePointer(Xhc
, SlotId
, Dci
, Urb
);
735 if (EFI_ERROR(Status
)) {
736 DEBUG ((EFI_D_ERROR
, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status
));
741 // 3)Ring the doorbell to transit from stop to active
743 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
750 Create XHCI event ring.
752 @param Xhc The XHCI Instance.
753 @param EventRing The created event ring.
758 IN USB_XHCI_INSTANCE
*Xhc
,
759 OUT EVENT_RING
*EventRing
763 EVENT_RING_SEG_TABLE_ENTRY
*ERSTBase
;
765 EFI_PHYSICAL_ADDRESS ERSTPhy
;
766 EFI_PHYSICAL_ADDRESS DequeuePhy
;
768 ASSERT (EventRing
!= NULL
);
770 Size
= sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
;
771 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
772 ASSERT (Buf
!= NULL
);
773 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
776 EventRing
->EventRingSeg0
= Buf
;
777 EventRing
->TrbNumber
= EVENT_RING_TRB_NUMBER
;
778 EventRing
->EventRingDequeue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
779 EventRing
->EventRingEnqueue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
781 DequeuePhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, Size
);
784 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
785 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
787 EventRing
->EventRingCCS
= 1;
789 Size
= sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
;
790 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
791 ASSERT (Buf
!= NULL
);
792 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
795 ERSTBase
= (EVENT_RING_SEG_TABLE_ENTRY
*) Buf
;
796 EventRing
->ERSTBase
= ERSTBase
;
797 ERSTBase
->PtrLo
= XHC_LOW_32BIT (DequeuePhy
);
798 ERSTBase
->PtrHi
= XHC_HIGH_32BIT (DequeuePhy
);
799 ERSTBase
->RingTrbSize
= EVENT_RING_TRB_NUMBER
;
801 ERSTPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, ERSTBase
, Size
);
804 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
812 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
814 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
815 // So divide it to two 32-bytes width register access.
820 XHC_LOW_32BIT((UINT64
)(UINTN
)DequeuePhy
)
825 XHC_HIGH_32BIT((UINT64
)(UINTN
)DequeuePhy
)
828 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
830 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
831 // So divide it to two 32-bytes width register access.
836 XHC_LOW_32BIT((UINT64
)(UINTN
)ERSTPhy
)
840 XHC_ERSTBA_OFFSET
+ 4,
841 XHC_HIGH_32BIT((UINT64
)(UINTN
)ERSTPhy
)
844 // Need set IMAN IE bit to enble the ring interrupt
846 XhcSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
, XHC_IMAN_IE
);
850 Create XHCI transfer ring.
852 @param Xhc The XHCI Instance.
853 @param TrbNum The number of TRB in the ring.
854 @param TransferRing The created transfer ring.
859 IN USB_XHCI_INSTANCE
*Xhc
,
861 OUT TRANSFER_RING
*TransferRing
866 EFI_PHYSICAL_ADDRESS PhyAddr
;
868 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (TRB_TEMPLATE
) * TrbNum
);
869 ASSERT (Buf
!= NULL
);
870 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
871 ZeroMem (Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
873 TransferRing
->RingSeg0
= Buf
;
874 TransferRing
->TrbNumber
= TrbNum
;
875 TransferRing
->RingEnqueue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
876 TransferRing
->RingDequeue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
877 TransferRing
->RingPCS
= 1;
879 // 4.9.2 Transfer Ring Management
880 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
881 // point to the first TRB in the ring.
883 EndTrb
= (LINK_TRB
*) ((UINTN
)Buf
+ sizeof (TRB_TEMPLATE
) * (TrbNum
- 1));
884 EndTrb
->Type
= TRB_TYPE_LINK
;
885 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
886 EndTrb
->PtrLo
= XHC_LOW_32BIT (PhyAddr
);
887 EndTrb
->PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
889 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
893 // Set Cycle bit as other TRB PCS init value
895 EndTrb
->CycleBit
= 0;
899 Free XHCI event ring.
901 @param Xhc The XHCI Instance.
902 @param EventRing The event ring to be freed.
908 IN USB_XHCI_INSTANCE
*Xhc
,
909 IN EVENT_RING
*EventRing
912 if(EventRing
->EventRingSeg0
== NULL
) {
917 // Free EventRing Segment 0
919 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->EventRingSeg0
, sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
);
924 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->ERSTBase
, sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
);
929 Free the resouce allocated at initializing schedule.
931 @param Xhc The XHCI Instance.
936 IN USB_XHCI_INSTANCE
*Xhc
940 UINT64
*ScratchEntry
;
942 if (Xhc
->ScratchBuf
!= NULL
) {
943 ScratchEntry
= Xhc
->ScratchEntry
;
944 for (Index
= 0; Index
< Xhc
->MaxScratchpadBufs
; Index
++) {
946 // Free Scratchpad Buffers
948 UsbHcFreeAlignedPages (Xhc
->PciIo
, (VOID
*)(UINTN
)ScratchEntry
[Index
], EFI_SIZE_TO_PAGES (Xhc
->PageSize
), (VOID
*) Xhc
->ScratchEntryMap
[Index
]);
951 // Free Scratchpad Buffer Array
953 UsbHcFreeAlignedPages (Xhc
->PciIo
, Xhc
->ScratchBuf
, EFI_SIZE_TO_PAGES (Xhc
->MaxScratchpadBufs
* sizeof (UINT64
)), Xhc
->ScratchMap
);
954 FreePool (Xhc
->ScratchEntryMap
);
955 FreePool (Xhc
->ScratchEntry
);
958 if (Xhc
->CmdRing
.RingSeg0
!= NULL
) {
959 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->CmdRing
.RingSeg0
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
960 Xhc
->CmdRing
.RingSeg0
= NULL
;
963 XhcFreeEventRing (Xhc
,&Xhc
->EventRing
);
965 if (Xhc
->DCBAA
!= NULL
) {
966 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->DCBAA
, (Xhc
->MaxSlotsEn
+ 1) * sizeof(UINT64
));
971 // Free memory pool at last
973 if (Xhc
->MemPool
!= NULL
) {
974 UsbHcFreeMemPool (Xhc
->MemPool
);
980 Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
982 @param Xhc The XHCI Instance.
983 @param Trb The TRB to be checked.
984 @param Urb The pointer to the matched Urb.
986 @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
987 @retval FALSE The Trb is not matched with any URBs in the async list.
992 IN USB_XHCI_INSTANCE
*Xhc
,
993 IN TRB_TEMPLATE
*Trb
,
999 TRB_TEMPLATE
*CheckedTrb
;
1003 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1004 CheckedUrb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1005 CheckedTrb
= CheckedUrb
->TrbStart
;
1006 for (Index
= 0; Index
< CheckedUrb
->TrbNum
; Index
++) {
1007 if (Trb
== CheckedTrb
) {
1013 // If the checked TRB is the link TRB at the end of the transfer ring,
1014 // recircle it to the head of the ring.
1016 if (CheckedTrb
->Type
== TRB_TYPE_LINK
) {
1017 CheckedTrb
= (TRB_TEMPLATE
*) CheckedUrb
->Ring
->RingSeg0
;
1026 Check if the Trb is a transaction of the URB.
1028 @param Trb The TRB to be checked
1029 @param Urb The transfer ring to be checked.
1031 @retval TRUE It is a transaction of the URB.
1032 @retval FALSE It is not any transaction of the URB.
1037 IN TRB_TEMPLATE
*Trb
,
1041 TRB_TEMPLATE
*CheckedTrb
;
1044 CheckedTrb
= Urb
->Ring
->RingSeg0
;
1046 ASSERT (Urb
->Ring
->TrbNumber
== CMD_RING_TRB_NUMBER
|| Urb
->Ring
->TrbNumber
== TR_RING_TRB_NUMBER
);
1048 for (Index
= 0; Index
< Urb
->Ring
->TrbNumber
; Index
++) {
1049 if (Trb
== CheckedTrb
) {
1059 Check the URB's execution result and update the URB's
1062 @param Xhc The XHCI Instance.
1063 @param Urb The URB to check result.
1065 @return Whether the result of URB transfer is finialized.
1070 IN USB_XHCI_INSTANCE
*Xhc
,
1074 EVT_TRB_TRANSFER
*EvtTrb
;
1075 TRB_TEMPLATE
*TRBPtr
;
1084 EFI_PHYSICAL_ADDRESS PhyAddr
;
1086 ASSERT ((Xhc
!= NULL
) && (Urb
!= NULL
));
1088 Status
= EFI_SUCCESS
;
1091 if (Urb
->Finished
) {
1097 if (XhcIsHalt (Xhc
) || XhcIsSysError (Xhc
)) {
1098 Urb
->Result
|= EFI_USB_ERR_SYSTEM
;
1103 // Traverse the event ring to find out all new events from the previous check.
1105 XhcSyncEventRing (Xhc
, &Xhc
->EventRing
);
1106 for (Index
= 0; Index
< Xhc
->EventRing
.TrbNumber
; Index
++) {
1107 Status
= XhcCheckNewEvent (Xhc
, &Xhc
->EventRing
, ((TRB_TEMPLATE
**)&EvtTrb
));
1108 if (Status
== EFI_NOT_READY
) {
1110 // All new events are handled, return directly.
1116 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
1118 if ((EvtTrb
->Type
!= TRB_TYPE_COMMAND_COMPLT_EVENT
) && (EvtTrb
->Type
!= TRB_TYPE_TRANS_EVENT
)) {
1123 // Need convert pci device address to host address
1125 PhyAddr
= (EFI_PHYSICAL_ADDRESS
)(EvtTrb
->TRBPtrLo
| LShiftU64 ((UINT64
) EvtTrb
->TRBPtrHi
, 32));
1126 TRBPtr
= (TRB_TEMPLATE
*)(UINTN
) UsbHcGetHostAddrForPciAddr (Xhc
->MemPool
, (VOID
*)(UINTN
) PhyAddr
, sizeof (TRB_TEMPLATE
));
1129 // Update the status of Urb according to the finished event regardless of whether
1130 // the urb is current checked one or in the XHCI's async transfer list.
1131 // This way is used to avoid that those completed async transfer events don't get
1132 // handled in time and are flushed by newer coming events.
1134 if (IsTransferRingTrb (TRBPtr
, Urb
)) {
1136 } else if (IsAsyncIntTrb (Xhc
, TRBPtr
, &AsyncUrb
)) {
1137 CheckedUrb
= AsyncUrb
;
1142 switch (EvtTrb
->Completecode
) {
1143 case TRB_COMPLETION_STALL_ERROR
:
1144 CheckedUrb
->Result
|= EFI_USB_ERR_STALL
;
1145 CheckedUrb
->Finished
= TRUE
;
1146 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1149 case TRB_COMPLETION_BABBLE_ERROR
:
1150 CheckedUrb
->Result
|= EFI_USB_ERR_BABBLE
;
1151 CheckedUrb
->Finished
= TRUE
;
1152 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1155 case TRB_COMPLETION_DATA_BUFFER_ERROR
:
1156 CheckedUrb
->Result
|= EFI_USB_ERR_BUFFER
;
1157 CheckedUrb
->Finished
= TRUE
;
1158 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb
->Completecode
));
1161 case TRB_COMPLETION_USB_TRANSACTION_ERROR
:
1162 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
1163 CheckedUrb
->Finished
= TRUE
;
1164 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1167 case TRB_COMPLETION_SHORT_PACKET
:
1168 case TRB_COMPLETION_SUCCESS
:
1169 if (EvtTrb
->Completecode
== TRB_COMPLETION_SHORT_PACKET
) {
1170 DEBUG ((EFI_D_VERBOSE
, "XhcCheckUrbResult: short packet happens!\n"));
1173 TRBType
= (UINT8
) (TRBPtr
->Type
);
1174 if ((TRBType
== TRB_TYPE_DATA_STAGE
) ||
1175 (TRBType
== TRB_TYPE_NORMAL
) ||
1176 (TRBType
== TRB_TYPE_ISOCH
)) {
1177 CheckedUrb
->Completed
+= (((TRANSFER_TRB_NORMAL
*)TRBPtr
)->Length
- EvtTrb
->Length
);
1183 DEBUG ((EFI_D_ERROR
, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb
->Completecode
));
1184 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
1185 CheckedUrb
->Finished
= TRUE
;
1190 // Only check first and end Trb event address
1192 if (TRBPtr
== CheckedUrb
->TrbStart
) {
1193 CheckedUrb
->StartDone
= TRUE
;
1196 if (TRBPtr
== CheckedUrb
->TrbEnd
) {
1197 CheckedUrb
->EndDone
= TRUE
;
1200 if (CheckedUrb
->StartDone
&& CheckedUrb
->EndDone
) {
1201 CheckedUrb
->Finished
= TRUE
;
1202 CheckedUrb
->EvtTrb
= (TRB_TEMPLATE
*)EvtTrb
;
1209 // Advance event ring to last available entry
1211 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1212 // So divide it to two 32-bytes width register access.
1214 Low
= XhcReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
);
1215 High
= XhcReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4);
1216 XhcDequeue
= (UINT64
)(LShiftU64((UINT64
)High
, 32) | Low
);
1218 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->EventRing
.EventRingDequeue
, sizeof (TRB_TEMPLATE
));
1220 if ((XhcDequeue
& (~0x0F)) != (PhyAddr
& (~0x0F))) {
1222 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1223 // So divide it to two 32-bytes width register access.
1225 XhcWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
, XHC_LOW_32BIT (PhyAddr
) | BIT3
);
1226 XhcWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4, XHC_HIGH_32BIT (PhyAddr
));
1229 return Urb
->Finished
;
1234 Execute the transfer by polling the URB. This is a synchronous operation.
1236 @param Xhc The XHCI Instance.
1237 @param CmdTransfer The executed URB is for cmd transfer or not.
1238 @param Urb The URB to execute.
1239 @param Timeout The time to wait before abort, in millisecond.
1241 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1242 @return EFI_TIMEOUT The transfer failed due to time out.
1243 @return EFI_SUCCESS The transfer finished OK.
1248 IN USB_XHCI_INSTANCE
*Xhc
,
1249 IN BOOLEAN CmdTransfer
,
1265 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1267 return EFI_DEVICE_ERROR
;
1269 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
1273 Status
= EFI_SUCCESS
;
1274 Loop
= Timeout
* XHC_1_MILLISECOND
;
1279 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
1281 for (Index
= 0; Index
< Loop
; Index
++) {
1282 Finished
= XhcCheckUrbResult (Xhc
, Urb
);
1286 gBS
->Stall (XHC_1_MICROSECOND
);
1289 if (Index
== Loop
) {
1290 Urb
->Result
= EFI_USB_ERR_TIMEOUT
;
1291 Status
= EFI_TIMEOUT
;
1292 } else if (Urb
->Result
!= EFI_USB_NOERROR
) {
1293 Status
= EFI_DEVICE_ERROR
;
1300 Delete a single asynchronous interrupt transfer for
1301 the device and endpoint.
1303 @param Xhc The XHCI Instance.
1304 @param BusAddr The logical device address assigned by UsbBus driver.
1305 @param EpNum The endpoint of the target.
1307 @retval EFI_SUCCESS An asynchronous transfer is removed.
1308 @retval EFI_NOT_FOUND No transfer for the device is found.
1312 XhciDelAsyncIntTransfer (
1313 IN USB_XHCI_INSTANCE
*Xhc
,
1321 EFI_USB_DATA_DIRECTION Direction
;
1324 Direction
= ((EpNum
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
1329 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1330 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1331 if ((Urb
->Ep
.BusAddr
== BusAddr
) &&
1332 (Urb
->Ep
.EpAddr
== EpNum
) &&
1333 (Urb
->Ep
.Direction
== Direction
)) {
1335 // Device doesn't finish the IntTransfer until real data comes
1336 // So the TRB should be removed as well.
1338 Status
= XhcDequeueTrbFromEndpoint (Xhc
, Urb
);
1339 if (EFI_ERROR (Status
)) {
1340 DEBUG ((EFI_D_ERROR
, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
1343 RemoveEntryList (&Urb
->UrbList
);
1344 FreePool (Urb
->Data
);
1345 XhcFreeUrb (Xhc
, Urb
);
1350 return EFI_NOT_FOUND
;
1354 Remove all the asynchronous interrutp transfers.
1356 @param Xhc The XHCI Instance.
1360 XhciDelAllAsyncIntTransfers (
1361 IN USB_XHCI_INSTANCE
*Xhc
1369 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1370 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1373 // Device doesn't finish the IntTransfer until real data comes
1374 // So the TRB should be removed as well.
1376 Status
= XhcDequeueTrbFromEndpoint (Xhc
, Urb
);
1377 if (EFI_ERROR (Status
)) {
1378 DEBUG ((EFI_D_ERROR
, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
1381 RemoveEntryList (&Urb
->UrbList
);
1382 FreePool (Urb
->Data
);
1383 XhcFreeUrb (Xhc
, Urb
);
1388 Update the queue head for next round of asynchronous transfer
1390 @param Xhc The XHCI Instance.
1391 @param Urb The URB to update
1395 XhcUpdateAsyncRequest (
1396 IN USB_XHCI_INSTANCE
*Xhc
,
1402 if (Urb
->Result
== EFI_USB_NOERROR
) {
1403 Status
= XhcCreateTransferTrb (Xhc
, Urb
);
1404 if (EFI_ERROR (Status
)) {
1407 Status
= RingIntTransferDoorBell (Xhc
, Urb
);
1408 if (EFI_ERROR (Status
)) {
1415 Flush data from PCI controller specific address to mapped system
1418 @param Xhc The XHCI device.
1419 @param Urb The URB to unmap.
1421 @retval EFI_SUCCESS Success to flush data to mapped system memory.
1422 @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.
1426 XhcFlushAsyncIntMap (
1427 IN USB_XHCI_INSTANCE
*Xhc
,
1432 EFI_PHYSICAL_ADDRESS PhyAddr
;
1433 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
1434 EFI_PCI_IO_PROTOCOL
*PciIo
;
1441 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
1442 MapOp
= EfiPciIoOperationBusMasterWrite
;
1444 MapOp
= EfiPciIoOperationBusMasterRead
;
1447 if (Urb
->DataMap
!= NULL
) {
1448 Status
= PciIo
->Unmap (PciIo
, Urb
->DataMap
);
1449 if (EFI_ERROR (Status
)) {
1454 Urb
->DataMap
= NULL
;
1456 Status
= PciIo
->Map (PciIo
, MapOp
, Urb
->Data
, &Len
, &PhyAddr
, &Map
);
1457 if (EFI_ERROR (Status
) || (Len
!= Urb
->DataLen
)) {
1461 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
1466 return EFI_DEVICE_ERROR
;
1470 Interrupt transfer periodic check handler.
1472 @param Event Interrupt event.
1473 @param Context Pointer to USB_XHCI_INSTANCE.
1478 XhcMonitorAsyncRequests (
1483 USB_XHCI_INSTANCE
*Xhc
;
1492 OldTpl
= gBS
->RaiseTPL (XHC_TPL
);
1494 Xhc
= (USB_XHCI_INSTANCE
*) Context
;
1496 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1497 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1500 // Make sure that the device is available before every check.
1502 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1508 // Check the result of URB execution. If it is still
1509 // active, check the next one.
1511 XhcCheckUrbResult (Xhc
, Urb
);
1513 if (!Urb
->Finished
) {
1518 // Flush any PCI posted write transactions from a PCI host
1519 // bridge to system memory.
1521 Status
= XhcFlushAsyncIntMap (Xhc
, Urb
);
1522 if (EFI_ERROR (Status
)) {
1523 DEBUG ((EFI_D_ERROR
, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
1527 // Allocate a buffer then copy the transferred data for user.
1528 // If failed to allocate the buffer, update the URB for next
1529 // round of transfer. Ignore the data of this round.
1532 if (Urb
->Result
== EFI_USB_NOERROR
) {
1533 ASSERT (Urb
->Completed
<= Urb
->DataLen
);
1535 ProcBuf
= AllocateZeroPool (Urb
->Completed
);
1537 if (ProcBuf
== NULL
) {
1538 XhcUpdateAsyncRequest (Xhc
, Urb
);
1542 CopyMem (ProcBuf
, Urb
->Data
, Urb
->Completed
);
1546 // Leave error recovery to its related device driver. A
1547 // common case of the error recovery is to re-submit the
1548 // interrupt transfer which is linked to the head of the
1549 // list. This function scans from head to tail. So the
1550 // re-submitted interrupt transfer's callback function
1551 // will not be called again in this round. Don't touch this
1552 // URB after the callback, it may have been removed by the
1555 if (Urb
->Callback
!= NULL
) {
1557 // Restore the old TPL, USB bus maybe connect device in
1558 // his callback. Some drivers may has a lower TPL restriction.
1560 gBS
->RestoreTPL (OldTpl
);
1561 (Urb
->Callback
) (ProcBuf
, Urb
->Completed
, Urb
->Context
, Urb
->Result
);
1562 OldTpl
= gBS
->RaiseTPL (XHC_TPL
);
1565 if (ProcBuf
!= NULL
) {
1566 gBS
->FreePool (ProcBuf
);
1569 XhcUpdateAsyncRequest (Xhc
, Urb
);
1571 gBS
->RestoreTPL (OldTpl
);
1575 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1577 @param Xhc The XHCI Instance.
1578 @param ParentRouteChart The route string pointed to the parent device if it exists.
1579 @param Port The port to be polled.
1580 @param PortState The port state.
1582 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1583 @retval Others Should not appear.
1588 XhcPollPortStatusChange (
1589 IN USB_XHCI_INSTANCE
*Xhc
,
1590 IN USB_DEV_ROUTE ParentRouteChart
,
1592 IN EFI_USB_PORT_STATUS
*PortState
1598 USB_DEV_ROUTE RouteChart
;
1600 Status
= EFI_SUCCESS
;
1602 if ((PortState
->PortChangeStatus
& (USB_PORT_STAT_C_CONNECTION
| USB_PORT_STAT_C_ENABLE
| USB_PORT_STAT_C_OVERCURRENT
| USB_PORT_STAT_C_RESET
)) == 0) {
1606 if (ParentRouteChart
.Dword
== 0) {
1607 RouteChart
.Route
.RouteString
= 0;
1608 RouteChart
.Route
.RootPortNum
= Port
+ 1;
1609 RouteChart
.Route
.TierNum
= 1;
1612 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (Port
<< (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
1614 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (15 << (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
1616 RouteChart
.Route
.RootPortNum
= ParentRouteChart
.Route
.RootPortNum
;
1617 RouteChart
.Route
.TierNum
= ParentRouteChart
.Route
.TierNum
+ 1;
1620 SlotId
= XhcRouteStringToSlotId (Xhc
, RouteChart
);
1622 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
1623 Status
= XhcDisableSlotCmd (Xhc
, SlotId
);
1625 Status
= XhcDisableSlotCmd64 (Xhc
, SlotId
);
1629 if (((PortState
->PortStatus
& USB_PORT_STAT_ENABLE
) != 0) &&
1630 ((PortState
->PortStatus
& USB_PORT_STAT_CONNECTION
) != 0)) {
1632 // Has a device attached, Identify device speed after port is enabled.
1634 Speed
= EFI_USB_SPEED_FULL
;
1635 if ((PortState
->PortStatus
& USB_PORT_STAT_LOW_SPEED
) != 0) {
1636 Speed
= EFI_USB_SPEED_LOW
;
1637 } else if ((PortState
->PortStatus
& USB_PORT_STAT_HIGH_SPEED
) != 0) {
1638 Speed
= EFI_USB_SPEED_HIGH
;
1639 } else if ((PortState
->PortStatus
& USB_PORT_STAT_SUPER_SPEED
) != 0) {
1640 Speed
= EFI_USB_SPEED_SUPER
;
1643 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1645 SlotId
= XhcRouteStringToSlotId (Xhc
, RouteChart
);
1646 if ((SlotId
== 0) && ((PortState
->PortChangeStatus
& USB_PORT_STAT_C_RESET
) != 0)) {
1647 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
1648 Status
= XhcInitializeDeviceSlot (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
1650 Status
= XhcInitializeDeviceSlot64 (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
1660 Calculate the device context index by endpoint address and direction.
1662 @param EpAddr The target endpoint number.
1663 @param Direction The direction of the target endpoint.
1665 @return The device context index of endpoint.
1679 Index
= (UINT8
) (2 * EpAddr
);
1680 if (Direction
== EfiUsbDataIn
) {
1688 Find out the actual device address according to the requested device address from UsbBus.
1690 @param Xhc The XHCI Instance.
1691 @param BusDevAddr The requested device address by UsbBus upper driver.
1693 @return The actual device address assigned to the device.
1698 XhcBusDevAddrToSlotId (
1699 IN USB_XHCI_INSTANCE
*Xhc
,
1705 for (Index
= 0; Index
< 255; Index
++) {
1706 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
1707 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
1708 (Xhc
->UsbDevContext
[Index
+ 1].BusDevAddr
== BusDevAddr
)) {
1717 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
1721 Find out the slot id according to the device's route string.
1723 @param Xhc The XHCI Instance.
1724 @param RouteString The route string described the device location.
1726 @return The slot id used by the device.
1731 XhcRouteStringToSlotId (
1732 IN USB_XHCI_INSTANCE
*Xhc
,
1733 IN USB_DEV_ROUTE RouteString
1738 for (Index
= 0; Index
< 255; Index
++) {
1739 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
1740 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
1741 (Xhc
->UsbDevContext
[Index
+ 1].RouteString
.Dword
== RouteString
.Dword
)) {
1750 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
1754 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1756 @param Xhc The XHCI Instance.
1757 @param EvtRing The event ring to sync.
1759 @retval EFI_SUCCESS The event ring is synchronized successfully.
1765 IN USB_XHCI_INSTANCE
*Xhc
,
1766 IN EVENT_RING
*EvtRing
1770 TRB_TEMPLATE
*EvtTrb1
;
1772 ASSERT (EvtRing
!= NULL
);
1775 // Calculate the EventRingEnqueue and EventRingCCS.
1776 // Note: only support single Segment
1778 EvtTrb1
= EvtRing
->EventRingDequeue
;
1780 for (Index
= 0; Index
< EvtRing
->TrbNumber
; Index
++) {
1781 if (EvtTrb1
->CycleBit
!= EvtRing
->EventRingCCS
) {
1787 if ((UINTN
)EvtTrb1
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
1788 EvtTrb1
= EvtRing
->EventRingSeg0
;
1789 EvtRing
->EventRingCCS
= (EvtRing
->EventRingCCS
) ? 0 : 1;
1793 if (Index
< EvtRing
->TrbNumber
) {
1794 EvtRing
->EventRingEnqueue
= EvtTrb1
;
1803 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1805 @param Xhc The XHCI Instance.
1806 @param TrsRing The transfer ring to sync.
1808 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1814 IN USB_XHCI_INSTANCE
*Xhc
,
1815 IN TRANSFER_RING
*TrsRing
1819 TRB_TEMPLATE
*TrsTrb
;
1821 ASSERT (TrsRing
!= NULL
);
1823 // Calculate the latest RingEnqueue and RingPCS
1825 TrsTrb
= TrsRing
->RingEnqueue
;
1826 ASSERT (TrsTrb
!= NULL
);
1828 for (Index
= 0; Index
< TrsRing
->TrbNumber
; Index
++) {
1829 if (TrsTrb
->CycleBit
!= (TrsRing
->RingPCS
& BIT0
)) {
1833 if ((UINT8
) TrsTrb
->Type
== TRB_TYPE_LINK
) {
1834 ASSERT (((LINK_TRB
*)TrsTrb
)->TC
!= 0);
1836 // set cycle bit in Link TRB as normal
1838 ((LINK_TRB
*)TrsTrb
)->CycleBit
= TrsRing
->RingPCS
& BIT0
;
1840 // Toggle PCS maintained by software
1842 TrsRing
->RingPCS
= (TrsRing
->RingPCS
& BIT0
) ? 0 : 1;
1843 TrsTrb
= (TRB_TEMPLATE
*) TrsRing
->RingSeg0
; // Use host address
1847 ASSERT (Index
!= TrsRing
->TrbNumber
);
1849 if (TrsTrb
!= TrsRing
->RingEnqueue
) {
1850 TrsRing
->RingEnqueue
= TrsTrb
;
1854 // Clear the Trb context for enqueue, but reserve the PCS bit
1856 TrsTrb
->Parameter1
= 0;
1857 TrsTrb
->Parameter2
= 0;
1861 TrsTrb
->Control
= 0;
1867 Check if there is a new generated event.
1869 @param Xhc The XHCI Instance.
1870 @param EvtRing The event ring to check.
1871 @param NewEvtTrb The new event TRB found.
1873 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1874 @retval EFI_NOT_READY The event ring has no new event.
1880 IN USB_XHCI_INSTANCE
*Xhc
,
1881 IN EVENT_RING
*EvtRing
,
1882 OUT TRB_TEMPLATE
**NewEvtTrb
1885 ASSERT (EvtRing
!= NULL
);
1887 *NewEvtTrb
= EvtRing
->EventRingDequeue
;
1889 if (EvtRing
->EventRingDequeue
== EvtRing
->EventRingEnqueue
) {
1890 return EFI_NOT_READY
;
1893 EvtRing
->EventRingDequeue
++;
1895 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1897 if ((UINTN
)EvtRing
->EventRingDequeue
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
1898 EvtRing
->EventRingDequeue
= EvtRing
->EventRingSeg0
;
1905 Ring the door bell to notify XHCI there is a transaction to be executed.
1907 @param Xhc The XHCI Instance.
1908 @param SlotId The slot id of the target device.
1909 @param Dci The device context index of the target slot or endpoint.
1911 @retval EFI_SUCCESS Successfully ring the door bell.
1917 IN USB_XHCI_INSTANCE
*Xhc
,
1923 XhcWriteDoorBellReg (Xhc
, 0, 0);
1925 XhcWriteDoorBellReg (Xhc
, SlotId
* sizeof (UINT32
), Dci
);
1932 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1934 @param Xhc The XHCI Instance.
1935 @param Urb The URB to be rung.
1937 @retval EFI_SUCCESS Successfully ring the door bell.
1941 RingIntTransferDoorBell (
1942 IN USB_XHCI_INSTANCE
*Xhc
,
1949 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1950 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
1951 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
1956 Assign and initialize the device slot for a new device.
1958 @param Xhc The XHCI Instance.
1959 @param ParentRouteChart The route string pointed to the parent device.
1960 @param ParentPort The port at which the device is located.
1961 @param RouteChart The route string pointed to the device.
1962 @param DeviceSpeed The device speed.
1964 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1969 XhcInitializeDeviceSlot (
1970 IN USB_XHCI_INSTANCE
*Xhc
,
1971 IN USB_DEV_ROUTE ParentRouteChart
,
1972 IN UINT16 ParentPort
,
1973 IN USB_DEV_ROUTE RouteChart
,
1974 IN UINT8 DeviceSpeed
1978 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
1979 INPUT_CONTEXT
*InputContext
;
1980 DEVICE_CONTEXT
*OutputContext
;
1981 TRANSFER_RING
*EndpointTransferRing
;
1982 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
1983 UINT8 DeviceAddress
;
1984 CMD_TRB_ENABLE_SLOT CmdTrb
;
1987 DEVICE_CONTEXT
*ParentDeviceContext
;
1988 EFI_PHYSICAL_ADDRESS PhyAddr
;
1990 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
1991 CmdTrb
.CycleBit
= 1;
1992 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
1994 Status
= XhcCmdTransfer (
1996 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
1997 XHC_GENERIC_TIMEOUT
,
1998 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2000 if (EFI_ERROR (Status
)) {
2001 DEBUG ((EFI_D_ERROR
, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status
));
2004 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
2005 DEBUG ((EFI_D_INFO
, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
2006 SlotId
= (UINT8
)EvtTrb
->SlotId
;
2007 ASSERT (SlotId
!= 0);
2009 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
2010 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
2011 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
2012 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
2013 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
2016 // 4.3.3 Device Slot Initialization
2017 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2019 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT
));
2020 ASSERT (InputContext
!= NULL
);
2021 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
2022 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2024 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
2027 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2028 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2029 // Context are affected by the command.
2031 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
2034 // 3) Initialize the Input Slot Context data structure
2036 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
2037 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
2038 InputContext
->Slot
.ContextEntries
= 1;
2039 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
2041 if (RouteChart
.Route
.RouteString
) {
2043 // The device is behind of hub device.
2045 ParentSlotId
= XhcRouteStringToSlotId(Xhc
, ParentRouteChart
);
2046 ASSERT (ParentSlotId
!= 0);
2048 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2050 ParentDeviceContext
= (DEVICE_CONTEXT
*)Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
2051 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
2052 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
2053 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
2055 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2056 // environment from Full/Low speed signaling environment for a device
2058 InputContext
->Slot
.TTPortNum
= ParentPort
;
2059 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
2063 // Inherit the TT parameters from parent device.
2065 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
2066 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
2068 // If the device is a High speed device then down the speed to be the same as its parent Hub
2070 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2071 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
2077 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2079 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
2080 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
2081 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
2083 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2085 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
2087 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2088 InputContext
->EP
[0].MaxPacketSize
= 512;
2089 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2090 InputContext
->EP
[0].MaxPacketSize
= 64;
2092 InputContext
->EP
[0].MaxPacketSize
= 8;
2095 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2096 // 1KB, and Bulk and Isoch endpoints 3KB.
2098 InputContext
->EP
[0].AverageTRBLength
= 8;
2099 InputContext
->EP
[0].MaxBurstSize
= 0;
2100 InputContext
->EP
[0].Interval
= 0;
2101 InputContext
->EP
[0].MaxPStreams
= 0;
2102 InputContext
->EP
[0].Mult
= 0;
2103 InputContext
->EP
[0].CErr
= 3;
2106 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2108 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2110 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
2111 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2113 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
2114 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2117 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2119 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT
));
2120 ASSERT (OutputContext
!= NULL
);
2121 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
2122 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT
));
2124 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
2126 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2127 // a pointer to the Output Device Context data structure (6.2.1).
2129 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT
));
2131 // Fill DCBAA with PCI device address
2133 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
2136 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2137 // Context data structure described above.
2139 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2142 gBS
->Stall (XHC_RESET_RECOVERY_DELAY
);
2143 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
2144 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
2145 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2146 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2147 CmdTrbAddr
.CycleBit
= 1;
2148 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
2149 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2150 Status
= XhcCmdTransfer (
2152 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
2153 XHC_GENERIC_TIMEOUT
,
2154 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2156 if (!EFI_ERROR (Status
)) {
2157 DeviceAddress
= (UINT8
) ((DEVICE_CONTEXT
*) OutputContext
)->Slot
.DeviceAddress
;
2158 DEBUG ((EFI_D_INFO
, " Address %d assigned successfully\n", DeviceAddress
));
2159 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
2166 Assign and initialize the device slot for a new device.
2168 @param Xhc The XHCI Instance.
2169 @param ParentRouteChart The route string pointed to the parent device.
2170 @param ParentPort The port at which the device is located.
2171 @param RouteChart The route string pointed to the device.
2172 @param DeviceSpeed The device speed.
2174 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
2179 XhcInitializeDeviceSlot64 (
2180 IN USB_XHCI_INSTANCE
*Xhc
,
2181 IN USB_DEV_ROUTE ParentRouteChart
,
2182 IN UINT16 ParentPort
,
2183 IN USB_DEV_ROUTE RouteChart
,
2184 IN UINT8 DeviceSpeed
2188 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2189 INPUT_CONTEXT_64
*InputContext
;
2190 DEVICE_CONTEXT_64
*OutputContext
;
2191 TRANSFER_RING
*EndpointTransferRing
;
2192 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
2193 UINT8 DeviceAddress
;
2194 CMD_TRB_ENABLE_SLOT CmdTrb
;
2197 DEVICE_CONTEXT_64
*ParentDeviceContext
;
2198 EFI_PHYSICAL_ADDRESS PhyAddr
;
2200 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
2201 CmdTrb
.CycleBit
= 1;
2202 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
2204 Status
= XhcCmdTransfer (
2206 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
2207 XHC_GENERIC_TIMEOUT
,
2208 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2210 if (EFI_ERROR (Status
)) {
2211 DEBUG ((EFI_D_ERROR
, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status
));
2214 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
2215 DEBUG ((EFI_D_INFO
, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
2216 SlotId
= (UINT8
)EvtTrb
->SlotId
;
2217 ASSERT (SlotId
!= 0);
2219 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
2220 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
2221 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
2222 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
2223 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
2226 // 4.3.3 Device Slot Initialization
2227 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2229 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT_64
));
2230 ASSERT (InputContext
!= NULL
);
2231 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
2232 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2234 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
2237 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2238 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2239 // Context are affected by the command.
2241 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
2244 // 3) Initialize the Input Slot Context data structure
2246 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
2247 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
2248 InputContext
->Slot
.ContextEntries
= 1;
2249 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
2251 if (RouteChart
.Route
.RouteString
) {
2253 // The device is behind of hub device.
2255 ParentSlotId
= XhcRouteStringToSlotId(Xhc
, ParentRouteChart
);
2256 ASSERT (ParentSlotId
!= 0);
2258 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2260 ParentDeviceContext
= (DEVICE_CONTEXT_64
*)Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
2261 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
2262 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
2263 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
2265 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2266 // environment from Full/Low speed signaling environment for a device
2268 InputContext
->Slot
.TTPortNum
= ParentPort
;
2269 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
2273 // Inherit the TT parameters from parent device.
2275 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
2276 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
2278 // If the device is a High speed device then down the speed to be the same as its parent Hub
2280 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2281 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
2287 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2289 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
2290 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
2291 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
2293 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2295 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
2297 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2298 InputContext
->EP
[0].MaxPacketSize
= 512;
2299 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2300 InputContext
->EP
[0].MaxPacketSize
= 64;
2302 InputContext
->EP
[0].MaxPacketSize
= 8;
2305 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2306 // 1KB, and Bulk and Isoch endpoints 3KB.
2308 InputContext
->EP
[0].AverageTRBLength
= 8;
2309 InputContext
->EP
[0].MaxBurstSize
= 0;
2310 InputContext
->EP
[0].Interval
= 0;
2311 InputContext
->EP
[0].MaxPStreams
= 0;
2312 InputContext
->EP
[0].Mult
= 0;
2313 InputContext
->EP
[0].CErr
= 3;
2316 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2318 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2320 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
2321 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2323 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
2324 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2327 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2329 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT_64
));
2330 ASSERT (OutputContext
!= NULL
);
2331 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
2332 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2334 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
2336 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2337 // a pointer to the Output Device Context data structure (6.2.1).
2339 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2341 // Fill DCBAA with PCI device address
2343 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
2346 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2347 // Context data structure described above.
2349 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2352 gBS
->Stall (XHC_RESET_RECOVERY_DELAY
);
2353 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
2354 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
2355 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2356 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2357 CmdTrbAddr
.CycleBit
= 1;
2358 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
2359 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2360 Status
= XhcCmdTransfer (
2362 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
2363 XHC_GENERIC_TIMEOUT
,
2364 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2366 if (!EFI_ERROR (Status
)) {
2367 DeviceAddress
= (UINT8
) ((DEVICE_CONTEXT_64
*) OutputContext
)->Slot
.DeviceAddress
;
2368 DEBUG ((EFI_D_INFO
, " Address %d assigned successfully\n", DeviceAddress
));
2369 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
2376 Disable the specified device slot.
2378 @param Xhc The XHCI Instance.
2379 @param SlotId The slot id to be disabled.
2381 @retval EFI_SUCCESS Successfully disable the device slot.
2387 IN USB_XHCI_INSTANCE
*Xhc
,
2392 TRB_TEMPLATE
*EvtTrb
;
2393 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
2398 // Disable the device slots occupied by these devices on its downstream ports.
2399 // Entry 0 is reserved.
2401 for (Index
= 0; Index
< 255; Index
++) {
2402 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
2403 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
2404 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
2408 Status
= XhcDisableSlotCmd (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
2410 if (EFI_ERROR (Status
)) {
2411 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2412 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
2417 // Construct the disable slot command
2419 DEBUG ((EFI_D_INFO
, "Disable device slot %d!\n", SlotId
));
2421 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
2422 CmdTrbDisSlot
.CycleBit
= 1;
2423 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
2424 CmdTrbDisSlot
.SlotId
= SlotId
;
2425 Status
= XhcCmdTransfer (
2427 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
2428 XHC_GENERIC_TIMEOUT
,
2429 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2431 if (EFI_ERROR (Status
)) {
2432 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
2436 // Free the slot's device context entry
2438 Xhc
->DCBAA
[SlotId
] = 0;
2441 // Free the slot related data structure
2443 for (Index
= 0; Index
< 31; Index
++) {
2444 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
2445 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
2446 if (RingSeg
!= NULL
) {
2447 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
2449 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
2450 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
2454 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
2455 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
2456 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
2460 if (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
!= NULL
) {
2461 FreePool (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
);
2464 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
2465 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
2468 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
2469 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT
));
2472 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2473 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2474 // remove urb from XHCI's asynchronous transfer list.
2476 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
2477 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
2483 Disable the specified device slot.
2485 @param Xhc The XHCI Instance.
2486 @param SlotId The slot id to be disabled.
2488 @retval EFI_SUCCESS Successfully disable the device slot.
2493 XhcDisableSlotCmd64 (
2494 IN USB_XHCI_INSTANCE
*Xhc
,
2499 TRB_TEMPLATE
*EvtTrb
;
2500 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
2505 // Disable the device slots occupied by these devices on its downstream ports.
2506 // Entry 0 is reserved.
2508 for (Index
= 0; Index
< 255; Index
++) {
2509 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
2510 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
2511 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
2515 Status
= XhcDisableSlotCmd64 (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
2517 if (EFI_ERROR (Status
)) {
2518 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2519 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
2524 // Construct the disable slot command
2526 DEBUG ((EFI_D_INFO
, "Disable device slot %d!\n", SlotId
));
2528 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
2529 CmdTrbDisSlot
.CycleBit
= 1;
2530 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
2531 CmdTrbDisSlot
.SlotId
= SlotId
;
2532 Status
= XhcCmdTransfer (
2534 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
2535 XHC_GENERIC_TIMEOUT
,
2536 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2538 if (EFI_ERROR (Status
)) {
2539 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
2543 // Free the slot's device context entry
2545 Xhc
->DCBAA
[SlotId
] = 0;
2548 // Free the slot related data structure
2550 for (Index
= 0; Index
< 31; Index
++) {
2551 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
2552 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
2553 if (RingSeg
!= NULL
) {
2554 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
2556 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
2557 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
2561 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
2562 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
2563 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
2567 if (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
!= NULL
) {
2568 FreePool (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
);
2571 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
2572 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
2575 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
2576 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2579 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2580 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2581 // remove urb from XHCI's asynchronous transfer list.
2583 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
2584 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
2590 Initialize endpoint context in input context.
2592 @param Xhc The XHCI Instance.
2593 @param SlotId The slot id to be configured.
2594 @param DeviceSpeed The device's speed.
2595 @param InputContext The pointer to the input context.
2596 @param IfDesc The pointer to the usb device interface descriptor.
2598 @return The maximum device context index of endpoint.
2603 XhcInitializeEndpointContext (
2604 IN USB_XHCI_INSTANCE
*Xhc
,
2606 IN UINT8 DeviceSpeed
,
2607 IN INPUT_CONTEXT
*InputContext
,
2608 IN USB_INTERFACE_DESCRIPTOR
*IfDesc
2611 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
2618 EFI_PHYSICAL_ADDRESS PhyAddr
;
2620 TRANSFER_RING
*EndpointTransferRing
;
2624 NumEp
= IfDesc
->NumEndpoints
;
2626 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)(IfDesc
+ 1);
2627 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
2628 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
2629 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2632 if (EpDesc
->Length
< sizeof (USB_ENDPOINT_DESCRIPTOR
)) {
2633 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2637 EpAddr
= (UINT8
)(EpDesc
->EndpointAddress
& 0x0F);
2638 Direction
= (UINT8
)((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
2640 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
2646 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
2647 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
2649 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2651 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2653 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2655 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2658 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
2659 case USB_ENDPOINT_BULK
:
2660 if (Direction
== EfiUsbDataIn
) {
2661 InputContext
->EP
[Dci
-1].CErr
= 3;
2662 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
2664 InputContext
->EP
[Dci
-1].CErr
= 3;
2665 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
2668 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2669 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2670 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2671 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2672 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2676 case USB_ENDPOINT_ISO
:
2677 if (Direction
== EfiUsbDataIn
) {
2678 InputContext
->EP
[Dci
-1].CErr
= 0;
2679 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
2681 InputContext
->EP
[Dci
-1].CErr
= 0;
2682 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
2685 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2686 // Refer to XHCI 1.1 spec section 6.2.3.6.
2688 if (DeviceSpeed
== EFI_USB_SPEED_FULL
) {
2689 Interval
= EpDesc
->Interval
;
2690 ASSERT (Interval
>= 1 && Interval
<= 16);
2691 InputContext
->EP
[Dci
-1].Interval
= Interval
+ 2;
2692 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2693 Interval
= EpDesc
->Interval
;
2694 ASSERT (Interval
>= 1 && Interval
<= 16);
2695 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2699 // Do not support isochronous transfer now.
2701 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2702 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2704 case USB_ENDPOINT_INTERRUPT
:
2705 if (Direction
== EfiUsbDataIn
) {
2706 InputContext
->EP
[Dci
-1].CErr
= 3;
2707 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
2709 InputContext
->EP
[Dci
-1].CErr
= 3;
2710 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
2712 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2713 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
2715 // Get the bInterval from descriptor and init the the interval field of endpoint context
2717 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
2718 Interval
= EpDesc
->Interval
;
2720 // Calculate through the bInterval field of Endpoint descriptor.
2722 ASSERT (Interval
!= 0);
2723 InputContext
->EP
[Dci
-1].Interval
= (UINT32
)HighBitSet32((UINT32
)Interval
) + 3;
2724 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2725 Interval
= EpDesc
->Interval
;
2726 ASSERT (Interval
>= 1 && Interval
<= 16);
2728 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2730 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2731 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2732 InputContext
->EP
[Dci
-1].MaxESITPayload
= 0x0002;
2733 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2734 InputContext
->EP
[Dci
-1].CErr
= 3;
2737 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2738 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2739 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2740 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2744 case USB_ENDPOINT_CONTROL
:
2746 // Do not support control transfer now.
2748 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2750 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
2751 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2755 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2757 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
2758 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2760 PhyAddr
&= ~((EFI_PHYSICAL_ADDRESS
)0x0F);
2761 PhyAddr
|= (EFI_PHYSICAL_ADDRESS
)((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
2762 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2763 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2765 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2772 Initialize endpoint context in input context.
2774 @param Xhc The XHCI Instance.
2775 @param SlotId The slot id to be configured.
2776 @param DeviceSpeed The device's speed.
2777 @param InputContext The pointer to the input context.
2778 @param IfDesc The pointer to the usb device interface descriptor.
2780 @return The maximum device context index of endpoint.
2785 XhcInitializeEndpointContext64 (
2786 IN USB_XHCI_INSTANCE
*Xhc
,
2788 IN UINT8 DeviceSpeed
,
2789 IN INPUT_CONTEXT_64
*InputContext
,
2790 IN USB_INTERFACE_DESCRIPTOR
*IfDesc
2793 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
2800 EFI_PHYSICAL_ADDRESS PhyAddr
;
2802 TRANSFER_RING
*EndpointTransferRing
;
2806 NumEp
= IfDesc
->NumEndpoints
;
2808 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)(IfDesc
+ 1);
2809 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
2810 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
2811 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2814 if (EpDesc
->Length
< sizeof (USB_ENDPOINT_DESCRIPTOR
)) {
2815 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2819 EpAddr
= (UINT8
)(EpDesc
->EndpointAddress
& 0x0F);
2820 Direction
= (UINT8
)((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
2822 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
2828 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
2829 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
2831 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2833 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2835 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2837 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2840 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
2841 case USB_ENDPOINT_BULK
:
2842 if (Direction
== EfiUsbDataIn
) {
2843 InputContext
->EP
[Dci
-1].CErr
= 3;
2844 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
2846 InputContext
->EP
[Dci
-1].CErr
= 3;
2847 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
2850 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2851 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2852 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2853 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2854 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2858 case USB_ENDPOINT_ISO
:
2859 if (Direction
== EfiUsbDataIn
) {
2860 InputContext
->EP
[Dci
-1].CErr
= 0;
2861 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
2863 InputContext
->EP
[Dci
-1].CErr
= 0;
2864 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
2867 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2868 // Refer to XHCI 1.1 spec section 6.2.3.6.
2870 if (DeviceSpeed
== EFI_USB_SPEED_FULL
) {
2871 Interval
= EpDesc
->Interval
;
2872 ASSERT (Interval
>= 1 && Interval
<= 16);
2873 InputContext
->EP
[Dci
-1].Interval
= Interval
+ 2;
2874 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2875 Interval
= EpDesc
->Interval
;
2876 ASSERT (Interval
>= 1 && Interval
<= 16);
2877 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2881 // Do not support isochronous transfer now.
2883 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2884 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2886 case USB_ENDPOINT_INTERRUPT
:
2887 if (Direction
== EfiUsbDataIn
) {
2888 InputContext
->EP
[Dci
-1].CErr
= 3;
2889 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
2891 InputContext
->EP
[Dci
-1].CErr
= 3;
2892 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
2894 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2895 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
2897 // Get the bInterval from descriptor and init the the interval field of endpoint context
2899 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
2900 Interval
= EpDesc
->Interval
;
2902 // Calculate through the bInterval field of Endpoint descriptor.
2904 ASSERT (Interval
!= 0);
2905 InputContext
->EP
[Dci
-1].Interval
= (UINT32
)HighBitSet32((UINT32
)Interval
) + 3;
2906 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2907 Interval
= EpDesc
->Interval
;
2908 ASSERT (Interval
>= 1 && Interval
<= 16);
2910 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2912 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2913 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2914 InputContext
->EP
[Dci
-1].MaxESITPayload
= 0x0002;
2915 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2916 InputContext
->EP
[Dci
-1].CErr
= 3;
2919 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2920 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2921 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2922 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2926 case USB_ENDPOINT_CONTROL
:
2928 // Do not support control transfer now.
2930 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2932 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
2933 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2937 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2939 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
2940 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2942 PhyAddr
&= ~((EFI_PHYSICAL_ADDRESS
)0x0F);
2943 PhyAddr
|= (EFI_PHYSICAL_ADDRESS
)((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
2944 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2945 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2947 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2954 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2956 @param Xhc The XHCI Instance.
2957 @param SlotId The slot id to be configured.
2958 @param DeviceSpeed The device's speed.
2959 @param ConfigDesc The pointer to the usb device configuration descriptor.
2961 @retval EFI_SUCCESS Successfully configure all the device endpoints.
2967 IN USB_XHCI_INSTANCE
*Xhc
,
2969 IN UINT8 DeviceSpeed
,
2970 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
2974 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
2978 EFI_PHYSICAL_ADDRESS PhyAddr
;
2980 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
2981 INPUT_CONTEXT
*InputContext
;
2982 DEVICE_CONTEXT
*OutputContext
;
2983 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2985 // 4.6.6 Configure Endpoint
2987 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2988 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
2989 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2990 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT
));
2992 ASSERT (ConfigDesc
!= NULL
);
2996 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
2997 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
2998 while ((IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) || (IfDesc
->AlternateSetting
!= 0)) {
2999 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3002 if (IfDesc
->Length
< sizeof (USB_INTERFACE_DESCRIPTOR
)) {
3003 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3007 Dci
= XhcInitializeEndpointContext (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDesc
);
3012 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3015 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3016 InputContext
->Slot
.ContextEntries
= MaxDci
;
3018 // configure endpoint
3020 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3021 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3022 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3023 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3024 CmdTrbCfgEP
.CycleBit
= 1;
3025 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3026 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3027 DEBUG ((EFI_D_INFO
, "Configure Endpoint\n"));
3028 Status
= XhcCmdTransfer (
3030 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3031 XHC_GENERIC_TIMEOUT
,
3032 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3034 if (EFI_ERROR (Status
)) {
3035 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status
));
3037 Xhc
->UsbDevContext
[SlotId
].ActiveConfiguration
= ConfigDesc
->ConfigurationValue
;
3044 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
3046 @param Xhc The XHCI Instance.
3047 @param SlotId The slot id to be configured.
3048 @param DeviceSpeed The device's speed.
3049 @param ConfigDesc The pointer to the usb device configuration descriptor.
3051 @retval EFI_SUCCESS Successfully configure all the device endpoints.
3057 IN USB_XHCI_INSTANCE
*Xhc
,
3059 IN UINT8 DeviceSpeed
,
3060 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
3064 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
3068 EFI_PHYSICAL_ADDRESS PhyAddr
;
3070 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3071 INPUT_CONTEXT_64
*InputContext
;
3072 DEVICE_CONTEXT_64
*OutputContext
;
3073 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3075 // 4.6.6 Configure Endpoint
3077 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3078 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3079 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3080 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT_64
));
3082 ASSERT (ConfigDesc
!= NULL
);
3086 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
3087 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
3088 while ((IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) || (IfDesc
->AlternateSetting
!= 0)) {
3089 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3092 if (IfDesc
->Length
< sizeof (USB_INTERFACE_DESCRIPTOR
)) {
3093 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3097 Dci
= XhcInitializeEndpointContext64 (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDesc
);
3102 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3105 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3106 InputContext
->Slot
.ContextEntries
= MaxDci
;
3108 // configure endpoint
3110 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3111 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3112 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3113 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3114 CmdTrbCfgEP
.CycleBit
= 1;
3115 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3116 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3117 DEBUG ((EFI_D_INFO
, "Configure Endpoint\n"));
3118 Status
= XhcCmdTransfer (
3120 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3121 XHC_GENERIC_TIMEOUT
,
3122 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3124 if (EFI_ERROR (Status
)) {
3125 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status
));
3127 Xhc
->UsbDevContext
[SlotId
].ActiveConfiguration
= ConfigDesc
->ConfigurationValue
;
3134 Stop endpoint through XHCI's Stop_Endpoint cmd.
3136 @param Xhc The XHCI Instance.
3137 @param SlotId The slot id to be configured.
3138 @param Dci The device context index of endpoint.
3140 @retval EFI_SUCCESS Stop endpoint successfully.
3141 @retval Others Failed to stop endpoint.
3147 IN USB_XHCI_INSTANCE
*Xhc
,
3153 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3154 CMD_TRB_STOP_ENDPOINT CmdTrbStopED
;
3156 DEBUG ((EFI_D_INFO
, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId
, Dci
));
3159 // Send stop endpoint command to transit Endpoint from running to stop state
3161 ZeroMem (&CmdTrbStopED
, sizeof (CmdTrbStopED
));
3162 CmdTrbStopED
.CycleBit
= 1;
3163 CmdTrbStopED
.Type
= TRB_TYPE_STOP_ENDPOINT
;
3164 CmdTrbStopED
.EDID
= Dci
;
3165 CmdTrbStopED
.SlotId
= SlotId
;
3166 Status
= XhcCmdTransfer (
3168 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbStopED
,
3169 XHC_GENERIC_TIMEOUT
,
3170 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3172 if (EFI_ERROR(Status
)) {
3173 DEBUG ((EFI_D_ERROR
, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status
));
3180 Reset endpoint through XHCI's Reset_Endpoint cmd.
3182 @param Xhc The XHCI Instance.
3183 @param SlotId The slot id to be configured.
3184 @param Dci The device context index of endpoint.
3186 @retval EFI_SUCCESS Reset endpoint successfully.
3187 @retval Others Failed to reset endpoint.
3193 IN USB_XHCI_INSTANCE
*Xhc
,
3199 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3200 CMD_TRB_RESET_ENDPOINT CmdTrbResetED
;
3202 DEBUG ((EFI_D_INFO
, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId
, Dci
));
3205 // Send stop endpoint command to transit Endpoint from running to stop state
3207 ZeroMem (&CmdTrbResetED
, sizeof (CmdTrbResetED
));
3208 CmdTrbResetED
.CycleBit
= 1;
3209 CmdTrbResetED
.Type
= TRB_TYPE_RESET_ENDPOINT
;
3210 CmdTrbResetED
.EDID
= Dci
;
3211 CmdTrbResetED
.SlotId
= SlotId
;
3212 Status
= XhcCmdTransfer (
3214 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbResetED
,
3215 XHC_GENERIC_TIMEOUT
,
3216 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3218 if (EFI_ERROR(Status
)) {
3219 DEBUG ((EFI_D_ERROR
, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status
));
3226 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
3228 @param Xhc The XHCI Instance.
3229 @param SlotId The slot id to be configured.
3230 @param Dci The device context index of endpoint.
3231 @param Urb The dequeue pointer of the transfer ring specified
3232 by the urb to be updated.
3234 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
3235 @retval Others Failed to set transfer ring dequeue pointer.
3240 XhcSetTrDequeuePointer (
3241 IN USB_XHCI_INSTANCE
*Xhc
,
3248 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3249 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq
;
3250 EFI_PHYSICAL_ADDRESS PhyAddr
;
3252 DEBUG ((EFI_D_INFO
, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId
, Dci
, Urb
));
3255 // Send stop endpoint command to transit Endpoint from running to stop state
3257 ZeroMem (&CmdSetTRDeq
, sizeof (CmdSetTRDeq
));
3258 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Urb
->Ring
->RingEnqueue
, sizeof (CMD_SET_TR_DEQ_POINTER
));
3259 CmdSetTRDeq
.PtrLo
= XHC_LOW_32BIT (PhyAddr
) | Urb
->Ring
->RingPCS
;
3260 CmdSetTRDeq
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3261 CmdSetTRDeq
.CycleBit
= 1;
3262 CmdSetTRDeq
.Type
= TRB_TYPE_SET_TR_DEQUE
;
3263 CmdSetTRDeq
.Endpoint
= Dci
;
3264 CmdSetTRDeq
.SlotId
= SlotId
;
3265 Status
= XhcCmdTransfer (
3267 (TRB_TEMPLATE
*) (UINTN
) &CmdSetTRDeq
,
3268 XHC_GENERIC_TIMEOUT
,
3269 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3271 if (EFI_ERROR(Status
)) {
3272 DEBUG ((EFI_D_ERROR
, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status
));
3279 Set interface through XHCI's Configure_Endpoint cmd.
3281 @param Xhc The XHCI Instance.
3282 @param SlotId The slot id to be configured.
3283 @param DeviceSpeed The device's speed.
3284 @param ConfigDesc The pointer to the usb device configuration descriptor.
3285 @param Request USB device request to send.
3287 @retval EFI_SUCCESS Successfully set interface.
3293 IN USB_XHCI_INSTANCE
*Xhc
,
3295 IN UINT8 DeviceSpeed
,
3296 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
,
3297 IN EFI_USB_DEVICE_REQUEST
*Request
3301 USB_INTERFACE_DESCRIPTOR
*IfDescActive
;
3302 USB_INTERFACE_DESCRIPTOR
*IfDescSet
;
3303 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
3304 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
3311 EFI_PHYSICAL_ADDRESS PhyAddr
;
3314 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3315 INPUT_CONTEXT
*InputContext
;
3316 DEVICE_CONTEXT
*OutputContext
;
3317 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3319 Status
= EFI_SUCCESS
;
3321 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3322 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3324 // XHCI 4.6.6 Configure Endpoint
3325 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3326 // Context and Add Context flags as follows:
3327 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3328 // Context and Add Context flags to '0'.
3330 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3331 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3333 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3334 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT
));
3336 ASSERT (ConfigDesc
!= NULL
);
3340 IfDescActive
= NULL
;
3343 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
3344 while ((UINTN
) IfDesc
< ((UINTN
) ConfigDesc
+ ConfigDesc
->TotalLength
)) {
3345 if ((IfDesc
->DescriptorType
== USB_DESC_TYPE_INTERFACE
) && (IfDesc
->Length
>= sizeof (USB_INTERFACE_DESCRIPTOR
))) {
3346 if (IfDesc
->InterfaceNumber
== (UINT8
) Request
->Index
) {
3347 if (IfDesc
->AlternateSetting
== Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[IfDesc
->InterfaceNumber
]) {
3349 // Find out the active interface descriptor.
3351 IfDescActive
= IfDesc
;
3352 } else if (IfDesc
->AlternateSetting
== (UINT8
) Request
->Value
) {
3354 // Find out the interface descriptor to set.
3360 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3364 // XHCI 4.6.6 Configure Endpoint
3365 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3366 // Context and Add Context flags as follows:
3367 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3368 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3369 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3370 // the Drop Context flag to '1' and Add Context flag to '0'.
3371 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3372 // and Add Context flags shall be set to '1'.
3374 // Below codes are to cover 2), 3) and 4).
3377 if ((IfDescActive
!= NULL
) && (IfDescSet
!= NULL
)) {
3378 NumEp
= IfDescActive
->NumEndpoints
;
3379 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) (IfDescActive
+ 1);
3380 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
3381 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
3382 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3385 if (EpDesc
->Length
< sizeof (USB_ENDPOINT_DESCRIPTOR
)) {
3386 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3390 EpAddr
= (UINT8
) (EpDesc
->EndpointAddress
& 0x0F);
3391 Direction
= (UINT8
) ((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
3393 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
3399 // XHCI 4.3.6 - Setting Alternate Interfaces
3400 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3402 Status
= XhcStopEndpoint (Xhc
, SlotId
, Dci
);
3403 if (EFI_ERROR (Status
)) {
3407 // XHCI 4.3.6 - Setting Alternate Interfaces
3408 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3410 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] != NULL
) {
3411 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1])->RingSeg0
;
3412 if (RingSeg
!= NULL
) {
3413 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
3415 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1]);
3416 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] = NULL
;
3420 // Set the Drop Context flag to '1'.
3422 InputContext
->InputControlContext
.Dword1
|= (BIT0
<< Dci
);
3424 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3428 // XHCI 4.3.6 - Setting Alternate Interfaces
3429 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3430 // Interface setting, to '0'.
3432 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3436 // XHCI 4.3.6 - Setting Alternate Interfaces
3437 // 4) For each endpoint enabled by the Configure Endpoint Command:
3438 // a. Allocate a Transfer Ring.
3439 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3440 // c. Initialize the Endpoint Context data structure.
3442 Dci
= XhcInitializeEndpointContext (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDescSet
);
3447 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3448 InputContext
->Slot
.ContextEntries
= MaxDci
;
3450 // XHCI 4.3.6 - Setting Alternate Interfaces
3451 // 5) Issue and successfully complete a Configure Endpoint Command.
3453 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3454 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3455 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3456 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3457 CmdTrbCfgEP
.CycleBit
= 1;
3458 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3459 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3460 DEBUG ((EFI_D_INFO
, "SetInterface: Configure Endpoint\n"));
3461 Status
= XhcCmdTransfer (
3463 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3464 XHC_GENERIC_TIMEOUT
,
3465 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3467 if (EFI_ERROR (Status
)) {
3468 DEBUG ((EFI_D_ERROR
, "SetInterface: Config Endpoint Failed, Status = %r\n", Status
));
3471 // Update the active AlternateSetting.
3473 Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[(UINT8
) Request
->Index
] = (UINT8
) Request
->Value
;
3481 Set interface through XHCI's Configure_Endpoint cmd.
3483 @param Xhc The XHCI Instance.
3484 @param SlotId The slot id to be configured.
3485 @param DeviceSpeed The device's speed.
3486 @param ConfigDesc The pointer to the usb device configuration descriptor.
3487 @param Request USB device request to send.
3489 @retval EFI_SUCCESS Successfully set interface.
3495 IN USB_XHCI_INSTANCE
*Xhc
,
3497 IN UINT8 DeviceSpeed
,
3498 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
,
3499 IN EFI_USB_DEVICE_REQUEST
*Request
3503 USB_INTERFACE_DESCRIPTOR
*IfDescActive
;
3504 USB_INTERFACE_DESCRIPTOR
*IfDescSet
;
3505 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
3506 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
3513 EFI_PHYSICAL_ADDRESS PhyAddr
;
3516 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3517 INPUT_CONTEXT_64
*InputContext
;
3518 DEVICE_CONTEXT_64
*OutputContext
;
3519 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3521 Status
= EFI_SUCCESS
;
3523 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3524 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3526 // XHCI 4.6.6 Configure Endpoint
3527 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3528 // Context and Add Context flags as follows:
3529 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3530 // Context and Add Context flags to '0'.
3532 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3533 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3535 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3536 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT_64
));
3538 ASSERT (ConfigDesc
!= NULL
);
3542 IfDescActive
= NULL
;
3545 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
3546 while ((UINTN
) IfDesc
< ((UINTN
) ConfigDesc
+ ConfigDesc
->TotalLength
)) {
3547 if ((IfDesc
->DescriptorType
== USB_DESC_TYPE_INTERFACE
) && (IfDesc
->Length
>= sizeof (USB_INTERFACE_DESCRIPTOR
))) {
3548 if (IfDesc
->InterfaceNumber
== (UINT8
) Request
->Index
) {
3549 if (IfDesc
->AlternateSetting
== Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[IfDesc
->InterfaceNumber
]) {
3551 // Find out the active interface descriptor.
3553 IfDescActive
= IfDesc
;
3554 } else if (IfDesc
->AlternateSetting
== (UINT8
) Request
->Value
) {
3556 // Find out the interface descriptor to set.
3562 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3566 // XHCI 4.6.6 Configure Endpoint
3567 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3568 // Context and Add Context flags as follows:
3569 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3570 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3571 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3572 // the Drop Context flag to '1' and Add Context flag to '0'.
3573 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3574 // and Add Context flags shall be set to '1'.
3576 // Below codes are to cover 2), 3) and 4).
3579 if ((IfDescActive
!= NULL
) && (IfDescSet
!= NULL
)) {
3580 NumEp
= IfDescActive
->NumEndpoints
;
3581 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) (IfDescActive
+ 1);
3582 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
3583 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
3584 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3587 if (EpDesc
->Length
< sizeof (USB_ENDPOINT_DESCRIPTOR
)) {
3588 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3592 EpAddr
= (UINT8
) (EpDesc
->EndpointAddress
& 0x0F);
3593 Direction
= (UINT8
) ((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
3595 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
3601 // XHCI 4.3.6 - Setting Alternate Interfaces
3602 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3604 Status
= XhcStopEndpoint (Xhc
, SlotId
, Dci
);
3605 if (EFI_ERROR (Status
)) {
3609 // XHCI 4.3.6 - Setting Alternate Interfaces
3610 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3612 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] != NULL
) {
3613 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1])->RingSeg0
;
3614 if (RingSeg
!= NULL
) {
3615 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
3617 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1]);
3618 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] = NULL
;
3622 // Set the Drop Context flag to '1'.
3624 InputContext
->InputControlContext
.Dword1
|= (BIT0
<< Dci
);
3626 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3630 // XHCI 4.3.6 - Setting Alternate Interfaces
3631 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3632 // Interface setting, to '0'.
3634 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3638 // XHCI 4.3.6 - Setting Alternate Interfaces
3639 // 4) For each endpoint enabled by the Configure Endpoint Command:
3640 // a. Allocate a Transfer Ring.
3641 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3642 // c. Initialize the Endpoint Context data structure.
3644 Dci
= XhcInitializeEndpointContext64 (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDescSet
);
3649 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3650 InputContext
->Slot
.ContextEntries
= MaxDci
;
3652 // XHCI 4.3.6 - Setting Alternate Interfaces
3653 // 5) Issue and successfully complete a Configure Endpoint Command.
3655 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3656 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3657 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3658 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3659 CmdTrbCfgEP
.CycleBit
= 1;
3660 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3661 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3662 DEBUG ((EFI_D_INFO
, "SetInterface64: Configure Endpoint\n"));
3663 Status
= XhcCmdTransfer (
3665 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3666 XHC_GENERIC_TIMEOUT
,
3667 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3669 if (EFI_ERROR (Status
)) {
3670 DEBUG ((EFI_D_ERROR
, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status
));
3673 // Update the active AlternateSetting.
3675 Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[(UINT8
) Request
->Index
] = (UINT8
) Request
->Value
;
3683 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3685 @param Xhc The XHCI Instance.
3686 @param SlotId The slot id to be evaluated.
3687 @param MaxPacketSize The max packet size supported by the device control transfer.
3689 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3694 XhcEvaluateContext (
3695 IN USB_XHCI_INSTANCE
*Xhc
,
3697 IN UINT32 MaxPacketSize
3701 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
3702 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3703 INPUT_CONTEXT
*InputContext
;
3704 EFI_PHYSICAL_ADDRESS PhyAddr
;
3706 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3709 // 4.6.7 Evaluate Context
3711 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3712 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3714 InputContext
->InputControlContext
.Dword2
|= BIT1
;
3715 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
3717 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
3718 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3719 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3720 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3721 CmdTrbEvalu
.CycleBit
= 1;
3722 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
3723 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3724 DEBUG ((EFI_D_INFO
, "Evaluate context\n"));
3725 Status
= XhcCmdTransfer (
3727 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
3728 XHC_GENERIC_TIMEOUT
,
3729 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3731 if (EFI_ERROR (Status
)) {
3732 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status
));
3738 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3740 @param Xhc The XHCI Instance.
3741 @param SlotId The slot id to be evaluated.
3742 @param MaxPacketSize The max packet size supported by the device control transfer.
3744 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3749 XhcEvaluateContext64 (
3750 IN USB_XHCI_INSTANCE
*Xhc
,
3752 IN UINT32 MaxPacketSize
3756 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
3757 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3758 INPUT_CONTEXT_64
*InputContext
;
3759 EFI_PHYSICAL_ADDRESS PhyAddr
;
3761 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3764 // 4.6.7 Evaluate Context
3766 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3767 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3769 InputContext
->InputControlContext
.Dword2
|= BIT1
;
3770 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
3772 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
3773 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3774 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3775 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3776 CmdTrbEvalu
.CycleBit
= 1;
3777 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
3778 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3779 DEBUG ((EFI_D_INFO
, "Evaluate context\n"));
3780 Status
= XhcCmdTransfer (
3782 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
3783 XHC_GENERIC_TIMEOUT
,
3784 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3786 if (EFI_ERROR (Status
)) {
3787 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status
));
3794 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3796 @param Xhc The XHCI Instance.
3797 @param SlotId The slot id to be configured.
3798 @param PortNum The total number of downstream port supported by the hub.
3799 @param TTT The TT think time of the hub device.
3800 @param MTT The multi-TT of the hub device.
3802 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3806 XhcConfigHubContext (
3807 IN USB_XHCI_INSTANCE
*Xhc
,
3815 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3816 INPUT_CONTEXT
*InputContext
;
3817 DEVICE_CONTEXT
*OutputContext
;
3818 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3819 EFI_PHYSICAL_ADDRESS PhyAddr
;
3821 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3822 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3823 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3826 // 4.6.7 Evaluate Context
3828 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3830 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3833 // Copy the slot context from OutputContext to Input context
3835 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT
));
3836 InputContext
->Slot
.Hub
= 1;
3837 InputContext
->Slot
.PortNum
= PortNum
;
3838 InputContext
->Slot
.TTT
= TTT
;
3839 InputContext
->Slot
.MTT
= MTT
;
3841 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3842 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3843 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3844 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3845 CmdTrbCfgEP
.CycleBit
= 1;
3846 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3847 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3848 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
3849 Status
= XhcCmdTransfer (
3851 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3852 XHC_GENERIC_TIMEOUT
,
3853 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3855 if (EFI_ERROR (Status
)) {
3856 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status
));
3862 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3864 @param Xhc The XHCI Instance.
3865 @param SlotId The slot id to be configured.
3866 @param PortNum The total number of downstream port supported by the hub.
3867 @param TTT The TT think time of the hub device.
3868 @param MTT The multi-TT of the hub device.
3870 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3874 XhcConfigHubContext64 (
3875 IN USB_XHCI_INSTANCE
*Xhc
,
3883 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3884 INPUT_CONTEXT_64
*InputContext
;
3885 DEVICE_CONTEXT_64
*OutputContext
;
3886 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3887 EFI_PHYSICAL_ADDRESS PhyAddr
;
3889 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3890 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3891 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3894 // 4.6.7 Evaluate Context
3896 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3898 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3901 // Copy the slot context from OutputContext to Input context
3903 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT_64
));
3904 InputContext
->Slot
.Hub
= 1;
3905 InputContext
->Slot
.PortNum
= PortNum
;
3906 InputContext
->Slot
.TTT
= TTT
;
3907 InputContext
->Slot
.MTT
= MTT
;
3909 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3910 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3911 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3912 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3913 CmdTrbCfgEP
.CycleBit
= 1;
3914 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3915 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3916 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
3917 Status
= XhcCmdTransfer (
3919 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3920 XHC_GENERIC_TIMEOUT
,
3921 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3923 if (EFI_ERROR (Status
)) {
3924 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status
));