2 Private Header file for Usb Host Controller PEIM
4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _EFI_PEI_XHCI_REG_H_
11 #define _EFI_PEI_XHCI_REG_H_
14 // Capability registers offset
16 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
17 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
18 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
19 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
20 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
21 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
22 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
23 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
26 // Operational registers offset
28 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
29 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
30 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
31 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
32 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
33 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
34 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
35 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
38 // Runtime registers offset
40 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
41 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
42 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
43 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
44 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
45 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
48 // Register Bit Definition
50 #define XHC_USBCMD_RUN BIT0 // Run/Stop
51 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
52 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
53 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
55 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
56 #define XHC_USBSTS_HSE BIT2 // Host System Error
57 #define XHC_USBSTS_EINT BIT3 // Event Interrupt
58 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
59 #define XHC_USBSTS_SSS BIT8 // Save State Status
60 #define XHC_USBSTS_RSS BIT9 // Restore State Status
61 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
62 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
63 #define XHC_USBSTS_HCE BIT12 // Host Controller Error
65 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
67 #define XHC_CRCR_RCS BIT0 // Ring Cycle State
68 #define XHC_CRCR_CS BIT1 // Command Stop
69 #define XHC_CRCR_CA BIT2 // Command Abort
70 #define XHC_CRCR_CRR BIT3 // Command Ring Running
72 #define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled
74 #define XHC_PORTSC_CCS BIT0 // Current Connect Status
75 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
76 #define XHC_PORTSC_OCA BIT3 // Over-current Active
77 #define XHC_PORTSC_RESET BIT4 // Port Reset
78 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
79 #define XHC_PORTSC_PP BIT9 // Port Power
80 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
81 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
82 #define XHC_PORTSC_CSC BIT17 // Connect Status Change
83 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
84 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
85 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
86 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
87 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
88 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
89 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
91 #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
92 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
93 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
94 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
95 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
96 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
97 #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
98 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
99 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
100 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
102 #define XHC_IMAN_IP BIT0 // Interrupt Pending
103 #define XHC_IMAN_IE BIT1 // Interrupt Enable
105 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
106 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
111 UINT8 MaxSlots
; // Number of Device Slots
112 UINT16 MaxIntrs
:11; // Number of Interrupters
114 UINT8 MaxPorts
; // Number of Ports
118 // Structural Parameters 1 Register Bitmap Definition
126 UINT32 Ist
:4; // Isochronous Scheduling Threshold
127 UINT32 Erst
:4; // Event Ring Segment Table Max
129 UINT32 ScratchBufHi
:5; // Max Scratchpad Buffers Hi
130 UINT32 Spr
:1; // Scratchpad Restore
131 UINT32 ScratchBufLo
:5; // Max Scratchpad Buffers Lo
135 // Structural Parameters 2 Register Bitmap Definition
143 UINT16 Ac64
:1; // 64-bit Addressing Capability
144 UINT16 Bnc
:1; // BW Negotiation Capability
145 UINT16 Csz
:1; // Context Size
146 UINT16 Ppc
:1; // Port Power Control
147 UINT16 Pind
:1; // Port Indicators
148 UINT16 Lhrc
:1; // Light HC Reset Capability
149 UINT16 Ltc
:1; // Latency Tolerance Messaging Capability
150 UINT16 Nss
:1; // No Secondary SID Support
151 UINT16 Pae
:1; // Parse All Event Data
153 UINT16 MaxPsaSize
:4; // Maximum Primary Stream Array Size
154 UINT16 ExtCapReg
; // xHCI Extended Capabilities Pointer
158 // Capability Parameters Register Bitmap Definition
168 // XHCi Data and Ctrl Structures
183 UINT8 HubContrCurrent
;
185 } EFI_USB_HUB_DESCRIPTOR
;
189 // Hub Class Feature Selector for Clear Port Feature Request
190 // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
191 // For more details, Please refer to USB 3.0 Spec Table 10-7.
194 Usb3PortBHPortReset
= 28,
195 Usb3PortBHPortResetChange
= 29
199 // Structure to map the hardware port states to the
200 // UEFI's port states.
205 } USB_PORT_STATE_MAP
;
208 // Structure to map the hardware port states to feature selector for clear port feature request.
213 } USB_CLEAR_PORT_MAP
;
216 Read XHCI Operation register.
218 @param Xhc The XHCI device.
219 @param Offset The operation register offset.
221 @retval the register content read.
231 Write the data to the XHCI operation register.
233 @param Xhc The XHCI device.
234 @param Offset The operation register offset.
235 @param Data The data to write.
246 Set one bit of the operational register while keeping other bits.
248 @param Xhc The XHCI device.
249 @param Offset The offset of the operational register.
250 @param Bit The bit mask of the register to set.
261 Clear one bit of the operational register while keeping other bits.
263 @param Xhc The XHCI device.
264 @param Offset The offset of the operational register.
265 @param Bit The bit mask of the register to clear.
269 XhcPeiClearOpRegBit (
276 Wait the operation register's bit as specified by Bit
277 to be set (or clear).
279 @param Xhc The XHCI device.
280 @param Offset The offset of the operational register.
281 @param Bit The bit of the register to wait for.
282 @param WaitToSet Wait the bit to set or clear.
283 @param Timeout The time to wait before abort (in millisecond, ms).
285 @retval EFI_SUCCESS The bit successfully changed by host controller.
286 @retval EFI_TIMEOUT The time out occurred.
294 IN BOOLEAN WaitToSet
,
300 Write the data to the XHCI door bell register.
302 @param Xhc The XHCI device.
303 @param Offset The offset of the door bell register.
304 @param Data The data to write.
308 XhcPeiWriteDoorBellReg (
315 Read XHCI runtime register.
317 @param Xhc The XHCI device.
318 @param Offset The offset of the runtime register.
320 @return The register content read
324 XhcPeiReadRuntimeReg (
330 Write the data to the XHCI runtime register.
332 @param Xhc The XHCI device.
333 @param Offset The offset of the runtime register.
334 @param Data The data to write.
338 XhcPeiWriteRuntimeReg (
345 Set one bit of the runtime register while keeping other bits.
347 @param Xhc The XHCI device.
348 @param Offset The offset of the runtime register.
349 @param Bit The bit mask of the register to set.
353 XhcPeiSetRuntimeRegBit (
360 Clear one bit of the runtime register while keeping other bits.
362 @param Xhc The XHCI device.
363 @param Offset The offset of the runtime register.
364 @param Bit The bit mask of the register to set.
368 XhcPeiClearRuntimeRegBit (
375 Check whether Xhc is halted.
377 @param Xhc The XHCI device.
379 @retval TRUE The controller is halted.
380 @retval FALSE The controller isn't halted.
389 Check whether system error occurred.
391 @param Xhc The XHCI device.
393 @retval TRUE System error happened.
394 @retval FALSE No system error.
403 Reset the host controller.
405 @param Xhc The XHCI device.
406 @param Timeout Time to wait before abort (in millisecond, ms).
408 @retval EFI_TIMEOUT The transfer failed due to time out.
409 @retval Others Failed to reset the host.
419 Halt the host controller.
421 @param Xhc The XHCI device.
422 @param Timeout Time to wait before abort.
424 @retval EFI_TIMEOUT Failed to halt the controller before Timeout.
425 @retval EFI_SUCCESS The XHCI is halt.
437 @param Xhc The XHCI device.
438 @param Timeout Time to wait before abort.
440 @retval EFI_SUCCESS The XHCI is running.
441 @retval Others Failed to set the XHCI to run.