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MdeModulePkg/SdBlockIoPei: Support IoMmu
[mirror_edk2.git] / MdeModulePkg / Bus / Sd / SdBlockIoPei / SdHci.c
1 /** @file
2
3 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php.
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 **/
13
14 #include "SdBlockIoPei.h"
15
16 /**
17 Read/Write specified SD host controller mmio register.
18
19 @param[in] Address The address of the mmio register to be read/written.
20 @param[in] Read A boolean to indicate it's read or write operation.
21 @param[in] Count The width of the mmio register in bytes.
22 Must be 1, 2 , 4 or 8 bytes.
23 @param[in, out] Data For read operations, the destination buffer to store
24 the results. For write operations, the source buffer
25 to write data from. The caller is responsible for
26 having ownership of the data buffer and ensuring its
27 size not less than Count bytes.
28
29 @retval EFI_INVALID_PARAMETER The Address or the Data or the Count is not valid.
30 @retval EFI_SUCCESS The read/write operation succeeds.
31 @retval Others The read/write operation fails.
32
33 **/
34 EFI_STATUS
35 EFIAPI
36 SdPeimHcRwMmio (
37 IN UINTN Address,
38 IN BOOLEAN Read,
39 IN UINT8 Count,
40 IN OUT VOID *Data
41 )
42 {
43 if ((Address == 0) || (Data == NULL)) {
44 return EFI_INVALID_PARAMETER;
45 }
46
47 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
48 return EFI_INVALID_PARAMETER;
49 }
50
51 switch (Count) {
52 case 1:
53 if (Read) {
54 *(UINT8*)Data = MmioRead8 (Address);
55 } else {
56 MmioWrite8 (Address, *(UINT8*)Data);
57 }
58 break;
59 case 2:
60 if (Read) {
61 *(UINT16*)Data = MmioRead16 (Address);
62 } else {
63 MmioWrite16 (Address, *(UINT16*)Data);
64 }
65 break;
66 case 4:
67 if (Read) {
68 *(UINT32*)Data = MmioRead32 (Address);
69 } else {
70 MmioWrite32 (Address, *(UINT32*)Data);
71 }
72 break;
73 case 8:
74 if (Read) {
75 *(UINT64*)Data = MmioRead64 (Address);
76 } else {
77 MmioWrite64 (Address, *(UINT64*)Data);
78 }
79 break;
80 default:
81 ASSERT (FALSE);
82 return EFI_INVALID_PARAMETER;
83 }
84
85 return EFI_SUCCESS;
86 }
87
88 /**
89 Do OR operation with the value of the specified SD host controller mmio register.
90
91 @param[in] Address The address of the mmio register to be read/written.
92 @param[in] Count The width of the mmio register in bytes.
93 Must be 1, 2 , 4 or 8 bytes.
94 @param[in] OrData The pointer to the data used to do OR operation.
95 The caller is responsible for having ownership of
96 the data buffer and ensuring its size not less than
97 Count bytes.
98
99 @retval EFI_INVALID_PARAMETER The Address or the OrData or the Count is not valid.
100 @retval EFI_SUCCESS The OR operation succeeds.
101 @retval Others The OR operation fails.
102
103 **/
104 EFI_STATUS
105 EFIAPI
106 SdPeimHcOrMmio (
107 IN UINTN Address,
108 IN UINT8 Count,
109 IN VOID *OrData
110 )
111 {
112 EFI_STATUS Status;
113 UINT64 Data;
114 UINT64 Or;
115
116 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Data);
117 if (EFI_ERROR (Status)) {
118 return Status;
119 }
120
121 if (Count == 1) {
122 Or = *(UINT8*) OrData;
123 } else if (Count == 2) {
124 Or = *(UINT16*) OrData;
125 } else if (Count == 4) {
126 Or = *(UINT32*) OrData;
127 } else if (Count == 8) {
128 Or = *(UINT64*) OrData;
129 } else {
130 return EFI_INVALID_PARAMETER;
131 }
132
133 Data |= Or;
134 Status = SdPeimHcRwMmio (Address, FALSE, Count, &Data);
135
136 return Status;
137 }
138
139 /**
140 Do AND operation with the value of the specified SD host controller mmio register.
141
142 @param[in] Address The address of the mmio register to be read/written.
143 @param[in] Count The width of the mmio register in bytes.
144 Must be 1, 2 , 4 or 8 bytes.
145 @param[in] AndData The pointer to the data used to do AND operation.
146 The caller is responsible for having ownership of
147 the data buffer and ensuring its size not less than
148 Count bytes.
149
150 @retval EFI_INVALID_PARAMETER The Address or the AndData or the Count is not valid.
151 @retval EFI_SUCCESS The AND operation succeeds.
152 @retval Others The AND operation fails.
153
154 **/
155 EFI_STATUS
156 EFIAPI
157 SdPeimHcAndMmio (
158 IN UINTN Address,
159 IN UINT8 Count,
160 IN VOID *AndData
161 )
162 {
163 EFI_STATUS Status;
164 UINT64 Data;
165 UINT64 And;
166
167 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Data);
168 if (EFI_ERROR (Status)) {
169 return Status;
170 }
171
172 if (Count == 1) {
173 And = *(UINT8*) AndData;
174 } else if (Count == 2) {
175 And = *(UINT16*) AndData;
176 } else if (Count == 4) {
177 And = *(UINT32*) AndData;
178 } else if (Count == 8) {
179 And = *(UINT64*) AndData;
180 } else {
181 return EFI_INVALID_PARAMETER;
182 }
183
184 Data &= And;
185 Status = SdPeimHcRwMmio (Address, FALSE, Count, &Data);
186
187 return Status;
188 }
189
190 /**
191 Wait for the value of the specified MMIO register set to the test value.
192
193 @param[in] Address The address of the mmio register to be checked.
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2, 4 or 8 bytes.
196 @param[in] MaskValue The mask value of memory.
197 @param[in] TestValue The test value of memory.
198
199 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
200 @retval EFI_SUCCESS The MMIO register has expected value.
201 @retval Others The MMIO operation fails.
202
203 **/
204 EFI_STATUS
205 EFIAPI
206 SdPeimHcCheckMmioSet (
207 IN UINTN Address,
208 IN UINT8 Count,
209 IN UINT64 MaskValue,
210 IN UINT64 TestValue
211 )
212 {
213 EFI_STATUS Status;
214 UINT64 Value;
215
216 //
217 // Access PCI MMIO space to see if the value is the tested one.
218 //
219 Value = 0;
220 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Value);
221 if (EFI_ERROR (Status)) {
222 return Status;
223 }
224
225 Value &= MaskValue;
226
227 if (Value == TestValue) {
228 return EFI_SUCCESS;
229 }
230
231 return EFI_NOT_READY;
232 }
233
234 /**
235 Wait for the value of the specified MMIO register set to the test value.
236
237 @param[in] Address The address of the mmio register to wait.
238 @param[in] Count The width of the mmio register in bytes.
239 Must be 1, 2, 4 or 8 bytes.
240 @param[in] MaskValue The mask value of memory.
241 @param[in] TestValue The test value of memory.
242 @param[in] Timeout The time out value for wait memory set, uses 1
243 microsecond as a unit.
244
245 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
246 range.
247 @retval EFI_SUCCESS The MMIO register has expected value.
248 @retval Others The MMIO operation fails.
249
250 **/
251 EFI_STATUS
252 EFIAPI
253 SdPeimHcWaitMmioSet (
254 IN UINTN Address,
255 IN UINT8 Count,
256 IN UINT64 MaskValue,
257 IN UINT64 TestValue,
258 IN UINT64 Timeout
259 )
260 {
261 EFI_STATUS Status;
262 BOOLEAN InfiniteWait;
263
264 if (Timeout == 0) {
265 InfiniteWait = TRUE;
266 } else {
267 InfiniteWait = FALSE;
268 }
269
270 while (InfiniteWait || (Timeout > 0)) {
271 Status = SdPeimHcCheckMmioSet (
272 Address,
273 Count,
274 MaskValue,
275 TestValue
276 );
277 if (Status != EFI_NOT_READY) {
278 return Status;
279 }
280
281 //
282 // Stall for 1 microsecond.
283 //
284 MicroSecondDelay (1);
285
286 Timeout--;
287 }
288
289 return EFI_TIMEOUT;
290 }
291
292 /**
293 Software reset the specified SD host controller and enable all interrupts.
294
295 @param[in] Bar The mmio base address of the slot to be accessed.
296
297 @retval EFI_SUCCESS The software reset executes successfully.
298 @retval Others The software reset fails.
299
300 **/
301 EFI_STATUS
302 SdPeimHcReset (
303 IN UINTN Bar
304 )
305 {
306 EFI_STATUS Status;
307 UINT8 SwReset;
308
309 SwReset = 0xFF;
310 Status = SdPeimHcRwMmio (Bar + SD_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);
311
312 if (EFI_ERROR (Status)) {
313 DEBUG ((EFI_D_ERROR, "SdPeimHcReset: write full 1 fails: %r\n", Status));
314 return Status;
315 }
316
317 Status = SdPeimHcWaitMmioSet (
318 Bar + SD_HC_SW_RST,
319 sizeof (SwReset),
320 0xFF,
321 0x00,
322 SD_TIMEOUT
323 );
324 if (EFI_ERROR (Status)) {
325 DEBUG ((EFI_D_INFO, "SdPeimHcReset: reset done with %r\n", Status));
326 return Status;
327 }
328 //
329 // Enable all interrupt after reset all.
330 //
331 Status = SdPeimHcEnableInterrupt (Bar);
332
333 return Status;
334 }
335
336 /**
337 Set all interrupt status bits in Normal and Error Interrupt Status Enable
338 register.
339
340 @param[in] Bar The mmio base address of the slot to be accessed.
341
342 @retval EFI_SUCCESS The operation executes successfully.
343 @retval Others The operation fails.
344
345 **/
346 EFI_STATUS
347 SdPeimHcEnableInterrupt (
348 IN UINTN Bar
349 )
350 {
351 EFI_STATUS Status;
352 UINT16 IntStatus;
353
354 //
355 // Enable all bits in Error Interrupt Status Enable Register
356 //
357 IntStatus = 0xFFFF;
358 Status = SdPeimHcRwMmio (Bar + SD_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
359 if (EFI_ERROR (Status)) {
360 return Status;
361 }
362 //
363 // Enable all bits in Normal Interrupt Status Enable Register
364 //
365 IntStatus = 0xFFFF;
366 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
367
368 return Status;
369 }
370
371 /**
372 Get the capability data from the specified slot.
373
374 @param[in] Bar The mmio base address of the slot to be accessed.
375 @param[out] Capability The buffer to store the capability data.
376
377 @retval EFI_SUCCESS The operation executes successfully.
378 @retval Others The operation fails.
379
380 **/
381 EFI_STATUS
382 SdPeimHcGetCapability (
383 IN UINTN Bar,
384 OUT SD_HC_SLOT_CAP *Capability
385 )
386 {
387 EFI_STATUS Status;
388 UINT64 Cap;
389
390 Status = SdPeimHcRwMmio (Bar + SD_HC_CAP, TRUE, sizeof (Cap), &Cap);
391 if (EFI_ERROR (Status)) {
392 return Status;
393 }
394
395 CopyMem (Capability, &Cap, sizeof (Cap));
396
397 return EFI_SUCCESS;
398 }
399
400 /**
401 Detect whether there is a SD card attached at the specified SD host controller
402 slot.
403
404 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
405
406 @param[in] Bar The mmio base address of the slot to be accessed.
407
408 @retval EFI_SUCCESS There is a SD card attached.
409 @retval EFI_NO_MEDIA There is not a SD card attached.
410 @retval Others The detection fails.
411
412 **/
413 EFI_STATUS
414 SdPeimHcCardDetect (
415 IN UINTN Bar
416 )
417 {
418 EFI_STATUS Status;
419 UINT16 Data;
420 UINT32 PresentState;
421
422 //
423 // Check Normal Interrupt Status Register
424 //
425 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
426 if (EFI_ERROR (Status)) {
427 return Status;
428 }
429
430 if ((Data & (BIT6 | BIT7)) != 0) {
431 //
432 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
433 //
434 Data &= BIT6 | BIT7;
435 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
436 if (EFI_ERROR (Status)) {
437 return Status;
438 }
439 }
440
441 //
442 // Check Present State Register to see if there is a card presented.
443 //
444 Status = SdPeimHcRwMmio (Bar + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
445 if (EFI_ERROR (Status)) {
446 return Status;
447 }
448
449 if ((PresentState & BIT16) != 0) {
450 return EFI_SUCCESS;
451 } else {
452 return EFI_NO_MEDIA;
453 }
454 }
455
456 /**
457 Stop SD card clock.
458
459 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
460
461 @param[in] Bar The mmio base address of the slot to be accessed.
462
463 @retval EFI_SUCCESS Succeed to stop SD clock.
464 @retval Others Fail to stop SD clock.
465
466 **/
467 EFI_STATUS
468 SdPeimHcStopClock (
469 IN UINTN Bar
470 )
471 {
472 EFI_STATUS Status;
473 UINT32 PresentState;
474 UINT16 ClockCtrl;
475
476 //
477 // Ensure no SD transactions are occurring on the SD Bus by
478 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
479 // in the Present State register to be 0.
480 //
481 Status = SdPeimHcWaitMmioSet (
482 Bar + SD_HC_PRESENT_STATE,
483 sizeof (PresentState),
484 BIT0 | BIT1,
485 0,
486 SD_TIMEOUT
487 );
488 if (EFI_ERROR (Status)) {
489 return Status;
490 }
491
492 //
493 // Set SD Clock Enable in the Clock Control register to 0
494 //
495 ClockCtrl = (UINT16)~BIT2;
496 Status = SdPeimHcAndMmio (Bar + SD_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
497
498 return Status;
499 }
500
501 /**
502 SD card clock supply.
503
504 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
505
506 @param[in] Bar The mmio base address of the slot to be accessed.
507 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
508
509 @retval EFI_SUCCESS The clock is supplied successfully.
510 @retval Others The clock isn't supplied successfully.
511
512 **/
513 EFI_STATUS
514 SdPeimHcClockSupply (
515 IN UINTN Bar,
516 IN UINT64 ClockFreq
517 )
518 {
519 EFI_STATUS Status;
520 SD_HC_SLOT_CAP Capability;
521 UINT32 BaseClkFreq;
522 UINT32 SettingFreq;
523 UINT32 Divisor;
524 UINT32 Remainder;
525 UINT16 ControllerVer;
526 UINT16 ClockCtrl;
527
528 //
529 // Calculate a divisor for SD clock frequency
530 //
531 Status = SdPeimHcGetCapability (Bar, &Capability);
532 if (EFI_ERROR (Status)) {
533 return Status;
534 }
535 ASSERT (Capability.BaseClkFreq != 0);
536
537 BaseClkFreq = Capability.BaseClkFreq;
538
539 if (ClockFreq == 0) {
540 return EFI_INVALID_PARAMETER;
541 }
542
543 if (ClockFreq > (BaseClkFreq * 1000)) {
544 ClockFreq = BaseClkFreq * 1000;
545 }
546
547 //
548 // Calculate the divisor of base frequency.
549 //
550 Divisor = 0;
551 SettingFreq = BaseClkFreq * 1000;
552 while (ClockFreq < SettingFreq) {
553 Divisor++;
554
555 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
556 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
557 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
558 break;
559 }
560 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
561 SettingFreq ++;
562 }
563 }
564
565 DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
566
567 Status = SdPeimHcRwMmio (Bar + SD_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
568 if (EFI_ERROR (Status)) {
569 return Status;
570 }
571 //
572 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
573 //
574 if ((ControllerVer & 0xFF) == 2) {
575 ASSERT (Divisor <= 0x3FF);
576 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
577 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
578 //
579 // Only the most significant bit can be used as divisor.
580 //
581 if (((Divisor - 1) & Divisor) != 0) {
582 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
583 }
584 ASSERT (Divisor <= 0x80);
585 ClockCtrl = (Divisor & 0xFF) << 8;
586 } else {
587 DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
588 return EFI_UNSUPPORTED;
589 }
590
591 //
592 // Stop bus clock at first
593 //
594 Status = SdPeimHcStopClock (Bar);
595 if (EFI_ERROR (Status)) {
596 return Status;
597 }
598
599 //
600 // Supply clock frequency with specified divisor
601 //
602 ClockCtrl |= BIT0;
603 Status = SdPeimHcRwMmio (Bar + SD_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
604 if (EFI_ERROR (Status)) {
605 DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
606 return Status;
607 }
608
609 //
610 // Wait Internal Clock Stable in the Clock Control register to be 1
611 //
612 Status = SdPeimHcWaitMmioSet (
613 Bar + SD_HC_CLOCK_CTRL,
614 sizeof (ClockCtrl),
615 BIT1,
616 BIT1,
617 SD_TIMEOUT
618 );
619 if (EFI_ERROR (Status)) {
620 return Status;
621 }
622
623 //
624 // Set SD Clock Enable in the Clock Control register to 1
625 //
626 ClockCtrl = BIT2;
627 Status = SdPeimHcOrMmio (Bar + SD_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
628
629 return Status;
630 }
631
632 /**
633 SD bus power control.
634
635 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
636
637 @param[in] Bar The mmio base address of the slot to be accessed.
638 @param[in] PowerCtrl The value setting to the power control register.
639
640 @retval TRUE There is a SD card attached.
641 @retval FALSE There is no a SD card attached.
642
643 **/
644 EFI_STATUS
645 SdPeimHcPowerControl (
646 IN UINTN Bar,
647 IN UINT8 PowerCtrl
648 )
649 {
650 EFI_STATUS Status;
651
652 //
653 // Clr SD Bus Power
654 //
655 PowerCtrl &= (UINT8)~BIT0;
656 Status = SdPeimHcRwMmio (Bar + SD_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
657 if (EFI_ERROR (Status)) {
658 return Status;
659 }
660
661 //
662 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
663 //
664 PowerCtrl |= BIT0;
665 Status = SdPeimHcRwMmio (Bar + SD_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
666
667 return Status;
668 }
669
670 /**
671 Set the SD bus width.
672
673 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
674
675 @param[in] Bar The mmio base address of the slot to be accessed.
676 @param[in] BusWidth The bus width used by the SD device, it must be 1, 4 or 8.
677
678 @retval EFI_SUCCESS The bus width is set successfully.
679 @retval Others The bus width isn't set successfully.
680
681 **/
682 EFI_STATUS
683 SdPeimHcSetBusWidth (
684 IN UINTN Bar,
685 IN UINT16 BusWidth
686 )
687 {
688 EFI_STATUS Status;
689 UINT8 HostCtrl1;
690
691 if (BusWidth == 1) {
692 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
693 Status = SdPeimHcAndMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
694 } else if (BusWidth == 4) {
695 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
696 if (EFI_ERROR (Status)) {
697 return Status;
698 }
699 HostCtrl1 |= BIT1;
700 HostCtrl1 &= (UINT8)~BIT5;
701 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
702 } else if (BusWidth == 8) {
703 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
704 if (EFI_ERROR (Status)) {
705 return Status;
706 }
707 HostCtrl1 &= (UINT8)~BIT1;
708 HostCtrl1 |= BIT5;
709 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
710 } else {
711 ASSERT (FALSE);
712 return EFI_INVALID_PARAMETER;
713 }
714
715 return Status;
716 }
717
718 /**
719 Supply SD card with lowest clock frequency at initialization.
720
721 @param[in] Bar The mmio base address of the slot to be accessed.
722
723 @retval EFI_SUCCESS The clock is supplied successfully.
724 @retval Others The clock isn't supplied successfully.
725
726 **/
727 EFI_STATUS
728 SdPeimHcInitClockFreq (
729 IN UINTN Bar
730 )
731 {
732 EFI_STATUS Status;
733 SD_HC_SLOT_CAP Capability;
734 UINT32 InitFreq;
735
736 //
737 // Calculate a divisor for SD clock frequency
738 //
739 Status = SdPeimHcGetCapability (Bar, &Capability);
740 if (EFI_ERROR (Status)) {
741 return Status;
742 }
743
744 if (Capability.BaseClkFreq == 0) {
745 //
746 // Don't support get Base Clock Frequency information via another method
747 //
748 return EFI_UNSUPPORTED;
749 }
750 //
751 // Supply 400KHz clock frequency at initialization phase.
752 //
753 InitFreq = 400;
754 Status = SdPeimHcClockSupply (Bar, InitFreq);
755 return Status;
756 }
757
758 /**
759 Supply SD card with maximum voltage at initialization.
760
761 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
762
763 @param[in] Bar The mmio base address of the slot to be accessed.
764
765 @retval EFI_SUCCESS The voltage is supplied successfully.
766 @retval Others The voltage isn't supplied successfully.
767
768 **/
769 EFI_STATUS
770 SdPeimHcInitPowerVoltage (
771 IN UINTN Bar
772 )
773 {
774 EFI_STATUS Status;
775 SD_HC_SLOT_CAP Capability;
776 UINT8 MaxVoltage;
777 UINT8 HostCtrl2;
778
779 //
780 // Get the support voltage of the Host Controller
781 //
782 Status = SdPeimHcGetCapability (Bar, &Capability);
783 if (EFI_ERROR (Status)) {
784 return Status;
785 }
786 //
787 // Calculate supported maximum voltage according to SD Bus Voltage Select
788 //
789 if (Capability.Voltage33 != 0) {
790 //
791 // Support 3.3V
792 //
793 MaxVoltage = 0x0E;
794 } else if (Capability.Voltage30 != 0) {
795 //
796 // Support 3.0V
797 //
798 MaxVoltage = 0x0C;
799 } else if (Capability.Voltage18 != 0) {
800 //
801 // Support 1.8V
802 //
803 MaxVoltage = 0x0A;
804 HostCtrl2 = BIT3;
805 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
806 if (EFI_ERROR (Status)) {
807 return Status;
808 }
809 MicroSecondDelay (5000);
810 } else {
811 ASSERT (FALSE);
812 return EFI_DEVICE_ERROR;
813 }
814
815 //
816 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
817 //
818 Status = SdPeimHcPowerControl (Bar, MaxVoltage);
819
820 return Status;
821 }
822
823 /**
824 Initialize the Timeout Control register with most conservative value at initialization.
825
826 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
827
828 @param[in] Bar The mmio base address of the slot to be accessed.
829
830 @retval EFI_SUCCESS The timeout control register is configured successfully.
831 @retval Others The timeout control register isn't configured successfully.
832
833 **/
834 EFI_STATUS
835 SdPeimHcInitTimeoutCtrl (
836 IN UINTN Bar
837 )
838 {
839 EFI_STATUS Status;
840 UINT8 Timeout;
841
842 Timeout = 0x0E;
843 Status = SdPeimHcRwMmio (Bar + SD_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
844
845 return Status;
846 }
847
848 /**
849 Initial SD host controller with lowest clock frequency, max power and max timeout value
850 at initialization.
851
852 @param[in] Bar The mmio base address of the slot to be accessed.
853
854 @retval EFI_SUCCESS The host controller is initialized successfully.
855 @retval Others The host controller isn't initialized successfully.
856
857 **/
858 EFI_STATUS
859 SdPeimHcInitHost (
860 IN UINTN Bar
861 )
862 {
863 EFI_STATUS Status;
864
865 Status = SdPeimHcInitClockFreq (Bar);
866 if (EFI_ERROR (Status)) {
867 return Status;
868 }
869
870 Status = SdPeimHcInitPowerVoltage (Bar);
871 if (EFI_ERROR (Status)) {
872 return Status;
873 }
874
875 Status = SdPeimHcInitTimeoutCtrl (Bar);
876 return Status;
877 }
878
879 /**
880 Turn on/off LED.
881
882 @param[in] Bar The mmio base address of the slot to be accessed.
883 @param[in] On The boolean to turn on/off LED.
884
885 @retval EFI_SUCCESS The LED is turned on/off successfully.
886 @retval Others The LED isn't turned on/off successfully.
887
888 **/
889 EFI_STATUS
890 SdPeimHcLedOnOff (
891 IN UINTN Bar,
892 IN BOOLEAN On
893 )
894 {
895 EFI_STATUS Status;
896 UINT8 HostCtrl1;
897
898 if (On) {
899 HostCtrl1 = BIT0;
900 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
901 } else {
902 HostCtrl1 = (UINT8)~BIT0;
903 Status = SdPeimHcAndMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
904 }
905
906 return Status;
907 }
908
909 /**
910 Build ADMA descriptor table for transfer.
911
912 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
913
914 @param[in] Trb The pointer to the SD_TRB instance.
915
916 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
917 @retval Others The ADMA descriptor table isn't created successfully.
918
919 **/
920 EFI_STATUS
921 BuildAdmaDescTable (
922 IN SD_TRB *Trb
923 )
924 {
925 EFI_PHYSICAL_ADDRESS Data;
926 UINT64 DataLen;
927 UINT64 Entries;
928 UINT32 Index;
929 UINT64 Remaining;
930 UINT32 Address;
931
932 Data = Trb->DataPhy;
933 DataLen = Trb->DataLen;
934 //
935 // Only support 32bit ADMA Descriptor Table
936 //
937 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
938 return EFI_INVALID_PARAMETER;
939 }
940 //
941 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
942 // for 32-bit address descriptor table.
943 //
944 if ((Data & (BIT0 | BIT1)) != 0) {
945 DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
946 }
947
948 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
949
950 Trb->AdmaDescSize = (UINTN)MultU64x32 (Entries, sizeof (SD_HC_ADMA_DESC_LINE));
951 Trb->AdmaDesc = SdPeimAllocateMem (Trb->Slot->Private->Pool, Trb->AdmaDescSize);
952 if (Trb->AdmaDesc == NULL) {
953 return EFI_OUT_OF_RESOURCES;
954 }
955
956 Remaining = DataLen;
957 Address = (UINT32)Data;
958 for (Index = 0; Index < Entries; Index++) {
959 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
960 Trb->AdmaDesc[Index].Valid = 1;
961 Trb->AdmaDesc[Index].Act = 2;
962 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
963 Trb->AdmaDesc[Index].Address = Address;
964 break;
965 } else {
966 Trb->AdmaDesc[Index].Valid = 1;
967 Trb->AdmaDesc[Index].Act = 2;
968 Trb->AdmaDesc[Index].Length = 0;
969 Trb->AdmaDesc[Index].Address = Address;
970 }
971
972 Remaining -= ADMA_MAX_DATA_PER_LINE;
973 Address += ADMA_MAX_DATA_PER_LINE;
974 }
975
976 //
977 // Set the last descriptor line as end of descriptor table
978 //
979 Trb->AdmaDesc[Index].End = 1;
980 return EFI_SUCCESS;
981 }
982
983 /**
984 Create a new TRB for the SD cmd request.
985
986 @param[in] Slot The slot number of the SD card to send the command to.
987 @param[in] Packet A pointer to the SD command data structure.
988
989 @return Created Trb or NULL.
990
991 **/
992 SD_TRB *
993 SdPeimCreateTrb (
994 IN SD_PEIM_HC_SLOT *Slot,
995 IN SD_COMMAND_PACKET *Packet
996 )
997 {
998 SD_TRB *Trb;
999 EFI_STATUS Status;
1000 SD_HC_SLOT_CAP Capability;
1001 EDKII_IOMMU_OPERATION MapOp;
1002 UINTN MapLength;
1003
1004 //
1005 // Calculate a divisor for SD clock frequency
1006 //
1007 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
1008 if (EFI_ERROR (Status)) {
1009 return NULL;
1010 }
1011
1012 Trb = AllocateZeroPool (sizeof (SD_TRB));
1013 if (Trb == NULL) {
1014 return NULL;
1015 }
1016
1017 Trb->Slot = Slot;
1018 Trb->BlockSize = 0x200;
1019 Trb->Packet = Packet;
1020 Trb->Timeout = Packet->Timeout;
1021
1022 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1023 Trb->Data = Packet->InDataBuffer;
1024 Trb->DataLen = Packet->InTransferLength;
1025 Trb->Read = TRUE;
1026 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1027 Trb->Data = Packet->OutDataBuffer;
1028 Trb->DataLen = Packet->OutTransferLength;
1029 Trb->Read = FALSE;
1030 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1031 Trb->Data = NULL;
1032 Trb->DataLen = 0;
1033 } else {
1034 goto Error;
1035 }
1036
1037 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1038 Trb->BlockSize = (UINT16)Trb->DataLen;
1039 }
1040
1041 if (Packet->SdCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK) {
1042 Trb->Mode = SdPioMode;
1043 } else {
1044 if (Trb->Read) {
1045 MapOp = EdkiiIoMmuOperationBusMasterWrite;
1046 } else {
1047 MapOp = EdkiiIoMmuOperationBusMasterRead;
1048 }
1049
1050 if (Trb->DataLen != 0) {
1051 MapLength = Trb->DataLen;
1052 Status = IoMmuMap (MapOp, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap);
1053
1054 if (EFI_ERROR (Status) || (MapLength != Trb->DataLen)) {
1055 DEBUG ((DEBUG_ERROR, "SdPeimCreateTrb: Fail to map data buffer.\n"));
1056 goto Error;
1057 }
1058 }
1059
1060 if (Trb->DataLen == 0) {
1061 Trb->Mode = SdNoData;
1062 } else if (Capability.Adma2 != 0) {
1063 Trb->Mode = SdAdmaMode;
1064 Status = BuildAdmaDescTable (Trb);
1065 if (EFI_ERROR (Status)) {
1066 goto Error;
1067 }
1068 } else if (Capability.Sdma != 0) {
1069 Trb->Mode = SdSdmaMode;
1070 } else {
1071 Trb->Mode = SdPioMode;
1072 }
1073 }
1074 return Trb;
1075
1076 Error:
1077 SdPeimFreeTrb (Trb);
1078 return NULL;
1079 }
1080
1081 /**
1082 Free the resource used by the TRB.
1083
1084 @param[in] Trb The pointer to the SD_TRB instance.
1085
1086 **/
1087 VOID
1088 SdPeimFreeTrb (
1089 IN SD_TRB *Trb
1090 )
1091 {
1092 if ((Trb != NULL) && (Trb->DataMap != NULL)) {
1093 IoMmuUnmap (Trb->DataMap);
1094 }
1095
1096 if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
1097 SdPeimFreeMem (Trb->Slot->Private->Pool, Trb->AdmaDesc, Trb->AdmaDescSize);
1098 }
1099
1100 if (Trb != NULL) {
1101 FreePool (Trb);
1102 }
1103 return;
1104 }
1105
1106 /**
1107 Check if the env is ready for execute specified TRB.
1108
1109 @param[in] Bar The mmio base address of the slot to be accessed.
1110 @param[in] Trb The pointer to the SD_TRB instance.
1111
1112 @retval EFI_SUCCESS The env is ready for TRB execution.
1113 @retval EFI_NOT_READY The env is not ready for TRB execution.
1114 @retval Others Some erros happen.
1115
1116 **/
1117 EFI_STATUS
1118 SdPeimCheckTrbEnv (
1119 IN UINTN Bar,
1120 IN SD_TRB *Trb
1121 )
1122 {
1123 EFI_STATUS Status;
1124 SD_COMMAND_PACKET *Packet;
1125 UINT32 PresentState;
1126
1127 Packet = Trb->Packet;
1128
1129 if ((Packet->SdCmdBlk->CommandType == SdCommandTypeAdtc) ||
1130 (Packet->SdCmdBlk->ResponseType == SdResponseTypeR1b) ||
1131 (Packet->SdCmdBlk->ResponseType == SdResponseTypeR5b)) {
1132 //
1133 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1134 // the Present State register to be 0
1135 //
1136 PresentState = BIT0 | BIT1;
1137 } else {
1138 //
1139 // Wait Command Inhibit (CMD) in the Present State register
1140 // to be 0
1141 //
1142 PresentState = BIT0;
1143 }
1144
1145 Status = SdPeimHcCheckMmioSet (
1146 Bar + SD_HC_PRESENT_STATE,
1147 sizeof (PresentState),
1148 PresentState,
1149 0
1150 );
1151
1152 return Status;
1153 }
1154
1155 /**
1156 Wait for the env to be ready for execute specified TRB.
1157
1158 @param[in] Bar The mmio base address of the slot to be accessed.
1159 @param[in] Trb The pointer to the SD_TRB instance.
1160
1161 @retval EFI_SUCCESS The env is ready for TRB execution.
1162 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1163 @retval Others Some erros happen.
1164
1165 **/
1166 EFI_STATUS
1167 SdPeimWaitTrbEnv (
1168 IN UINTN Bar,
1169 IN SD_TRB *Trb
1170 )
1171 {
1172 EFI_STATUS Status;
1173 SD_COMMAND_PACKET *Packet;
1174 UINT64 Timeout;
1175 BOOLEAN InfiniteWait;
1176
1177 //
1178 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1179 //
1180 Packet = Trb->Packet;
1181 Timeout = Packet->Timeout;
1182 if (Timeout == 0) {
1183 InfiniteWait = TRUE;
1184 } else {
1185 InfiniteWait = FALSE;
1186 }
1187
1188 while (InfiniteWait || (Timeout > 0)) {
1189 //
1190 // Check Trb execution result by reading Normal Interrupt Status register.
1191 //
1192 Status = SdPeimCheckTrbEnv (Bar, Trb);
1193 if (Status != EFI_NOT_READY) {
1194 return Status;
1195 }
1196 //
1197 // Stall for 1 microsecond.
1198 //
1199 MicroSecondDelay (1);
1200
1201 Timeout--;
1202 }
1203
1204 return EFI_TIMEOUT;
1205 }
1206
1207 /**
1208 Execute the specified TRB.
1209
1210 @param[in] Bar The mmio base address of the slot to be accessed.
1211 @param[in] Trb The pointer to the SD_TRB instance.
1212
1213 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1214 @retval Others Some erros happen when sending this request to the host controller.
1215
1216 **/
1217 EFI_STATUS
1218 SdPeimExecTrb (
1219 IN UINTN Bar,
1220 IN SD_TRB *Trb
1221 )
1222 {
1223 EFI_STATUS Status;
1224 SD_COMMAND_PACKET *Packet;
1225 UINT16 Cmd;
1226 UINT16 IntStatus;
1227 UINT32 Argument;
1228 UINT16 BlkCount;
1229 UINT16 BlkSize;
1230 UINT16 TransMode;
1231 UINT8 HostCtrl1;
1232 UINT32 SdmaAddr;
1233 UINT64 AdmaAddr;
1234
1235 Packet = Trb->Packet;
1236 //
1237 // Clear all bits in Error Interrupt Status Register
1238 //
1239 IntStatus = 0xFFFF;
1240 Status = SdPeimHcRwMmio (Bar + SD_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1241 if (EFI_ERROR (Status)) {
1242 return Status;
1243 }
1244 //
1245 // Clear all bits in Normal Interrupt Status Register
1246 //
1247 IntStatus = 0xFFFF;
1248 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1249 if (EFI_ERROR (Status)) {
1250 return Status;
1251 }
1252 //
1253 // Set Host Control 1 register DMA Select field
1254 //
1255 if (Trb->Mode == SdAdmaMode) {
1256 HostCtrl1 = BIT4;
1257 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1258 if (EFI_ERROR (Status)) {
1259 return Status;
1260 }
1261 }
1262
1263 SdPeimHcLedOnOff (Bar, TRUE);
1264
1265 if (Trb->Mode == SdSdmaMode) {
1266 if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
1267 return EFI_INVALID_PARAMETER;
1268 }
1269
1270 SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
1271 Status = SdPeimHcRwMmio (Bar + SD_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1272 if (EFI_ERROR (Status)) {
1273 return Status;
1274 }
1275 } else if (Trb->Mode == SdAdmaMode) {
1276 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDesc;
1277 Status = SdPeimHcRwMmio (Bar + SD_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1278 if (EFI_ERROR (Status)) {
1279 return Status;
1280 }
1281 }
1282
1283 BlkSize = Trb->BlockSize;
1284 if (Trb->Mode == SdSdmaMode) {
1285 //
1286 // Set SDMA boundary to be 512K bytes.
1287 //
1288 BlkSize |= 0x7000;
1289 }
1290
1291 Status = SdPeimHcRwMmio (Bar + SD_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1292 if (EFI_ERROR (Status)) {
1293 return Status;
1294 }
1295
1296 BlkCount = 0;
1297 if (Trb->Mode != SdNoData) {
1298 //
1299 // Calcuate Block Count.
1300 //
1301 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1302 }
1303 Status = SdPeimHcRwMmio (Bar + SD_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1304 if (EFI_ERROR (Status)) {
1305 return Status;
1306 }
1307
1308 Argument = Packet->SdCmdBlk->CommandArgument;
1309 Status = SdPeimHcRwMmio (Bar + SD_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1310 if (EFI_ERROR (Status)) {
1311 return Status;
1312 }
1313
1314 TransMode = 0;
1315 if (Trb->Mode != SdNoData) {
1316 if (Trb->Mode != SdPioMode) {
1317 TransMode |= BIT0;
1318 }
1319 if (Trb->Read) {
1320 TransMode |= BIT4;
1321 }
1322 if (BlkCount > 1) {
1323 TransMode |= BIT5 | BIT1;
1324 }
1325 //
1326 // SD memory card needs to use AUTO CMD12 feature.
1327 //
1328 if (BlkCount > 1) {
1329 TransMode |= BIT2;
1330 }
1331 }
1332
1333 Status = SdPeimHcRwMmio (Bar + SD_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1334 if (EFI_ERROR (Status)) {
1335 return Status;
1336 }
1337
1338 Cmd = (UINT16)LShiftU64(Packet->SdCmdBlk->CommandIndex, 8);
1339 if (Packet->SdCmdBlk->CommandType == SdCommandTypeAdtc) {
1340 Cmd |= BIT5;
1341 }
1342 //
1343 // Convert ResponseType to value
1344 //
1345 if (Packet->SdCmdBlk->CommandType != SdCommandTypeBc) {
1346 switch (Packet->SdCmdBlk->ResponseType) {
1347 case SdResponseTypeR1:
1348 case SdResponseTypeR5:
1349 case SdResponseTypeR6:
1350 case SdResponseTypeR7:
1351 Cmd |= (BIT1 | BIT3 | BIT4);
1352 break;
1353 case SdResponseTypeR2:
1354 Cmd |= (BIT0 | BIT3);
1355 break;
1356 case SdResponseTypeR3:
1357 case SdResponseTypeR4:
1358 Cmd |= BIT1;
1359 break;
1360 case SdResponseTypeR1b:
1361 case SdResponseTypeR5b:
1362 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1363 break;
1364 default:
1365 ASSERT (FALSE);
1366 break;
1367 }
1368 }
1369 //
1370 // Execute cmd
1371 //
1372 Status = SdPeimHcRwMmio (Bar + SD_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1373 return Status;
1374 }
1375
1376 /**
1377 Check the TRB execution result.
1378
1379 @param[in] Bar The mmio base address of the slot to be accessed.
1380 @param[in] Trb The pointer to the SD_TRB instance.
1381
1382 @retval EFI_SUCCESS The TRB is executed successfully.
1383 @retval EFI_NOT_READY The TRB is not completed for execution.
1384 @retval Others Some erros happen when executing this request.
1385
1386 **/
1387 EFI_STATUS
1388 SdPeimCheckTrbResult (
1389 IN UINTN Bar,
1390 IN SD_TRB *Trb
1391 )
1392 {
1393 EFI_STATUS Status;
1394 SD_COMMAND_PACKET *Packet;
1395 UINT16 IntStatus;
1396 UINT32 Response[4];
1397 UINT32 SdmaAddr;
1398 UINT8 Index;
1399 UINT8 SwReset;
1400 UINT32 PioLength;
1401
1402 SwReset = 0;
1403 Packet = Trb->Packet;
1404 //
1405 // Check Trb execution result by reading Normal Interrupt Status register.
1406 //
1407 Status = SdPeimHcRwMmio (
1408 Bar + SD_HC_NOR_INT_STS,
1409 TRUE,
1410 sizeof (IntStatus),
1411 &IntStatus
1412 );
1413 if (EFI_ERROR (Status)) {
1414 goto Done;
1415 }
1416 //
1417 // Check Transfer Complete bit is set or not.
1418 //
1419 if ((IntStatus & BIT1) == BIT1) {
1420 if ((IntStatus & BIT15) == BIT15) {
1421 //
1422 // Read Error Interrupt Status register to check if the error is
1423 // Data Timeout Error.
1424 // If yes, treat it as success as Transfer Complete has higher
1425 // priority than Data Timeout Error.
1426 //
1427 Status = SdPeimHcRwMmio (
1428 Bar + SD_HC_ERR_INT_STS,
1429 TRUE,
1430 sizeof (IntStatus),
1431 &IntStatus
1432 );
1433 if (!EFI_ERROR (Status)) {
1434 if ((IntStatus & BIT4) == BIT4) {
1435 Status = EFI_SUCCESS;
1436 } else {
1437 Status = EFI_DEVICE_ERROR;
1438 }
1439 }
1440 }
1441
1442 goto Done;
1443 }
1444 //
1445 // Check if there is a error happened during cmd execution.
1446 // If yes, then do error recovery procedure to follow SD Host Controller
1447 // Simplified Spec 3.0 section 3.10.1.
1448 //
1449 if ((IntStatus & BIT15) == BIT15) {
1450 Status = SdPeimHcRwMmio (
1451 Bar + SD_HC_ERR_INT_STS,
1452 TRUE,
1453 sizeof (IntStatus),
1454 &IntStatus
1455 );
1456 if (EFI_ERROR (Status)) {
1457 goto Done;
1458 }
1459
1460 if ((IntStatus & 0x0F) != 0) {
1461 SwReset |= BIT1;
1462 }
1463 if ((IntStatus & 0xF0) != 0) {
1464 SwReset |= BIT2;
1465 }
1466
1467 Status = SdPeimHcRwMmio (
1468 Bar + SD_HC_SW_RST,
1469 FALSE,
1470 sizeof (SwReset),
1471 &SwReset
1472 );
1473 if (EFI_ERROR (Status)) {
1474 goto Done;
1475 }
1476 Status = SdPeimHcWaitMmioSet (
1477 Bar + SD_HC_SW_RST,
1478 sizeof (SwReset),
1479 0xFF,
1480 0,
1481 SD_TIMEOUT
1482 );
1483 if (EFI_ERROR (Status)) {
1484 goto Done;
1485 }
1486
1487 Status = EFI_DEVICE_ERROR;
1488 goto Done;
1489 }
1490 //
1491 // Check if DMA interrupt is signalled for the SDMA transfer.
1492 //
1493 if ((Trb->Mode == SdSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1494 //
1495 // Clear DMA interrupt bit.
1496 //
1497 IntStatus = BIT3;
1498 Status = SdPeimHcRwMmio (
1499 Bar + SD_HC_NOR_INT_STS,
1500 FALSE,
1501 sizeof (IntStatus),
1502 &IntStatus
1503 );
1504 if (EFI_ERROR (Status)) {
1505 goto Done;
1506 }
1507 //
1508 // Update SDMA Address register.
1509 //
1510 SdmaAddr = SD_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_SDMA_BOUNDARY);
1511 Status = SdPeimHcRwMmio (
1512 Bar + SD_HC_SDMA_ADDR,
1513 FALSE,
1514 sizeof (UINT32),
1515 &SdmaAddr
1516 );
1517 if (EFI_ERROR (Status)) {
1518 goto Done;
1519 }
1520 Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
1521 }
1522
1523 if ((Packet->SdCmdBlk->CommandType != SdCommandTypeAdtc) &&
1524 (Packet->SdCmdBlk->ResponseType != SdResponseTypeR1b) &&
1525 (Packet->SdCmdBlk->ResponseType != SdResponseTypeR5b)) {
1526 if ((IntStatus & BIT0) == BIT0) {
1527 Status = EFI_SUCCESS;
1528 goto Done;
1529 }
1530 }
1531
1532 if (Packet->SdCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK) {
1533 //
1534 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
1535 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
1536 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
1537 //
1538 if ((IntStatus & BIT5) == BIT5) {
1539 //
1540 // Clear Buffer Read Ready interrupt at first.
1541 //
1542 IntStatus = BIT5;
1543 SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1544 //
1545 // Read data out from Buffer Port register
1546 //
1547 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
1548 SdPeimHcRwMmio (Bar + SD_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
1549 }
1550 Status = EFI_SUCCESS;
1551 goto Done;
1552 }
1553 }
1554
1555 Status = EFI_NOT_READY;
1556 Done:
1557 //
1558 // Get response data when the cmd is executed successfully.
1559 //
1560 if (!EFI_ERROR (Status)) {
1561 if (Packet->SdCmdBlk->CommandType != SdCommandTypeBc) {
1562 for (Index = 0; Index < 4; Index++) {
1563 Status = SdPeimHcRwMmio (
1564 Bar + SD_HC_RESPONSE + Index * 4,
1565 TRUE,
1566 sizeof (UINT32),
1567 &Response[Index]
1568 );
1569 if (EFI_ERROR (Status)) {
1570 SdPeimHcLedOnOff (Bar, FALSE);
1571 return Status;
1572 }
1573 }
1574 CopyMem (Packet->SdStatusBlk, Response, sizeof (Response));
1575 }
1576 }
1577
1578 if (Status != EFI_NOT_READY) {
1579 SdPeimHcLedOnOff (Bar, FALSE);
1580 }
1581
1582 return Status;
1583 }
1584
1585 /**
1586 Wait for the TRB execution result.
1587
1588 @param[in] Bar The mmio base address of the slot to be accessed.
1589 @param[in] Trb The pointer to the SD_TRB instance.
1590
1591 @retval EFI_SUCCESS The TRB is executed successfully.
1592 @retval Others Some erros happen when executing this request.
1593
1594 **/
1595 EFI_STATUS
1596 SdPeimWaitTrbResult (
1597 IN UINTN Bar,
1598 IN SD_TRB *Trb
1599 )
1600 {
1601 EFI_STATUS Status;
1602 SD_COMMAND_PACKET *Packet;
1603 UINT64 Timeout;
1604 BOOLEAN InfiniteWait;
1605
1606 Packet = Trb->Packet;
1607 //
1608 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1609 //
1610 Timeout = Packet->Timeout;
1611 if (Timeout == 0) {
1612 InfiniteWait = TRUE;
1613 } else {
1614 InfiniteWait = FALSE;
1615 }
1616
1617 while (InfiniteWait || (Timeout > 0)) {
1618 //
1619 // Check Trb execution result by reading Normal Interrupt Status register.
1620 //
1621 Status = SdPeimCheckTrbResult (Bar, Trb);
1622 if (Status != EFI_NOT_READY) {
1623 return Status;
1624 }
1625 //
1626 // Stall for 1 microsecond.
1627 //
1628 MicroSecondDelay (1);
1629
1630 Timeout--;
1631 }
1632
1633 return EFI_TIMEOUT;
1634 }
1635
1636 /**
1637 Sends SD command to an SD card that is attached to the SD controller.
1638
1639 If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.
1640
1641 If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
1642
1643 If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER
1644 is returned.
1645
1646 If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
1647 EFI_INVALID_PARAMETER is returned.
1648
1649 @param[in] Slot The slot number of the Sd card to send the command to.
1650 @param[in,out] Packet A pointer to the SD command data structure.
1651
1652 @retval EFI_SUCCESS The SD Command Packet was sent by the host.
1653 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD
1654 command Packet.
1655 @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
1656 @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
1657 OutDataBuffer are NULL.
1658 @retval EFI_NO_MEDIA SD Device not present in the Slot.
1659 @retval EFI_UNSUPPORTED The command described by the SD Command Packet is not
1660 supported by the host controller.
1661 @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the
1662 limit supported by SD card ( i.e. if the number of bytes
1663 exceed the Last LBA).
1664
1665 **/
1666 EFI_STATUS
1667 EFIAPI
1668 SdPeimExecCmd (
1669 IN SD_PEIM_HC_SLOT *Slot,
1670 IN OUT SD_COMMAND_PACKET *Packet
1671 )
1672 {
1673 EFI_STATUS Status;
1674 SD_TRB *Trb;
1675
1676 if (Packet == NULL) {
1677 return EFI_INVALID_PARAMETER;
1678 }
1679
1680 if ((Packet->SdCmdBlk == NULL) || (Packet->SdStatusBlk == NULL)) {
1681 return EFI_INVALID_PARAMETER;
1682 }
1683
1684 if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
1685 return EFI_INVALID_PARAMETER;
1686 }
1687
1688 if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
1689 return EFI_INVALID_PARAMETER;
1690 }
1691
1692 Trb = SdPeimCreateTrb (Slot, Packet);
1693 if (Trb == NULL) {
1694 return EFI_OUT_OF_RESOURCES;
1695 }
1696
1697 Status = SdPeimWaitTrbEnv (Slot->SdHcBase, Trb);
1698 if (EFI_ERROR (Status)) {
1699 goto Done;
1700 }
1701
1702 Status = SdPeimExecTrb (Slot->SdHcBase, Trb);
1703 if (EFI_ERROR (Status)) {
1704 goto Done;
1705 }
1706
1707 Status = SdPeimWaitTrbResult (Slot->SdHcBase, Trb);
1708 if (EFI_ERROR (Status)) {
1709 goto Done;
1710 }
1711
1712 Done:
1713 SdPeimFreeTrb (Trb);
1714
1715 return Status;
1716 }
1717
1718 /**
1719 Send command GO_IDLE_STATE to the device to make it go to Idle State.
1720
1721 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1722
1723 @param[in] Slot The slot number of the SD card to send the command to.
1724
1725 @retval EFI_SUCCESS The SD device is reset correctly.
1726 @retval Others The device reset fails.
1727
1728 **/
1729 EFI_STATUS
1730 SdPeimReset (
1731 IN SD_PEIM_HC_SLOT *Slot
1732 )
1733 {
1734 SD_COMMAND_BLOCK SdCmdBlk;
1735 SD_STATUS_BLOCK SdStatusBlk;
1736 SD_COMMAND_PACKET Packet;
1737 EFI_STATUS Status;
1738
1739 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1740 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1741 ZeroMem (&Packet, sizeof (Packet));
1742
1743 Packet.SdCmdBlk = &SdCmdBlk;
1744 Packet.SdStatusBlk = &SdStatusBlk;
1745 Packet.Timeout = SD_TIMEOUT;
1746
1747 SdCmdBlk.CommandIndex = SD_GO_IDLE_STATE;
1748 SdCmdBlk.CommandType = SdCommandTypeBc;
1749 SdCmdBlk.ResponseType = 0;
1750 SdCmdBlk.CommandArgument = 0;
1751
1752 Status = SdPeimExecCmd (Slot, &Packet);
1753
1754 return Status;
1755 }
1756
1757 /**
1758 Send command SEND_IF_COND to the device to inquiry the SD Memory Card interface
1759 condition.
1760
1761 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1762
1763 @param[in] Slot The slot number of the SD card to send the command to.
1764 @param[in] SupplyVoltage The supplied voltage by the host.
1765 @param[in] CheckPattern The check pattern to be sent to the device.
1766
1767 @retval EFI_SUCCESS The operation is done correctly.
1768 @retval Others The operation fails.
1769
1770 **/
1771 EFI_STATUS
1772 SdPeimVoltageCheck (
1773 IN SD_PEIM_HC_SLOT *Slot,
1774 IN UINT8 SupplyVoltage,
1775 IN UINT8 CheckPattern
1776 )
1777 {
1778 SD_COMMAND_BLOCK SdCmdBlk;
1779 SD_STATUS_BLOCK SdStatusBlk;
1780 SD_COMMAND_PACKET Packet;
1781 EFI_STATUS Status;
1782
1783 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1784 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1785 ZeroMem (&Packet, sizeof (Packet));
1786
1787 Packet.SdCmdBlk = &SdCmdBlk;
1788 Packet.SdStatusBlk = &SdStatusBlk;
1789 Packet.Timeout = SD_TIMEOUT;
1790
1791 SdCmdBlk.CommandIndex = SD_SEND_IF_COND;
1792 SdCmdBlk.CommandType = SdCommandTypeBcr;
1793 SdCmdBlk.ResponseType = SdResponseTypeR7;
1794 SdCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern;
1795
1796 Status = SdPeimExecCmd (Slot, &Packet);
1797 if (!EFI_ERROR (Status)) {
1798 if (SdStatusBlk.Resp0 != SdCmdBlk.CommandArgument) {
1799 return EFI_DEVICE_ERROR;
1800 }
1801 }
1802
1803 return Status;
1804 }
1805
1806 /**
1807 Send command SDIO_SEND_OP_COND to the device to see whether it is SDIO device.
1808
1809 Refer to SDIO Simplified Spec 3 Section 3.2 for details.
1810
1811 @param[in] Slot The slot number of the SD card to send the command to.
1812 @param[in] VoltageWindow The supply voltage window.
1813 @param[in] S18r The boolean to show if it should switch to 1.8v.
1814
1815 @retval EFI_SUCCESS The operation is done correctly.
1816 @retval Others The operation fails.
1817
1818 **/
1819 EFI_STATUS
1820 SdioSendOpCond (
1821 IN SD_PEIM_HC_SLOT *Slot,
1822 IN UINT32 VoltageWindow,
1823 IN BOOLEAN S18r
1824 )
1825 {
1826 SD_COMMAND_BLOCK SdCmdBlk;
1827 SD_STATUS_BLOCK SdStatusBlk;
1828 SD_COMMAND_PACKET Packet;
1829 EFI_STATUS Status;
1830 UINT32 Switch;
1831
1832 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1833 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1834 ZeroMem (&Packet, sizeof (Packet));
1835
1836 Packet.SdCmdBlk = &SdCmdBlk;
1837 Packet.SdStatusBlk = &SdStatusBlk;
1838 Packet.Timeout = SD_TIMEOUT;
1839
1840 SdCmdBlk.CommandIndex = SDIO_SEND_OP_COND;
1841 SdCmdBlk.CommandType = SdCommandTypeBcr;
1842 SdCmdBlk.ResponseType = SdResponseTypeR4;
1843
1844 Switch = S18r ? BIT24 : 0;
1845
1846 SdCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch;
1847
1848 Status = SdPeimExecCmd (Slot, &Packet);
1849
1850 return Status;
1851 }
1852
1853 /**
1854 Send command SD_SEND_OP_COND to the device to see whether it is SDIO device.
1855
1856 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1857
1858 @param[in] Slot The slot number of the SD card to send the command to.
1859 @param[in] Rca The relative device address of addressed device.
1860 @param[in] VoltageWindow The supply voltage window.
1861 @param[in] S18r The boolean to show if it should switch to 1.8v.
1862 @param[in] Xpc The boolean to show if it should provide 0.36w power control.
1863 @param[in] Hcs The boolean to show if it support host capacity info.
1864 @param[out] Ocr The buffer to store returned OCR register value.
1865
1866
1867 @retval EFI_SUCCESS The operation is done correctly.
1868 @retval Others The operation fails.
1869
1870 **/
1871 EFI_STATUS
1872 SdPeimSendOpCond (
1873 IN SD_PEIM_HC_SLOT *Slot,
1874 IN UINT16 Rca,
1875 IN UINT32 VoltageWindow,
1876 IN BOOLEAN S18r,
1877 IN BOOLEAN Xpc,
1878 IN BOOLEAN Hcs,
1879 OUT UINT32 *Ocr
1880 )
1881 {
1882 SD_COMMAND_BLOCK SdCmdBlk;
1883 SD_STATUS_BLOCK SdStatusBlk;
1884 SD_COMMAND_PACKET Packet;
1885 EFI_STATUS Status;
1886 UINT32 Switch;
1887 UINT32 MaxPower;
1888 UINT32 HostCapacity;
1889
1890 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1891 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1892 ZeroMem (&Packet, sizeof (Packet));
1893
1894 Packet.SdCmdBlk = &SdCmdBlk;
1895 Packet.SdStatusBlk = &SdStatusBlk;
1896 Packet.Timeout = SD_TIMEOUT;
1897
1898 SdCmdBlk.CommandIndex = SD_APP_CMD;
1899 SdCmdBlk.CommandType = SdCommandTypeAc;
1900 SdCmdBlk.ResponseType = SdResponseTypeR1;
1901 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
1902
1903 Status = SdPeimExecCmd (Slot, &Packet);
1904 if (EFI_ERROR (Status)) {
1905 return Status;
1906 }
1907
1908 SdCmdBlk.CommandIndex = SD_SEND_OP_COND;
1909 SdCmdBlk.CommandType = SdCommandTypeBcr;
1910 SdCmdBlk.ResponseType = SdResponseTypeR3;
1911
1912 Switch = S18r ? BIT24 : 0;
1913 MaxPower = Xpc ? BIT28 : 0;
1914 HostCapacity = Hcs ? BIT30 : 0;
1915 SdCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch | MaxPower | HostCapacity;
1916
1917 Status = SdPeimExecCmd (Slot, &Packet);
1918 if (!EFI_ERROR (Status)) {
1919 //
1920 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
1921 //
1922 *Ocr = SdStatusBlk.Resp0;
1923 }
1924
1925 return Status;
1926 }
1927
1928 /**
1929 Broadcast command ALL_SEND_CID to the bus to ask all the SD devices to send the
1930 data of their CID registers.
1931
1932 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1933
1934 @param[in] Slot The slot number of the SD card to send the command to.
1935
1936 @retval EFI_SUCCESS The operation is done correctly.
1937 @retval Others The operation fails.
1938
1939 **/
1940 EFI_STATUS
1941 SdPeimAllSendCid (
1942 IN SD_PEIM_HC_SLOT *Slot
1943 )
1944 {
1945 SD_COMMAND_BLOCK SdCmdBlk;
1946 SD_STATUS_BLOCK SdStatusBlk;
1947 SD_COMMAND_PACKET Packet;
1948 EFI_STATUS Status;
1949
1950 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1951 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1952 ZeroMem (&Packet, sizeof (Packet));
1953
1954 Packet.SdCmdBlk = &SdCmdBlk;
1955 Packet.SdStatusBlk = &SdStatusBlk;
1956 Packet.Timeout = SD_TIMEOUT;
1957
1958 SdCmdBlk.CommandIndex = SD_ALL_SEND_CID;
1959 SdCmdBlk.CommandType = SdCommandTypeBcr;
1960 SdCmdBlk.ResponseType = SdResponseTypeR2;
1961 SdCmdBlk.CommandArgument = 0;
1962
1963 Status = SdPeimExecCmd (Slot, &Packet);
1964
1965 return Status;
1966 }
1967
1968 /**
1969 Send command SET_RELATIVE_ADDR to the SD device to assign a Relative device
1970 Address (RCA).
1971
1972 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1973
1974 @param[in] Slot The slot number of the SD card to send the command to.
1975 @param[out] Rca The relative device address to be assigned.
1976
1977 @retval EFI_SUCCESS The operation is done correctly.
1978 @retval Others The operation fails.
1979
1980 **/
1981 EFI_STATUS
1982 SdPeimSetRca (
1983 IN SD_PEIM_HC_SLOT *Slot,
1984 OUT UINT16 *Rca
1985 )
1986 {
1987 SD_COMMAND_BLOCK SdCmdBlk;
1988 SD_STATUS_BLOCK SdStatusBlk;
1989 SD_COMMAND_PACKET Packet;
1990 EFI_STATUS Status;
1991
1992 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1993 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1994 ZeroMem (&Packet, sizeof (Packet));
1995
1996 Packet.SdCmdBlk = &SdCmdBlk;
1997 Packet.SdStatusBlk = &SdStatusBlk;
1998 Packet.Timeout = SD_TIMEOUT;
1999
2000 SdCmdBlk.CommandIndex = SD_SET_RELATIVE_ADDR;
2001 SdCmdBlk.CommandType = SdCommandTypeBcr;
2002 SdCmdBlk.ResponseType = SdResponseTypeR6;
2003
2004 Status = SdPeimExecCmd (Slot, &Packet);
2005 if (!EFI_ERROR (Status)) {
2006 *Rca = (UINT16)(SdStatusBlk.Resp0 >> 16);
2007 }
2008
2009 return Status;
2010 }
2011
2012 /**
2013 Send command SEND_CSD to the SD device to get the data of the CSD register.
2014
2015 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2016
2017 @param[in] Slot The slot number of the SD card to send the command to.
2018 @param[in] Rca The relative device address of selected device.
2019 @param[out] Csd The buffer to store the content of the CSD register.
2020 Note the caller should ignore the lowest byte of this
2021 buffer as the content of this byte is meaningless even
2022 if the operation succeeds.
2023
2024 @retval EFI_SUCCESS The operation is done correctly.
2025 @retval Others The operation fails.
2026
2027 **/
2028 EFI_STATUS
2029 SdPeimGetCsd (
2030 IN SD_PEIM_HC_SLOT *Slot,
2031 IN UINT16 Rca,
2032 OUT SD_CSD *Csd
2033 )
2034 {
2035 SD_COMMAND_BLOCK SdCmdBlk;
2036 SD_STATUS_BLOCK SdStatusBlk;
2037 SD_COMMAND_PACKET Packet;
2038 EFI_STATUS Status;
2039
2040 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2041 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2042 ZeroMem (&Packet, sizeof (Packet));
2043
2044 Packet.SdCmdBlk = &SdCmdBlk;
2045 Packet.SdStatusBlk = &SdStatusBlk;
2046 Packet.Timeout = SD_TIMEOUT;
2047
2048 SdCmdBlk.CommandIndex = SD_SEND_CSD;
2049 SdCmdBlk.CommandType = SdCommandTypeAc;
2050 SdCmdBlk.ResponseType = SdResponseTypeR2;
2051 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2052
2053 Status = SdPeimExecCmd (Slot, &Packet);
2054 if (!EFI_ERROR (Status)) {
2055 //
2056 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
2057 //
2058 CopyMem (((UINT8*)Csd) + 1, &SdStatusBlk.Resp0, sizeof (SD_CSD) - 1);
2059 }
2060
2061 return Status;
2062 }
2063
2064 /**
2065 Send command SELECT_DESELECT_CARD to the SD device to select/deselect it.
2066
2067 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2068
2069 @param[in] Slot The slot number of the SD card to send the command to.
2070 @param[in] Rca The relative device address of selected device.
2071
2072 @retval EFI_SUCCESS The operation is done correctly.
2073 @retval Others The operation fails.
2074
2075 **/
2076 EFI_STATUS
2077 SdPeimSelect (
2078 IN SD_PEIM_HC_SLOT *Slot,
2079 IN UINT16 Rca
2080 )
2081 {
2082 SD_COMMAND_BLOCK SdCmdBlk;
2083 SD_STATUS_BLOCK SdStatusBlk;
2084 SD_COMMAND_PACKET Packet;
2085 EFI_STATUS Status;
2086
2087 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2088 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2089 ZeroMem (&Packet, sizeof (Packet));
2090
2091 Packet.SdCmdBlk = &SdCmdBlk;
2092 Packet.SdStatusBlk = &SdStatusBlk;
2093 Packet.Timeout = SD_TIMEOUT;
2094
2095 SdCmdBlk.CommandIndex = SD_SELECT_DESELECT_CARD;
2096 SdCmdBlk.CommandType = SdCommandTypeAc;
2097 SdCmdBlk.ResponseType = SdResponseTypeR1b;
2098 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2099
2100 Status = SdPeimExecCmd (Slot, &Packet);
2101
2102 return Status;
2103 }
2104
2105 /**
2106 Send command VOLTAGE_SWITCH to the SD device to switch the voltage of the device.
2107
2108 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2109
2110 @param[in] Slot The slot number of the SD card to send the command to.
2111
2112 @retval EFI_SUCCESS The operation is done correctly.
2113 @retval Others The operation fails.
2114
2115 **/
2116 EFI_STATUS
2117 SdPeimVoltageSwitch (
2118 IN SD_PEIM_HC_SLOT *Slot
2119 )
2120 {
2121 SD_COMMAND_BLOCK SdCmdBlk;
2122 SD_STATUS_BLOCK SdStatusBlk;
2123 SD_COMMAND_PACKET Packet;
2124 EFI_STATUS Status;
2125
2126 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2127 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2128 ZeroMem (&Packet, sizeof (Packet));
2129
2130 Packet.SdCmdBlk = &SdCmdBlk;
2131 Packet.SdStatusBlk = &SdStatusBlk;
2132 Packet.Timeout = SD_TIMEOUT;
2133
2134 SdCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
2135 SdCmdBlk.CommandType = SdCommandTypeAc;
2136 SdCmdBlk.ResponseType = SdResponseTypeR1;
2137 SdCmdBlk.CommandArgument = 0;
2138
2139 Status = SdPeimExecCmd (Slot, &Packet);
2140
2141 return Status;
2142 }
2143
2144 /**
2145 Send command SET_BUS_WIDTH to the SD device to set the bus width.
2146
2147 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2148
2149 @param[in] Slot The slot number of the SD card to send the command to.
2150 @param[in] Rca The relative device address of addressed device.
2151 @param[in] BusWidth The bus width to be set, it could be 1 or 4.
2152
2153 @retval EFI_SUCCESS The operation is done correctly.
2154 @retval Others The operation fails.
2155
2156 **/
2157 EFI_STATUS
2158 SdPeimSetBusWidth (
2159 IN SD_PEIM_HC_SLOT *Slot,
2160 IN UINT16 Rca,
2161 IN UINT8 BusWidth
2162 )
2163 {
2164 SD_COMMAND_BLOCK SdCmdBlk;
2165 SD_STATUS_BLOCK SdStatusBlk;
2166 SD_COMMAND_PACKET Packet;
2167 EFI_STATUS Status;
2168 UINT8 Value;
2169
2170 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2171 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2172 ZeroMem (&Packet, sizeof (Packet));
2173
2174 Packet.SdCmdBlk = &SdCmdBlk;
2175 Packet.SdStatusBlk = &SdStatusBlk;
2176 Packet.Timeout = SD_TIMEOUT;
2177
2178 SdCmdBlk.CommandIndex = SD_APP_CMD;
2179 SdCmdBlk.CommandType = SdCommandTypeAc;
2180 SdCmdBlk.ResponseType = SdResponseTypeR1;
2181 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2182
2183 Status = SdPeimExecCmd (Slot, &Packet);
2184 if (EFI_ERROR (Status)) {
2185 return Status;
2186 }
2187
2188 SdCmdBlk.CommandIndex = SD_SET_BUS_WIDTH;
2189 SdCmdBlk.CommandType = SdCommandTypeAc;
2190 SdCmdBlk.ResponseType = SdResponseTypeR1;
2191
2192 if (BusWidth == 1) {
2193 Value = 0;
2194 } else if (BusWidth == 4) {
2195 Value = 2;
2196 } else {
2197 return EFI_INVALID_PARAMETER;
2198 }
2199 SdCmdBlk.CommandArgument = Value & 0x3;
2200
2201 Status = SdPeimExecCmd (Slot, &Packet);
2202
2203 return Status;
2204 }
2205
2206 /**
2207 Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.
2208
2209 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2210
2211 @param[in] Slot The slot number of the SD card to send the command to.
2212 @param[in] AccessMode The value for access mode group.
2213 @param[in] CommandSystem The value for command set group.
2214 @param[in] DriveStrength The value for drive length group.
2215 @param[in] PowerLimit The value for power limit group.
2216 @param[in] Mode Switch or check function.
2217 @param[out] SwitchResp The return switch function status.
2218
2219 @retval EFI_SUCCESS The operation is done correctly.
2220 @retval Others The operation fails.
2221
2222 **/
2223 EFI_STATUS
2224 SdPeimSwitch (
2225 IN SD_PEIM_HC_SLOT *Slot,
2226 IN UINT8 AccessMode,
2227 IN UINT8 CommandSystem,
2228 IN UINT8 DriveStrength,
2229 IN UINT8 PowerLimit,
2230 IN BOOLEAN Mode,
2231 OUT UINT8 *SwitchResp
2232 )
2233 {
2234 SD_COMMAND_BLOCK SdCmdBlk;
2235 SD_STATUS_BLOCK SdStatusBlk;
2236 SD_COMMAND_PACKET Packet;
2237 EFI_STATUS Status;
2238 UINT32 ModeValue;
2239
2240 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2241 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2242 ZeroMem (&Packet, sizeof (Packet));
2243
2244 Packet.SdCmdBlk = &SdCmdBlk;
2245 Packet.SdStatusBlk = &SdStatusBlk;
2246 Packet.Timeout = SD_TIMEOUT;
2247
2248 SdCmdBlk.CommandIndex = SD_SWITCH_FUNC;
2249 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2250 SdCmdBlk.ResponseType = SdResponseTypeR1;
2251
2252 ModeValue = Mode ? BIT31 : 0;
2253 SdCmdBlk.CommandArgument = (AccessMode & 0xF) | ((PowerLimit & 0xF) << 4) | \
2254 ((DriveStrength & 0xF) << 8) | ((DriveStrength & 0xF) << 12) | \
2255 ModeValue;
2256 Packet.InDataBuffer = SwitchResp;
2257 Packet.InTransferLength = 64;
2258
2259 Status = SdPeimExecCmd (Slot, &Packet);
2260
2261 return Status;
2262 }
2263
2264 /**
2265 Send command SEND_STATUS to the addressed SD device to get its status register.
2266
2267 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2268
2269 @param[in] Slot The slot number of the SD card to send the command to.
2270 @param[in] Rca The relative device address of addressed device.
2271 @param[out] DevStatus The returned device status.
2272
2273 @retval EFI_SUCCESS The operation is done correctly.
2274 @retval Others The operation fails.
2275
2276 **/
2277 EFI_STATUS
2278 SdPeimSendStatus (
2279 IN SD_PEIM_HC_SLOT *Slot,
2280 IN UINT16 Rca,
2281 OUT UINT32 *DevStatus
2282 )
2283 {
2284 SD_COMMAND_BLOCK SdCmdBlk;
2285 SD_STATUS_BLOCK SdStatusBlk;
2286 SD_COMMAND_PACKET Packet;
2287 EFI_STATUS Status;
2288
2289 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2290 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2291 ZeroMem (&Packet, sizeof (Packet));
2292
2293 Packet.SdCmdBlk = &SdCmdBlk;
2294 Packet.SdStatusBlk = &SdStatusBlk;
2295 Packet.Timeout = SD_TIMEOUT;
2296
2297 SdCmdBlk.CommandIndex = SD_SEND_STATUS;
2298 SdCmdBlk.CommandType = SdCommandTypeAc;
2299 SdCmdBlk.ResponseType = SdResponseTypeR1;
2300 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2301
2302 Status = SdPeimExecCmd (Slot, &Packet);
2303 if (!EFI_ERROR (Status)) {
2304 *DevStatus = SdStatusBlk.Resp0;
2305 }
2306
2307 return Status;
2308 }
2309
2310 /**
2311 Send command READ_SINGLE_BLOCK/WRITE_SINGLE_BLOCK to the addressed SD device
2312 to read/write the specified number of blocks.
2313
2314 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2315
2316 @param[in] Slot The slot number of the SD card to send the command to.
2317 @param[in] Lba The logical block address of starting access.
2318 @param[in] BlockSize The block size of specified SD device partition.
2319 @param[in] Buffer The pointer to the transfer buffer.
2320 @param[in] BufferSize The size of transfer buffer.
2321 @param[in] IsRead Boolean to show the operation direction.
2322
2323 @retval EFI_SUCCESS The operation is done correctly.
2324 @retval Others The operation fails.
2325
2326 **/
2327 EFI_STATUS
2328 SdPeimRwSingleBlock (
2329 IN SD_PEIM_HC_SLOT *Slot,
2330 IN EFI_LBA Lba,
2331 IN UINT32 BlockSize,
2332 IN VOID *Buffer,
2333 IN UINTN BufferSize,
2334 IN BOOLEAN IsRead
2335 )
2336 {
2337 SD_COMMAND_BLOCK SdCmdBlk;
2338 SD_STATUS_BLOCK SdStatusBlk;
2339 SD_COMMAND_PACKET Packet;
2340 EFI_STATUS Status;
2341
2342 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2343 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2344 ZeroMem (&Packet, sizeof (Packet));
2345
2346 Packet.SdCmdBlk = &SdCmdBlk;
2347 Packet.SdStatusBlk = &SdStatusBlk;
2348 //
2349 // Calculate timeout value through the below formula.
2350 // Timeout = (transfer size) / (2MB/s).
2351 // Taking 2MB/s as divisor is because it's the lowest
2352 // transfer speed of class 2.
2353 //
2354 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;
2355
2356 if (IsRead) {
2357 Packet.InDataBuffer = Buffer;
2358 Packet.InTransferLength = (UINT32)BufferSize;
2359
2360 SdCmdBlk.CommandIndex = SD_READ_SINGLE_BLOCK;
2361 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2362 SdCmdBlk.ResponseType = SdResponseTypeR1;
2363 } else {
2364 Packet.OutDataBuffer = Buffer;
2365 Packet.OutTransferLength = (UINT32)BufferSize;
2366
2367 SdCmdBlk.CommandIndex = SD_WRITE_SINGLE_BLOCK;
2368 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2369 SdCmdBlk.ResponseType = SdResponseTypeR1;
2370 }
2371
2372 if (Slot->SectorAddressing) {
2373 SdCmdBlk.CommandArgument = (UINT32)Lba;
2374 } else {
2375 SdCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);
2376 }
2377
2378 Status = SdPeimExecCmd (Slot, &Packet);
2379
2380 return Status;
2381 }
2382
2383 /**
2384 Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed SD device
2385 to read/write the specified number of blocks.
2386
2387 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2388
2389 @param[in] Slot The slot number of the SD card to send the command to.
2390 @param[in] Lba The logical block address of starting access.
2391 @param[in] BlockSize The block size of specified SD device partition.
2392 @param[in] Buffer The pointer to the transfer buffer.
2393 @param[in] BufferSize The size of transfer buffer.
2394 @param[in] IsRead Boolean to show the operation direction.
2395
2396 @retval EFI_SUCCESS The operation is done correctly.
2397 @retval Others The operation fails.
2398
2399 **/
2400 EFI_STATUS
2401 SdPeimRwMultiBlocks (
2402 IN SD_PEIM_HC_SLOT *Slot,
2403 IN EFI_LBA Lba,
2404 IN UINT32 BlockSize,
2405 IN VOID *Buffer,
2406 IN UINTN BufferSize,
2407 IN BOOLEAN IsRead
2408 )
2409 {
2410 SD_COMMAND_BLOCK SdCmdBlk;
2411 SD_STATUS_BLOCK SdStatusBlk;
2412 SD_COMMAND_PACKET Packet;
2413 EFI_STATUS Status;
2414
2415 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2416 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2417 ZeroMem (&Packet, sizeof (Packet));
2418
2419 Packet.SdCmdBlk = &SdCmdBlk;
2420 Packet.SdStatusBlk = &SdStatusBlk;
2421 //
2422 // Calculate timeout value through the below formula.
2423 // Timeout = (transfer size) / (2MB/s).
2424 // Taking 2MB/s as divisor is because it's the lowest
2425 // transfer speed of class 2.
2426 //
2427 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;
2428
2429 if (IsRead) {
2430 Packet.InDataBuffer = Buffer;
2431 Packet.InTransferLength = (UINT32)BufferSize;
2432
2433 SdCmdBlk.CommandIndex = SD_READ_MULTIPLE_BLOCK;
2434 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2435 SdCmdBlk.ResponseType = SdResponseTypeR1;
2436 } else {
2437 Packet.OutDataBuffer = Buffer;
2438 Packet.OutTransferLength = (UINT32)BufferSize;
2439
2440 SdCmdBlk.CommandIndex = SD_WRITE_MULTIPLE_BLOCK;
2441 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2442 SdCmdBlk.ResponseType = SdResponseTypeR1;
2443 }
2444
2445 if (Slot->SectorAddressing) {
2446 SdCmdBlk.CommandArgument = (UINT32)Lba;
2447 } else {
2448 SdCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);
2449 }
2450
2451 Status = SdPeimExecCmd (Slot, &Packet);
2452
2453 return Status;
2454 }
2455
2456 /**
2457 Send command SEND_TUNING_BLOCK to the SD device for SDR104/SDR50 optimal sampling point
2458 detection.
2459
2460 It may be sent up to 40 times until the host finishes the tuning procedure.
2461
2462 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2463
2464 @param[in] Slot The slot number of the SD card to send the command to.
2465
2466 @retval EFI_SUCCESS The operation is done correctly.
2467 @retval Others The operation fails.
2468
2469 **/
2470 EFI_STATUS
2471 SdPeimSendTuningBlk (
2472 IN SD_PEIM_HC_SLOT *Slot
2473 )
2474 {
2475 SD_COMMAND_BLOCK SdCmdBlk;
2476 SD_STATUS_BLOCK SdStatusBlk;
2477 SD_COMMAND_PACKET Packet;
2478 EFI_STATUS Status;
2479 UINT8 TuningBlock[64];
2480
2481 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2482 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2483 ZeroMem (&Packet, sizeof (Packet));
2484
2485 Packet.SdCmdBlk = &SdCmdBlk;
2486 Packet.SdStatusBlk = &SdStatusBlk;
2487 Packet.Timeout = SD_TIMEOUT;
2488
2489 SdCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
2490 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2491 SdCmdBlk.ResponseType = SdResponseTypeR1;
2492 SdCmdBlk.CommandArgument = 0;
2493
2494 Packet.InDataBuffer = TuningBlock;
2495 Packet.InTransferLength = sizeof (TuningBlock);
2496
2497 Status = SdPeimExecCmd (Slot, &Packet);
2498
2499 return Status;
2500 }
2501
2502 /**
2503 Tunning the sampling point of SDR104 or SDR50 bus speed mode.
2504
2505 Command SD_SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the
2506 tuning procedure.
2507
2508 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and SD Host Controller
2509 Simplified Spec 3.0 Figure 2-29 for details.
2510
2511 @param[in] Slot The slot number of the SD card to send the command to.
2512
2513 @retval EFI_SUCCESS The operation is done correctly.
2514 @retval Others The operation fails.
2515
2516 **/
2517 EFI_STATUS
2518 SdPeimTuningClock (
2519 IN SD_PEIM_HC_SLOT *Slot
2520 )
2521 {
2522 EFI_STATUS Status;
2523 UINT8 HostCtrl2;
2524 UINT8 Retry;
2525
2526 //
2527 // Notify the host that the sampling clock tuning procedure starts.
2528 //
2529 HostCtrl2 = BIT6;
2530 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2531 if (EFI_ERROR (Status)) {
2532 return Status;
2533 }
2534 //
2535 // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
2536 //
2537 Retry = 0;
2538 do {
2539 Status = SdPeimSendTuningBlk (Slot);
2540 if (EFI_ERROR (Status)) {
2541 return Status;
2542 }
2543
2544 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
2545 if (EFI_ERROR (Status)) {
2546 return Status;
2547 }
2548
2549 if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
2550 break;
2551 }
2552
2553 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
2554 return EFI_SUCCESS;
2555 }
2556 } while (++Retry < 40);
2557
2558 DEBUG ((EFI_D_ERROR, "SdPeimTuningClock: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));
2559 //
2560 // Abort the tuning procedure and reset the tuning circuit.
2561 //
2562 HostCtrl2 = (UINT8)~(BIT6 | BIT7);
2563 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2564 if (EFI_ERROR (Status)) {
2565 return Status;
2566 }
2567 return EFI_DEVICE_ERROR;
2568 }
2569
2570 /**
2571 Switch the bus width to specified width.
2572
2573 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
2574 SD Host Controller Simplified Spec 3.0 section Figure 3-7 for details.
2575
2576 @param[in] Slot The slot number of the SD card to send the command to.
2577 @param[in] Rca The relative device address to be assigned.
2578 @param[in] BusWidth The bus width to be set, it could be 4 or 8.
2579
2580 @retval EFI_SUCCESS The operation is done correctly.
2581 @retval Others The operation fails.
2582
2583 **/
2584 EFI_STATUS
2585 SdPeimSwitchBusWidth (
2586 IN SD_PEIM_HC_SLOT *Slot,
2587 IN UINT16 Rca,
2588 IN UINT8 BusWidth
2589 )
2590 {
2591 EFI_STATUS Status;
2592 UINT32 DevStatus;
2593
2594 Status = SdPeimSetBusWidth (Slot, Rca, BusWidth);
2595 if (EFI_ERROR (Status)) {
2596 return Status;
2597 }
2598
2599 Status = SdPeimSendStatus (Slot, Rca, &DevStatus);
2600 if (EFI_ERROR (Status)) {
2601 return Status;
2602 }
2603 //
2604 // Check the switch operation is really successful or not.
2605 //
2606 if ((DevStatus >> 16) != 0) {
2607 return EFI_DEVICE_ERROR;
2608 }
2609
2610 Status = SdPeimHcSetBusWidth (Slot->SdHcBase, BusWidth);
2611
2612 return Status;
2613 }
2614
2615 /**
2616 Switch the high speed timing according to request.
2617
2618 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
2619 SD Host Controller Simplified Spec 3.0 section Figure 2-29 for details.
2620
2621 @param[in] Slot The slot number of the SD card to send the command to.
2622 @param[in] Rca The relative device address to be assigned.
2623 @param[in] S18a The boolean to show if it's a UHS-I SD card.
2624
2625 @retval EFI_SUCCESS The operation is done correctly.
2626 @retval Others The operation fails.
2627
2628 **/
2629 EFI_STATUS
2630 SdPeimSetBusMode (
2631 IN SD_PEIM_HC_SLOT *Slot,
2632 IN UINT16 Rca,
2633 IN BOOLEAN S18a
2634 )
2635 {
2636 EFI_STATUS Status;
2637 SD_HC_SLOT_CAP Capability;
2638 UINT32 ClockFreq;
2639 UINT8 BusWidth;
2640 UINT8 AccessMode;
2641 UINT8 HostCtrl1;
2642 UINT8 HostCtrl2;
2643 UINT8 SwitchResp[64];
2644
2645 Status = SdPeimGetCsd (Slot, Rca, &Slot->Csd);
2646 if (EFI_ERROR (Status)) {
2647 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimGetCsd fails with %r\n", Status));
2648 return Status;
2649 }
2650
2651 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
2652 if (EFI_ERROR (Status)) {
2653 return Status;
2654 }
2655
2656 Status = SdPeimSelect (Slot, Rca);
2657 if (EFI_ERROR (Status)) {
2658 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSelect fails with %r\n", Status));
2659 return Status;
2660 }
2661
2662 BusWidth = 4;
2663 Status = SdPeimSwitchBusWidth (Slot, Rca, BusWidth);
2664 if (EFI_ERROR (Status)) {
2665 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitchBusWidth fails with %r\n", Status));
2666 return Status;
2667 }
2668
2669 //
2670 // Get the supported bus speed from SWITCH cmd return data group #1.
2671 //
2672 ZeroMem (SwitchResp, sizeof (SwitchResp));
2673 Status = SdPeimSwitch (Slot, 0xF, 0xF, 0xF, 0xF, FALSE, SwitchResp);
2674 if (EFI_ERROR (Status)) {
2675 return Status;
2676 }
2677 //
2678 // Calculate supported bus speed/bus width/clock frequency by host and device capability.
2679 //
2680 ClockFreq = 0;
2681 if (S18a && (Capability.Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
2682 ClockFreq = 208;
2683 AccessMode = 3;
2684 } else if (S18a && (Capability.Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
2685 ClockFreq = 100;
2686 AccessMode = 2;
2687 } else if (S18a && (Capability.Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
2688 ClockFreq = 50;
2689 AccessMode = 4;
2690 } else if ((SwitchResp[13] & BIT1) != 0) {
2691 ClockFreq = 50;
2692 AccessMode = 1;
2693 } else {
2694 ClockFreq = 25;
2695 AccessMode = 0;
2696 }
2697
2698 DEBUG ((EFI_D_INFO, "SdPeimSetBusMode: AccessMode %d ClockFreq %d BusWidth %d\n", AccessMode, ClockFreq, BusWidth));
2699
2700 Status = SdPeimSwitch (Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
2701 if (EFI_ERROR (Status)) {
2702 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitch fails with %r\n", Status));
2703 return Status;
2704 }
2705
2706 if ((SwitchResp[16] & 0xF) != AccessMode) {
2707 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitch to AccessMode %d ClockFreq %d BusWidth %d fails! The Switch response is 0x%1x\n", AccessMode, ClockFreq, BusWidth, SwitchResp[16] & 0xF));
2708 return EFI_DEVICE_ERROR;
2709 }
2710 //
2711 // Set to Hight Speed timing
2712 //
2713 if (AccessMode == 1) {
2714 HostCtrl1 = BIT2;
2715 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
2716 if (EFI_ERROR (Status)) {
2717 return Status;
2718 }
2719 }
2720
2721 HostCtrl2 = (UINT8)~0x7;
2722 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2723 if (EFI_ERROR (Status)) {
2724 return Status;
2725 }
2726 HostCtrl2 = AccessMode;
2727 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2728 if (EFI_ERROR (Status)) {
2729 return Status;
2730 }
2731
2732 Status = SdPeimHcClockSupply (Slot->SdHcBase, ClockFreq * 1000);
2733 if (EFI_ERROR (Status)) {
2734 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimHcClockSupply %r\n", Status));
2735 return Status;
2736 }
2737
2738 if ((AccessMode == 3) || ((AccessMode == 2) && (Capability.TuningSDR50 != 0))) {
2739 Status = SdPeimTuningClock (Slot);
2740 if (EFI_ERROR (Status)) {
2741 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimTuningClock fails with %r\n", Status));
2742 return Status;
2743 }
2744 }
2745
2746 DEBUG ((EFI_D_INFO, "SdPeimSetBusMode: SdPeimSetBusMode %r\n", Status));
2747
2748 return Status;
2749 }
2750
2751 /**
2752 Execute SD device identification procedure.
2753
2754 Refer to SD Physical Layer Simplified Spec 4.1 Section 3.6 for details.
2755
2756 @param[in] Slot The slot number of the SD card to send the command to.
2757
2758 @retval EFI_SUCCESS There is a SD card.
2759 @retval Others There is not a SD card.
2760
2761 **/
2762 EFI_STATUS
2763 SdPeimIdentification (
2764 IN SD_PEIM_HC_SLOT *Slot
2765 )
2766 {
2767 EFI_STATUS Status;
2768 UINT32 Ocr;
2769 UINT16 Rca;
2770 BOOLEAN Xpc;
2771 BOOLEAN S18r;
2772 UINT64 MaxCurrent;
2773 UINT64 Current;
2774 UINT16 ControllerVer;
2775 UINT8 PowerCtrl;
2776 UINT32 PresentState;
2777 UINT8 HostCtrl2;
2778 SD_HC_SLOT_CAP Capability;
2779 UINTN Retry;
2780 //
2781 // 1. Send Cmd0 to the device
2782 //
2783 Status = SdPeimReset (Slot);
2784 if (EFI_ERROR (Status)) {
2785 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing Cmd0 fails with %r\n", Status));
2786 return Status;
2787 }
2788 //
2789 // 2. Send Cmd8 to the device
2790 //
2791 Status = SdPeimVoltageCheck (Slot, 0x1, 0xFF);
2792 if (EFI_ERROR (Status)) {
2793 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing Cmd8 fails with %r\n", Status));
2794 return Status;
2795 }
2796 //
2797 // 3. Send SDIO Cmd5 to the device to the SDIO device OCR register.
2798 //
2799 Status = SdioSendOpCond (Slot, 0, FALSE);
2800 if (!EFI_ERROR (Status)) {
2801 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Found SDIO device, ignore it as we don't support\n"));
2802 return EFI_DEVICE_ERROR;
2803 }
2804 //
2805 // 4. Send Acmd41 with voltage window 0 to the device
2806 //
2807 Status = SdPeimSendOpCond (Slot, 0, 0, FALSE, FALSE, FALSE, &Ocr);
2808 if (EFI_ERROR (Status)) {
2809 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimSendOpCond fails with %r\n", Status));
2810 return EFI_DEVICE_ERROR;
2811 }
2812
2813 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
2814 if (EFI_ERROR (Status)) {
2815 return Status;
2816 }
2817
2818 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_MAX_CURRENT_CAP, TRUE, sizeof (Current), &Current);
2819 if (EFI_ERROR (Status)) {
2820 return Status;
2821 }
2822
2823 if (Capability.Voltage33 != 0) {
2824 //
2825 // Support 3.3V
2826 //
2827 MaxCurrent = ((UINT32)Current & 0xFF) * 4;
2828 } else if (Capability.Voltage30 != 0) {
2829 //
2830 // Support 3.0V
2831 //
2832 MaxCurrent = (((UINT32)Current >> 8) & 0xFF) * 4;
2833 } else if (Capability.Voltage18 != 0) {
2834 //
2835 // Support 1.8V
2836 //
2837 MaxCurrent = (((UINT32)Current >> 16) & 0xFF) * 4;
2838 } else {
2839 ASSERT (FALSE);
2840 return EFI_DEVICE_ERROR;
2841 }
2842
2843 if (MaxCurrent >= 150) {
2844 Xpc = TRUE;
2845 } else {
2846 Xpc = FALSE;
2847 }
2848
2849 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
2850 if (EFI_ERROR (Status)) {
2851 return Status;
2852 }
2853
2854 if ((ControllerVer & 0xFF) == 2) {
2855 S18r = TRUE;
2856 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
2857 S18r = FALSE;
2858 } else {
2859 ASSERT (FALSE);
2860 return EFI_UNSUPPORTED;
2861 }
2862 //
2863 // 5. Repeatly send Acmd41 with supply voltage window to the device.
2864 // Note here we only support the cards complied with SD physical
2865 // layer simplified spec version 2.0 and version 3.0 and above.
2866 //
2867 Ocr = 0;
2868 Retry = 0;
2869 do {
2870 Status = SdPeimSendOpCond (Slot, 0, Ocr, S18r, Xpc, TRUE, &Ocr);
2871 if (EFI_ERROR (Status)) {
2872 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SdPeimSendOpCond fails with %r Ocr %x, S18r %x, Xpc %x\n", Status, Ocr, S18r, Xpc));
2873 return EFI_DEVICE_ERROR;
2874 }
2875
2876 if (Retry++ == 100) {
2877 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SdPeimSendOpCond fails too many times\n"));
2878 return EFI_DEVICE_ERROR;
2879 }
2880 MicroSecondDelay (10 * 1000);
2881 } while ((Ocr & BIT31) == 0);
2882
2883 //
2884 // 6. If the S18a bit is set and the Host Controller supports 1.8V signaling
2885 // (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the
2886 // Capabilities register), switch its voltage to 1.8V.
2887 //
2888 if ((Capability.Sdr50 != 0 ||
2889 Capability.Sdr104 != 0 ||
2890 Capability.Ddr50 != 0) &&
2891 ((Ocr & BIT24) != 0)) {
2892 Status = SdPeimVoltageSwitch (Slot);
2893 if (EFI_ERROR (Status)) {
2894 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimVoltageSwitch fails with %r\n", Status));
2895 Status = EFI_DEVICE_ERROR;
2896 goto Error;
2897 } else {
2898 Status = SdPeimHcStopClock (Slot->SdHcBase);
2899 if (EFI_ERROR (Status)) {
2900 Status = EFI_DEVICE_ERROR;
2901 goto Error;
2902 }
2903
2904 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
2905 if (((PresentState >> 20) & 0xF) != 0) {
2906 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with PresentState = 0x%x\n", PresentState));
2907 Status = EFI_DEVICE_ERROR;
2908 goto Error;
2909 }
2910 HostCtrl2 = BIT3;
2911 SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2912
2913 MicroSecondDelay (5000);
2914
2915 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
2916 if ((HostCtrl2 & BIT3) == 0) {
2917 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with HostCtrl2 = 0x%x\n", HostCtrl2));
2918 Status = EFI_DEVICE_ERROR;
2919 goto Error;
2920 }
2921
2922 SdPeimHcInitClockFreq (Slot->SdHcBase);
2923
2924 MicroSecondDelay (1000);
2925
2926 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
2927 if (((PresentState >> 20) & 0xF) != 0xF) {
2928 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with PresentState = 0x%x, It should be 0xF\n", PresentState));
2929 Status = EFI_DEVICE_ERROR;
2930 goto Error;
2931 }
2932 }
2933 DEBUG ((EFI_D_INFO, "SdPeimIdentification: Switch to 1.8v signal voltage success\n"));
2934 }
2935
2936 Status = SdPeimAllSendCid (Slot);
2937 if (EFI_ERROR (Status)) {
2938 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimAllSendCid fails with %r\n", Status));
2939 return Status;
2940 }
2941
2942 Status = SdPeimSetRca (Slot, &Rca);
2943 if (EFI_ERROR (Status)) {
2944 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimSetRca fails with %r\n", Status));
2945 return Status;
2946 }
2947 //
2948 // Enter Data Tranfer Mode.
2949 //
2950 DEBUG ((EFI_D_INFO, "Found a SD device at slot [%d]\n", Slot));
2951
2952 Status = SdPeimSetBusMode (Slot, Rca, ((Ocr & BIT24) != 0));
2953
2954 return Status;
2955
2956 Error:
2957 //
2958 // Set SD Bus Power = 0
2959 //
2960 PowerCtrl = (UINT8)~BIT0;
2961 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);
2962 return EFI_DEVICE_ERROR;
2963 }
EFI Development Kit II mirror for PVE