2 x64 Virtual Memory Management Services in the form of an IA-32 driver.
3 Used to establish a 1:1 Virtual to Physical Mapping that is required to
4 enter Long Mode (x64 64-bit mode).
6 While we make a 1:1 mapping (identity mapping) for all physical pages
7 we still need to use the MTRR's to ensure that the cachability attributes
8 for all memory regions is correct.
10 The basic idea is to use 2MB page table entries where ever possible. If
11 more granularity of cachability is required then 4K page tables are used.
14 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
15 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
16 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
18 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
19 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
21 SPDX-License-Identifier: BSD-2-Clause-Patent
26 #include "VirtualMemory.h"
29 // Global variable to keep track current available memory used as page table.
31 PAGE_TABLE_POOL
*mPageTablePool
= NULL
;
34 Clear legacy memory located at the first 4K-page, if available.
36 This function traverses the whole HOB list to check if memory from 0 to 4095
37 exists and has not been allocated, and then clear it if so.
39 @param HobStart The start of HobList passed to DxeCore.
47 EFI_PEI_HOB_POINTERS RscHob
;
48 EFI_PEI_HOB_POINTERS MemHob
;
51 RscHob
.Raw
= HobStart
;
52 MemHob
.Raw
= HobStart
;
56 // Check if page 0 exists and free
58 while ((RscHob
.Raw
= GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR
,
59 RscHob
.Raw
)) != NULL
) {
60 if (RscHob
.ResourceDescriptor
->ResourceType
== EFI_RESOURCE_SYSTEM_MEMORY
&&
61 RscHob
.ResourceDescriptor
->PhysicalStart
== 0) {
64 // Make sure memory at 0-4095 has not been allocated.
66 while ((MemHob
.Raw
= GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION
,
67 MemHob
.Raw
)) != NULL
) {
68 if (MemHob
.MemoryAllocation
->AllocDescriptor
.MemoryBaseAddress
73 MemHob
.Raw
= GET_NEXT_HOB (MemHob
);
77 RscHob
.Raw
= GET_NEXT_HOB (RscHob
);
81 DEBUG ((DEBUG_INFO
, "Clearing first 4K-page!\r\n"));
82 SetMem (NULL
, EFI_PAGE_SIZE
, 0);
89 Return configure status of NULL pointer detection feature.
91 @return TRUE NULL pointer detection feature is enabled
92 @return FALSE NULL pointer detection feature is disabled
96 IsNullDetectionEnabled (
100 return ((PcdGet8 (PcdNullPointerDetectionPropertyMask
) & BIT0
) != 0);
104 The function will check if Execute Disable Bit is available.
106 @retval TRUE Execute Disable Bit is available.
107 @retval FALSE Execute Disable Bit is not available.
111 IsExecuteDisableBitAvailable (
120 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
121 if (RegEax
>= 0x80000001) {
122 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
123 if ((RegEdx
& BIT20
) != 0) {
125 // Bit 20: Execute Disable Bit available.
135 Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.
137 @retval TRUE IA32_EFER.NXE should be enabled.
138 @retval FALSE IA32_EFER.NXE should not be enabled.
142 IsEnableNonExecNeeded (
146 if (!IsExecuteDisableBitAvailable ()) {
151 // XD flag (BIT63) in page table entry is only valid if IA32_EFER.NXE is set.
152 // Features controlled by Following PCDs need this feature to be enabled.
154 return (PcdGetBool (PcdSetNxForStack
) ||
155 PcdGet64 (PcdDxeNxMemoryProtectionPolicy
) != 0 ||
156 PcdGet32 (PcdImageProtectionPolicy
) != 0);
160 Enable Execute Disable Bit.
164 EnableExecuteDisableBit (
170 MsrRegisters
= AsmReadMsr64 (0xC0000080);
171 MsrRegisters
|= BIT11
;
172 AsmWriteMsr64 (0xC0000080, MsrRegisters
);
176 The function will check if page table entry should be splitted to smaller
179 @param Address Physical memory address.
180 @param Size Size of the given physical memory.
181 @param StackBase Base address of stack.
182 @param StackSize Size of stack.
184 @retval TRUE Page table should be split.
185 @retval FALSE Page table should not be split.
189 IN EFI_PHYSICAL_ADDRESS Address
,
191 IN EFI_PHYSICAL_ADDRESS StackBase
,
195 if (IsNullDetectionEnabled () && Address
== 0) {
199 if (PcdGetBool (PcdCpuStackGuard
)) {
200 if (StackBase
>= Address
&& StackBase
< (Address
+ Size
)) {
205 if (PcdGetBool (PcdSetNxForStack
)) {
206 if ((Address
< StackBase
+ StackSize
) && ((Address
+ Size
) > StackBase
)) {
214 Initialize a buffer pool for page table use only.
216 To reduce the potential split operation on page table, the pages reserved for
217 page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and
218 at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always
219 initialized with number of pages greater than or equal to the given PoolPages.
221 Once the pages in the pool are used up, this method should be called again to
222 reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. But usually this won't
225 @param PoolPages The least page number of the pool to be created.
227 @retval TRUE The pool is initialized successfully.
228 @retval FALSE The memory is out of resource.
231 InitializePageTablePool (
238 // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
241 PoolPages
+= 1; // Add one page for header.
242 PoolPages
= ((PoolPages
- 1) / PAGE_TABLE_POOL_UNIT_PAGES
+ 1) *
243 PAGE_TABLE_POOL_UNIT_PAGES
;
244 Buffer
= AllocateAlignedPages (PoolPages
, PAGE_TABLE_POOL_ALIGNMENT
);
245 if (Buffer
== NULL
) {
246 DEBUG ((DEBUG_ERROR
, "ERROR: Out of aligned pages\r\n"));
251 // Link all pools into a list for easier track later.
253 if (mPageTablePool
== NULL
) {
254 mPageTablePool
= Buffer
;
255 mPageTablePool
->NextPool
= mPageTablePool
;
257 ((PAGE_TABLE_POOL
*)Buffer
)->NextPool
= mPageTablePool
->NextPool
;
258 mPageTablePool
->NextPool
= Buffer
;
259 mPageTablePool
= Buffer
;
263 // Reserve one page for pool header.
265 mPageTablePool
->FreePages
= PoolPages
- 1;
266 mPageTablePool
->Offset
= EFI_PAGES_TO_SIZE (1);
272 This API provides a way to allocate memory for page table.
274 This API can be called more than once to allocate memory for page tables.
276 Allocates the number of 4KB pages and returns a pointer to the allocated
277 buffer. The buffer returned is aligned on a 4KB boundary.
279 If Pages is 0, then NULL is returned.
280 If there is not enough memory remaining to satisfy the request, then NULL is
283 @param Pages The number of 4 KB pages to allocate.
285 @return A pointer to the allocated buffer or NULL if allocation fails.
289 AllocatePageTableMemory (
300 // Renew the pool if necessary.
302 if (mPageTablePool
== NULL
||
303 Pages
> mPageTablePool
->FreePages
) {
304 if (!InitializePageTablePool (Pages
)) {
309 Buffer
= (UINT8
*)mPageTablePool
+ mPageTablePool
->Offset
;
311 mPageTablePool
->Offset
+= EFI_PAGES_TO_SIZE (Pages
);
312 mPageTablePool
->FreePages
-= Pages
;
320 @param[in] PhysicalAddress Start physical address the 2M page covered.
321 @param[in, out] PageEntry2M Pointer to 2M page entry.
322 @param[in] StackBase Stack base address.
323 @param[in] StackSize Stack size.
328 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
329 IN OUT UINT64
*PageEntry2M
,
330 IN EFI_PHYSICAL_ADDRESS StackBase
,
334 EFI_PHYSICAL_ADDRESS PhysicalAddress4K
;
335 UINTN IndexOfPageTableEntries
;
336 PAGE_TABLE_4K_ENTRY
*PageTableEntry
;
337 UINT64 AddressEncMask
;
340 // Make sure AddressEncMask is contained to smallest supported address field
342 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
344 PageTableEntry
= AllocatePageTableMemory (1);
345 ASSERT (PageTableEntry
!= NULL
);
348 // Fill in 2M page entry.
350 *PageEntry2M
= (UINT64
) (UINTN
) PageTableEntry
| AddressEncMask
| IA32_PG_P
| IA32_PG_RW
;
352 PhysicalAddress4K
= PhysicalAddress
;
353 for (IndexOfPageTableEntries
= 0; IndexOfPageTableEntries
< 512; IndexOfPageTableEntries
++, PageTableEntry
++, PhysicalAddress4K
+= SIZE_4KB
) {
355 // Fill in the Page Table entries
357 PageTableEntry
->Uint64
= (UINT64
) PhysicalAddress4K
| AddressEncMask
;
358 PageTableEntry
->Bits
.ReadWrite
= 1;
360 if ((IsNullDetectionEnabled () && PhysicalAddress4K
== 0) ||
361 (PcdGetBool (PcdCpuStackGuard
) && PhysicalAddress4K
== StackBase
)) {
362 PageTableEntry
->Bits
.Present
= 0;
364 PageTableEntry
->Bits
.Present
= 1;
367 if (PcdGetBool (PcdSetNxForStack
)
368 && (PhysicalAddress4K
>= StackBase
)
369 && (PhysicalAddress4K
< StackBase
+ StackSize
)) {
371 // Set Nx bit for stack.
373 PageTableEntry
->Bits
.Nx
= 1;
381 @param[in] PhysicalAddress Start physical address the 1G page covered.
382 @param[in, out] PageEntry1G Pointer to 1G page entry.
383 @param[in] StackBase Stack base address.
384 @param[in] StackSize Stack size.
389 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
390 IN OUT UINT64
*PageEntry1G
,
391 IN EFI_PHYSICAL_ADDRESS StackBase
,
395 EFI_PHYSICAL_ADDRESS PhysicalAddress2M
;
396 UINTN IndexOfPageDirectoryEntries
;
397 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
398 UINT64 AddressEncMask
;
401 // Make sure AddressEncMask is contained to smallest supported address field
403 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
405 PageDirectoryEntry
= AllocatePageTableMemory (1);
406 ASSERT (PageDirectoryEntry
!= NULL
);
409 // Fill in 1G page entry.
411 *PageEntry1G
= (UINT64
) (UINTN
) PageDirectoryEntry
| AddressEncMask
| IA32_PG_P
| IA32_PG_RW
;
413 PhysicalAddress2M
= PhysicalAddress
;
414 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PhysicalAddress2M
+= SIZE_2MB
) {
415 if (ToSplitPageTable (PhysicalAddress2M
, SIZE_2MB
, StackBase
, StackSize
)) {
417 // Need to split this 2M page that covers NULL or stack range.
419 Split2MPageTo4K (PhysicalAddress2M
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
422 // Fill in the Page Directory entries
424 PageDirectoryEntry
->Uint64
= (UINT64
) PhysicalAddress2M
| AddressEncMask
;
425 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
426 PageDirectoryEntry
->Bits
.Present
= 1;
427 PageDirectoryEntry
->Bits
.MustBe1
= 1;
433 Set one page of page table pool memory to be read-only.
435 @param[in] PageTableBase Base address of page table (CR3).
436 @param[in] Address Start address of a page to be set as read-only.
437 @param[in] Level4Paging Level 4 paging flag.
441 SetPageTablePoolReadOnly (
442 IN UINTN PageTableBase
,
443 IN EFI_PHYSICAL_ADDRESS Address
,
444 IN BOOLEAN Level4Paging
449 UINT64 AddressEncMask
;
450 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
452 UINT64
*NewPageTable
;
460 ASSERT (PageTableBase
!= 0);
463 // Since the page table is always from page table pool, which is always
464 // located at the boundary of PcdPageTablePoolAlignment, we just need to
465 // set the whole pool unit to be read-only.
467 Address
= Address
& PAGE_TABLE_POOL_ALIGN_MASK
;
469 LevelShift
[1] = PAGING_L1_ADDRESS_SHIFT
;
470 LevelShift
[2] = PAGING_L2_ADDRESS_SHIFT
;
471 LevelShift
[3] = PAGING_L3_ADDRESS_SHIFT
;
472 LevelShift
[4] = PAGING_L4_ADDRESS_SHIFT
;
474 LevelMask
[1] = PAGING_4K_ADDRESS_MASK_64
;
475 LevelMask
[2] = PAGING_2M_ADDRESS_MASK_64
;
476 LevelMask
[3] = PAGING_1G_ADDRESS_MASK_64
;
477 LevelMask
[4] = PAGING_1G_ADDRESS_MASK_64
;
479 LevelSize
[1] = SIZE_4KB
;
480 LevelSize
[2] = SIZE_2MB
;
481 LevelSize
[3] = SIZE_1GB
;
482 LevelSize
[4] = SIZE_512GB
;
484 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) &
485 PAGING_1G_ADDRESS_MASK_64
;
486 PageTable
= (UINT64
*)(UINTN
)PageTableBase
;
487 PoolUnitSize
= PAGE_TABLE_POOL_UNIT_SIZE
;
489 for (Level
= (Level4Paging
) ? 4 : 3; Level
> 0; --Level
) {
490 Index
= ((UINTN
)RShiftU64 (Address
, LevelShift
[Level
]));
491 Index
&= PAGING_PAE_INDEX_MASK
;
493 PageAttr
= PageTable
[Index
];
494 if ((PageAttr
& IA32_PG_PS
) == 0) {
496 // Go to next level of table.
498 PageTable
= (UINT64
*)(UINTN
)(PageAttr
& ~AddressEncMask
&
499 PAGING_4K_ADDRESS_MASK_64
);
503 if (PoolUnitSize
>= LevelSize
[Level
]) {
505 // Clear R/W bit if current page granularity is not larger than pool unit
508 if ((PageAttr
& IA32_PG_RW
) != 0) {
509 while (PoolUnitSize
> 0) {
511 // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are fit in
512 // one page (2MB). Then we don't need to update attributes for pages
513 // crossing page directory. ASSERT below is for that purpose.
515 ASSERT (Index
< EFI_PAGE_SIZE
/sizeof (UINT64
));
517 PageTable
[Index
] &= ~(UINT64
)IA32_PG_RW
;
518 PoolUnitSize
-= LevelSize
[Level
];
528 // The smaller granularity of page must be needed.
532 NewPageTable
= AllocatePageTableMemory (1);
533 ASSERT (NewPageTable
!= NULL
);
535 PhysicalAddress
= PageAttr
& LevelMask
[Level
];
537 EntryIndex
< EFI_PAGE_SIZE
/sizeof (UINT64
);
539 NewPageTable
[EntryIndex
] = PhysicalAddress
| AddressEncMask
|
540 IA32_PG_P
| IA32_PG_RW
;
542 NewPageTable
[EntryIndex
] |= IA32_PG_PS
;
544 PhysicalAddress
+= LevelSize
[Level
- 1];
547 PageTable
[Index
] = (UINT64
)(UINTN
)NewPageTable
| AddressEncMask
|
548 IA32_PG_P
| IA32_PG_RW
;
549 PageTable
= NewPageTable
;
555 Prevent the memory pages used for page table from been overwritten.
557 @param[in] PageTableBase Base address of page table (CR3).
558 @param[in] Level4Paging Level 4 paging flag.
562 EnablePageTableProtection (
563 IN UINTN PageTableBase
,
564 IN BOOLEAN Level4Paging
567 PAGE_TABLE_POOL
*HeadPool
;
568 PAGE_TABLE_POOL
*Pool
;
570 EFI_PHYSICAL_ADDRESS Address
;
572 if (mPageTablePool
== NULL
) {
577 // Disable write protection, because we need to mark page table to be write
580 AsmWriteCr0 (AsmReadCr0() & ~CR0_WP
);
583 // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
584 // remember original one in advance.
586 HeadPool
= mPageTablePool
;
589 Address
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)Pool
;
590 PoolSize
= Pool
->Offset
+ EFI_PAGES_TO_SIZE (Pool
->FreePages
);
593 // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, which
594 // is one of page size of the processor (2MB by default). Let's apply the
595 // protection to them one by one.
597 while (PoolSize
> 0) {
598 SetPageTablePoolReadOnly(PageTableBase
, Address
, Level4Paging
);
599 Address
+= PAGE_TABLE_POOL_UNIT_SIZE
;
600 PoolSize
-= PAGE_TABLE_POOL_UNIT_SIZE
;
603 Pool
= Pool
->NextPool
;
604 } while (Pool
!= HeadPool
);
607 // Enable write protection, after page table attribute updated.
609 AsmWriteCr0 (AsmReadCr0() | CR0_WP
);
613 Allocates and fills in the Page Directory and Page Table Entries to
614 establish a 1:1 Virtual to Physical mapping.
616 @param[in] StackBase Stack base address.
617 @param[in] StackSize Stack size.
619 @return The address of 4 level page map.
623 CreateIdentityMappingPageTables (
624 IN EFI_PHYSICAL_ADDRESS StackBase
,
630 UINT8 PhysicalAddressBits
;
631 EFI_PHYSICAL_ADDRESS PageAddress
;
632 UINTN IndexOfPml4Entries
;
633 UINTN IndexOfPdpEntries
;
634 UINTN IndexOfPageDirectoryEntries
;
635 UINT32 NumberOfPml4EntriesNeeded
;
636 UINT32 NumberOfPdpEntriesNeeded
;
637 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMapLevel4Entry
;
638 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMap
;
639 PAGE_MAP_AND_DIRECTORY_POINTER
*PageDirectoryPointerEntry
;
640 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
642 UINTN BigPageAddress
;
644 BOOLEAN Page1GSupport
;
645 PAGE_TABLE_1G_ENTRY
*PageDirectory1GEntry
;
646 UINT64 AddressEncMask
;
649 // Make sure AddressEncMask is contained to smallest supported address field
651 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
653 Page1GSupport
= FALSE
;
654 if (PcdGetBool(PcdUse1GPageTable
)) {
655 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
656 if (RegEax
>= 0x80000001) {
657 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
658 if ((RegEdx
& BIT26
) != 0) {
659 Page1GSupport
= TRUE
;
665 // Get physical address bits supported.
667 Hob
= GetFirstHob (EFI_HOB_TYPE_CPU
);
669 PhysicalAddressBits
= ((EFI_HOB_CPU
*) Hob
)->SizeOfMemorySpace
;
671 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
672 if (RegEax
>= 0x80000008) {
673 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
674 PhysicalAddressBits
= (UINT8
) RegEax
;
676 PhysicalAddressBits
= 36;
681 // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
683 ASSERT (PhysicalAddressBits
<= 52);
684 if (PhysicalAddressBits
> 48) {
685 PhysicalAddressBits
= 48;
689 // Calculate the table entries needed.
691 if (PhysicalAddressBits
<= 39 ) {
692 NumberOfPml4EntriesNeeded
= 1;
693 NumberOfPdpEntriesNeeded
= (UINT32
)LShiftU64 (1, (PhysicalAddressBits
- 30));
695 NumberOfPml4EntriesNeeded
= (UINT32
)LShiftU64 (1, (PhysicalAddressBits
- 39));
696 NumberOfPdpEntriesNeeded
= 512;
700 // Pre-allocate big pages to avoid later allocations.
702 if (!Page1GSupport
) {
703 TotalPagesNum
= (NumberOfPdpEntriesNeeded
+ 1) * NumberOfPml4EntriesNeeded
+ 1;
705 TotalPagesNum
= NumberOfPml4EntriesNeeded
+ 1;
707 BigPageAddress
= (UINTN
) AllocatePageTableMemory (TotalPagesNum
);
708 ASSERT (BigPageAddress
!= 0);
711 // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
713 PageMap
= (VOID
*) BigPageAddress
;
714 BigPageAddress
+= SIZE_4KB
;
716 PageMapLevel4Entry
= PageMap
;
718 for (IndexOfPml4Entries
= 0; IndexOfPml4Entries
< NumberOfPml4EntriesNeeded
; IndexOfPml4Entries
++, PageMapLevel4Entry
++) {
720 // Each PML4 entry points to a page of Page Directory Pointer entires.
721 // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
723 PageDirectoryPointerEntry
= (VOID
*) BigPageAddress
;
724 BigPageAddress
+= SIZE_4KB
;
729 PageMapLevel4Entry
->Uint64
= (UINT64
)(UINTN
)PageDirectoryPointerEntry
| AddressEncMask
;
730 PageMapLevel4Entry
->Bits
.ReadWrite
= 1;
731 PageMapLevel4Entry
->Bits
.Present
= 1;
734 PageDirectory1GEntry
= (VOID
*) PageDirectoryPointerEntry
;
736 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectory1GEntry
++, PageAddress
+= SIZE_1GB
) {
737 if (ToSplitPageTable (PageAddress
, SIZE_1GB
, StackBase
, StackSize
)) {
738 Split1GPageTo2M (PageAddress
, (UINT64
*) PageDirectory1GEntry
, StackBase
, StackSize
);
741 // Fill in the Page Directory entries
743 PageDirectory1GEntry
->Uint64
= (UINT64
)PageAddress
| AddressEncMask
;
744 PageDirectory1GEntry
->Bits
.ReadWrite
= 1;
745 PageDirectory1GEntry
->Bits
.Present
= 1;
746 PageDirectory1GEntry
->Bits
.MustBe1
= 1;
750 for (IndexOfPdpEntries
= 0; IndexOfPdpEntries
< NumberOfPdpEntriesNeeded
; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
752 // Each Directory Pointer entries points to a page of Page Directory entires.
753 // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
755 PageDirectoryEntry
= (VOID
*) BigPageAddress
;
756 BigPageAddress
+= SIZE_4KB
;
759 // Fill in a Page Directory Pointer Entries
761 PageDirectoryPointerEntry
->Uint64
= (UINT64
)(UINTN
)PageDirectoryEntry
| AddressEncMask
;
762 PageDirectoryPointerEntry
->Bits
.ReadWrite
= 1;
763 PageDirectoryPointerEntry
->Bits
.Present
= 1;
765 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PageAddress
+= SIZE_2MB
) {
766 if (ToSplitPageTable (PageAddress
, SIZE_2MB
, StackBase
, StackSize
)) {
768 // Need to split this 2M page that covers NULL or stack range.
770 Split2MPageTo4K (PageAddress
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
773 // Fill in the Page Directory entries
775 PageDirectoryEntry
->Uint64
= (UINT64
)PageAddress
| AddressEncMask
;
776 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
777 PageDirectoryEntry
->Bits
.Present
= 1;
778 PageDirectoryEntry
->Bits
.MustBe1
= 1;
783 for (; IndexOfPdpEntries
< 512; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
785 PageDirectoryPointerEntry
,
786 sizeof(PAGE_MAP_AND_DIRECTORY_POINTER
)
793 // For the PML4 entries we are not using fill in a null entry.
795 for (; IndexOfPml4Entries
< 512; IndexOfPml4Entries
++, PageMapLevel4Entry
++) {
798 sizeof (PAGE_MAP_AND_DIRECTORY_POINTER
)
803 // Protect the page table by marking the memory used for page table to be
806 EnablePageTableProtection ((UINTN
)PageMap
, TRUE
);
809 // Set IA32_EFER.NXE if necessary.
811 if (IsEnableNonExecNeeded ()) {
812 EnableExecuteDisableBit ();
815 return (UINTN
)PageMap
;