2 16550 UART Serial Port library functions
4 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
5 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <IndustryStandard/Pci.h>
18 #include <Library/SerialPortLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/IoLib.h>
21 #include <Library/PciLib.h>
22 #include <Library/PlatformHookLib.h>
23 #include <Library/BaseLib.h>
28 #define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
31 // 16550 UART register offsets and bitfields
33 #define R_UART_RXBUF 0
34 #define R_UART_TXBUF 0
35 #define R_UART_BAUD_LOW 0
36 #define R_UART_BAUD_HIGH 1
38 #define B_UART_FCR_FIFOE BIT0
39 #define B_UART_FCR_FIFO64 BIT5
41 #define B_UART_LCR_DLAB BIT7
43 #define B_UART_MCR_RTS BIT1
45 #define B_UART_LSR_RXRDY BIT0
46 #define B_UART_LSR_TXRDY BIT5
47 #define B_UART_LSR_TEMT BIT6
49 #define B_UART_MSR_CTS BIT4
50 #define B_UART_MSR_DSR BIT5
53 // 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
58 UINT16 PowerManagementStatusAndControlRegister
;
59 } PCI_UART_DEVICE_INFO
;
62 Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
63 MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
64 parameter Offset is added to the base address of the 16550 registers that is specified
65 by PcdSerialRegisterBase.
67 @param Base The base address register of UART device.
68 @param Offset The offset of the 16550 register to read.
70 @return The value read from the 16550 register.
74 SerialPortReadRegister (
79 if (PcdGetBool (PcdSerialUseMmio
)) {
80 return MmioRead8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
));
82 return IoRead8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
));
87 Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
88 MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
89 parameter Offset is added to the base address of the 16550 registers that is specified
90 by PcdSerialRegisterBase.
92 @param Base The base address register of UART device.
93 @param Offset The offset of the 16550 register to write.
94 @param Value The value to write to the 16550 register specified by Offset.
96 @return The value written to the 16550 register.
100 SerialPortWriteRegister (
106 if (PcdGetBool (PcdSerialUseMmio
)) {
107 return MmioWrite8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
), Value
);
109 return IoWrite8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
), Value
);
114 Update the value of an 16-bit PCI configuration register in a PCI device. If the
115 PCI Configuration register specified by PciAddress is already programmed with a
116 non-zero value, then return the current value. Otherwise update the PCI configuration
117 register specified by PciAddress with the value specified by Value and return the
118 value programmed into the PCI configuration register. All values must be masked
119 using the bitmask specified by Mask.
121 @param PciAddress PCI Library address of the PCI Configuration register to update.
122 @param Value The value to program into the PCI Configuration Register.
123 @param Mask Bitmask of the bits to check and update in the PCI configuration register.
127 SerialPortLibUpdatePciRegister16 (
135 CurrentValue
= PciRead16 (PciAddress
) & Mask
;
136 if (CurrentValue
!= 0) {
139 return PciWrite16 (PciAddress
, Value
& Mask
);
143 Update the value of an 32-bit PCI configuration register in a PCI device. If the
144 PCI Configuration register specified by PciAddress is already programmed with a
145 non-zero value, then return the current value. Otherwise update the PCI configuration
146 register specified by PciAddress with the value specified by Value and return the
147 value programmed into the PCI configuration register. All values must be masked
148 using the bitmask specified by Mask.
150 @param PciAddress PCI Library address of the PCI Configuration register to update.
151 @param Value The value to program into the PCI Configuration Register.
152 @param Mask Bitmask of the bits to check and update in the PCI configuration register.
154 @return The Secondary bus number that is actually programed into the PCI to PCI Bridge device.
158 SerialPortLibUpdatePciRegister32 (
166 CurrentValue
= PciRead32 (PciAddress
) & Mask
;
167 if (CurrentValue
!= 0) {
170 return PciWrite32 (PciAddress
, Value
& Mask
);
174 Retrieve the I/O or MMIO base address register for the PCI UART device.
176 This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
177 Device if they are not already enabled.
179 @return The base address register of the UART device.
183 GetSerialRegisterBase (
189 UINTN SubordinateBusNumber
;
191 UINT32 ParentIoLimit
;
192 UINT16 ParentMemoryBase
;
193 UINT16 ParentMemoryLimit
;
198 UINTN SerialRegisterBase
;
200 UINT32 RegisterBaseMask
;
201 PCI_UART_DEVICE_INFO
*DeviceInfo
;
204 // Get PCI Device Info
206 DeviceInfo
= (PCI_UART_DEVICE_INFO
*) PcdGetPtr (PcdSerialPciDeviceInfo
);
209 // If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase
211 if (DeviceInfo
->Device
== 0xff) {
212 return (UINTN
)PcdGet64 (PcdSerialRegisterBase
);
216 // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB
218 ParentMemoryBase
= 0 >> 16;
219 ParentMemoryLimit
= 0xfff00000 >> 16;
220 ParentIoBase
= 0 >> 12;
221 ParentIoLimit
= 0xf000 >> 12;
224 // Enable I/O and MMIO in PCI Bridge
225 // Assume Root Bus Numer is Zero.
227 for (BusNumber
= 0; (DeviceInfo
+ 1)->Device
!= 0xff; DeviceInfo
++) {
229 // Compute PCI Lib Address to PCI to PCI Bridge
231 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
234 // Retrieve and verify the bus numbers in the PCI to PCI Bridge
236 BusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
);
237 SubordinateBusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET
);
238 if (BusNumber
== 0 || BusNumber
> SubordinateBusNumber
) {
243 // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
245 if (PcdGetBool (PcdSerialUseMmio
)) {
246 MemoryLimit
= PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.MemoryLimit
)) & 0xfff0;
247 MemoryBase
= PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.MemoryBase
)) & 0xfff0;
250 // If PCI Bridge MMIO window is disabled, then return 0
252 if (MemoryLimit
< MemoryBase
) {
257 // If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0
259 if (MemoryBase
< ParentMemoryBase
|| MemoryBase
> ParentMemoryLimit
|| MemoryLimit
> ParentMemoryLimit
) {
262 ParentMemoryBase
= MemoryBase
;
263 ParentMemoryLimit
= MemoryLimit
;
265 IoLimit
= PciRead8 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoLimit
));
266 if ((IoLimit
& PCI_BRIDGE_32_BIT_IO_SPACE
) == 0) {
267 IoLimit
= IoLimit
>> 4;
269 IoLimit
= (PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoLimitUpper16
)) << 4) | (IoLimit
>> 4);
271 IoBase
= PciRead8 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoBase
));
272 if ((IoBase
& PCI_BRIDGE_32_BIT_IO_SPACE
) == 0) {
273 IoBase
= IoBase
>> 4;
275 IoBase
= (PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoBaseUpper16
)) << 4) | (IoBase
>> 4);
279 // If PCI Bridge I/O window is disabled, then return 0
281 if (IoLimit
< IoBase
) {
286 // If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0
288 if (IoBase
< ParentIoBase
|| IoBase
> ParentIoLimit
|| IoLimit
> ParentIoLimit
) {
291 ParentIoBase
= IoBase
;
292 ParentIoLimit
= IoLimit
;
297 // Compute PCI Lib Address to PCI UART
299 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
302 // Find the first IO or MMIO BAR
304 RegisterBaseMask
= 0xFFFFFFF0;
305 for (BarIndex
= 0; BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
306 SerialRegisterBase
= PciRead32 (PciLibAddress
+ PCI_BASE_ADDRESSREG_OFFSET
+ BarIndex
* 4);
307 if (PcdGetBool (PcdSerialUseMmio
) && ((SerialRegisterBase
& BIT0
) == 0)) {
311 RegisterBaseMask
= 0xFFFFFFF0;
315 if ((!PcdGetBool (PcdSerialUseMmio
)) && ((SerialRegisterBase
& BIT0
) != 0)) {
319 RegisterBaseMask
= 0xFFFFFFF8;
325 // MMIO or IO BAR is not found.
327 if (BarIndex
== PCI_MAX_BAR
) {
334 SerialRegisterBase
= SerialPortLibUpdatePciRegister32 (
335 PciLibAddress
+ PCI_BASE_ADDRESSREG_OFFSET
+ BarIndex
* 4,
336 (UINT32
)PcdGet64 (PcdSerialRegisterBase
),
341 // Verify that the UART BAR is in the address range decoded by the parent PCI Bridge
343 if (PcdGetBool (PcdSerialUseMmio
)) {
344 if (((SerialRegisterBase
>> 16) & 0xfff0) < ParentMemoryBase
|| ((SerialRegisterBase
>> 16) & 0xfff0) > ParentMemoryLimit
) {
348 if ((SerialRegisterBase
>> 12) < ParentIoBase
|| (SerialRegisterBase
>> 12) > ParentIoLimit
) {
354 // Enable I/O and MMIO in PCI UART Device if they are not already enabled
357 PciLibAddress
+ PCI_COMMAND_OFFSET
,
358 PcdGetBool (PcdSerialUseMmio
) ? EFI_PCI_COMMAND_MEMORY_SPACE
: EFI_PCI_COMMAND_IO_SPACE
362 // Force D0 state if a Power Management and Status Register is specified
364 if (DeviceInfo
->PowerManagementStatusAndControlRegister
!= 0x00) {
365 if ((PciRead16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
) & (BIT0
| BIT1
)) != 0x00) {
366 PciAnd16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
, (UINT16
)~(BIT0
| BIT1
));
368 // If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs
370 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, (UINT8
)(PcdGet8 (PcdSerialFifoControl
) & (B_UART_FCR_FIFOE
| B_UART_FCR_FIFO64
)));
375 // Get PCI Device Info
377 DeviceInfo
= (PCI_UART_DEVICE_INFO
*) PcdGetPtr (PcdSerialPciDeviceInfo
);
380 // Enable I/O or MMIO in PCI Bridge
381 // Assume Root Bus Numer is Zero.
383 for (BusNumber
= 0; (DeviceInfo
+ 1)->Device
!= 0xff; DeviceInfo
++) {
385 // Compute PCI Lib Address to PCI to PCI Bridge
387 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
390 // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge
393 PciLibAddress
+ PCI_COMMAND_OFFSET
,
394 PcdGetBool (PcdSerialUseMmio
) ? EFI_PCI_COMMAND_MEMORY_SPACE
: EFI_PCI_COMMAND_IO_SPACE
398 // Force D0 state if a Power Management and Status Register is specified
400 if (DeviceInfo
->PowerManagementStatusAndControlRegister
!= 0x00) {
401 if ((PciRead16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
) & (BIT0
| BIT1
)) != 0x00) {
402 PciAnd16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
, (UINT16
)~(BIT0
| BIT1
));
406 BusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
);
409 return SerialRegisterBase
;
413 Return whether the hardware flow control signal allows writing.
415 @param SerialRegisterBase The base address register of UART device.
417 @retval TRUE The serial port is writable.
418 @retval FALSE The serial port is not writable.
422 UINTN SerialRegisterBase
425 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
426 if (PcdGetBool (PcdSerialDetectCable
)) {
428 // Wait for both DSR and CTS to be set
429 // DSR is set if a cable is connected.
430 // CTS is set if it is ok to transmit data
432 // DSR CTS Description Action
433 // === === ======================================== ========
434 // 0 0 No cable connected. Wait
435 // 0 1 No cable connected. Wait
436 // 1 0 Cable connected, but not clear to send. Wait
437 // 1 1 Cable connected, and clear to send. Transmit
439 return (BOOLEAN
) ((SerialPortReadRegister (SerialRegisterBase
, R_UART_MSR
) & (B_UART_MSR_DSR
| B_UART_MSR_CTS
)) == (B_UART_MSR_DSR
| B_UART_MSR_CTS
));
442 // Wait for both DSR and CTS to be set OR for DSR to be clear.
443 // DSR is set if a cable is connected.
444 // CTS is set if it is ok to transmit data
446 // DSR CTS Description Action
447 // === === ======================================== ========
448 // 0 0 No cable connected. Transmit
449 // 0 1 No cable connected. Transmit
450 // 1 0 Cable connected, but not clear to send. Wait
451 // 1 1 Cable connected, and clar to send. Transmit
453 return (BOOLEAN
) ((SerialPortReadRegister (SerialRegisterBase
, R_UART_MSR
) & (B_UART_MSR_DSR
| B_UART_MSR_CTS
)) != (B_UART_MSR_DSR
));
461 Initialize the serial device hardware.
463 If no initialization is required, then return RETURN_SUCCESS.
464 If the serial device was successfully initialized, then return RETURN_SUCCESS.
465 If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
467 @retval RETURN_SUCCESS The serial device was initialized.
468 @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
473 SerialPortInitialize (
477 RETURN_STATUS Status
;
478 UINTN SerialRegisterBase
;
480 UINT32 CurrentDivisor
;
484 // Perform platform specific initialization required to enable use of the 16550 device
485 // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
487 Status
= PlatformHookSerialPortInitialize ();
488 if (RETURN_ERROR (Status
)) {
493 // Calculate divisor for baud generator
494 // Ref_Clk_Rate / Baud_Rate / 16
496 Divisor
= PcdGet32 (PcdSerialClockRate
) / (PcdGet32 (PcdSerialBaudRate
) * 16);
497 if ((PcdGet32 (PcdSerialClockRate
) % (PcdGet32 (PcdSerialBaudRate
) * 16)) >= PcdGet32 (PcdSerialBaudRate
) * 8) {
502 // Get the base address of the serial port in either I/O or MMIO space
504 SerialRegisterBase
= GetSerialRegisterBase ();
505 if (SerialRegisterBase
==0) {
506 return RETURN_DEVICE_ERROR
;
510 // See if the serial port is already initialized
513 if ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) & 0x3F) != (PcdGet8 (PcdSerialLineControl
) & 0x3F)) {
516 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) | B_UART_LCR_DLAB
));
517 CurrentDivisor
= SerialPortReadRegister (SerialRegisterBase
, R_UART_BAUD_HIGH
) << 8;
518 CurrentDivisor
|= (UINT32
) SerialPortReadRegister (SerialRegisterBase
, R_UART_BAUD_LOW
);
519 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) & ~B_UART_LCR_DLAB
));
520 if (CurrentDivisor
!= Divisor
) {
524 return RETURN_SUCCESS
;
528 // Wait for the serial port to be ready.
529 // Verify that both the transmit FIFO and the shift register are empty.
531 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) != (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
));
534 // Configure baud rate
536 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, B_UART_LCR_DLAB
);
537 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_HIGH
, (UINT8
) (Divisor
>> 8));
538 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_LOW
, (UINT8
) (Divisor
& 0xff));
541 // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
542 // Strip reserved bits from PcdSerialLineControl
544 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(PcdGet8 (PcdSerialLineControl
) & 0x3F));
547 // Enable and reset FIFOs
548 // Strip reserved bits from PcdSerialFifoControl
550 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, 0x00);
551 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, (UINT8
)(PcdGet8 (PcdSerialFifoControl
) & (B_UART_FCR_FIFOE
| B_UART_FCR_FIFO64
)));
554 // Put Modem Control Register(MCR) into its reset state of 0x00.
556 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, 0x00);
558 return RETURN_SUCCESS
;
562 Write data from buffer to serial device.
564 Writes NumberOfBytes data bytes from Buffer to the serial device.
565 The number of bytes actually written to the serial device is returned.
566 If the return value is less than NumberOfBytes, then the write operation failed.
568 If Buffer is NULL, then ASSERT().
570 If NumberOfBytes is zero, then return 0.
572 @param Buffer Pointer to the data buffer to be written.
573 @param NumberOfBytes Number of bytes to written to the serial device.
575 @retval 0 NumberOfBytes is 0.
576 @retval >0 The number of bytes written to the serial device.
577 If this value is less than NumberOfBytes, then the read operation failed.
584 IN UINTN NumberOfBytes
587 UINTN SerialRegisterBase
;
592 if (Buffer
== NULL
) {
596 SerialRegisterBase
= GetSerialRegisterBase ();
597 if (SerialRegisterBase
==0) {
601 if (NumberOfBytes
== 0) {
603 // Flush the hardware
607 // Wait for both the transmit FIFO and shift register empty.
609 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) != (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
));
612 // Wait for the hardware flow control signal
614 while (!SerialPortWritable (SerialRegisterBase
));
619 // Compute the maximum size of the Tx FIFO
622 if ((PcdGet8 (PcdSerialFifoControl
) & B_UART_FCR_FIFOE
) != 0) {
623 if ((PcdGet8 (PcdSerialFifoControl
) & B_UART_FCR_FIFO64
) == 0) {
626 FifoSize
= PcdGet32 (PcdSerialExtendedTxFifoSize
);
630 Result
= NumberOfBytes
;
631 while (NumberOfBytes
!= 0) {
633 // Wait for the serial port to be ready, to make sure both the transmit FIFO
634 // and shift register empty.
636 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & B_UART_LSR_TEMT
) == 0);
639 // Fill then entire Tx FIFO
641 for (Index
= 0; Index
< FifoSize
&& NumberOfBytes
!= 0; Index
++, NumberOfBytes
--, Buffer
++) {
643 // Wait for the hardware flow control signal
645 while (!SerialPortWritable (SerialRegisterBase
));
648 // Write byte to the transmit buffer.
650 SerialPortWriteRegister (SerialRegisterBase
, R_UART_TXBUF
, *Buffer
);
657 Reads data from a serial device into a buffer.
659 @param Buffer Pointer to the data buffer to store the data read from the serial device.
660 @param NumberOfBytes Number of bytes to read from the serial device.
662 @retval 0 NumberOfBytes is 0.
663 @retval >0 The number of bytes read from the serial device.
664 If this value is less than NumberOfBytes, then the read operation failed.
671 IN UINTN NumberOfBytes
674 UINTN SerialRegisterBase
;
678 if (NULL
== Buffer
) {
682 SerialRegisterBase
= GetSerialRegisterBase ();
683 if (SerialRegisterBase
==0) {
687 Mcr
= (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) & ~B_UART_MCR_RTS
);
689 for (Result
= 0; NumberOfBytes
-- != 0; Result
++, Buffer
++) {
691 // Wait for the serial port to have some data.
693 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & B_UART_LSR_RXRDY
) == 0) {
694 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
696 // Set RTS to let the peer send some data
698 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(Mcr
| B_UART_MCR_RTS
));
701 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
703 // Clear RTS to prevent peer from sending data
705 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, Mcr
);
709 // Read byte from the receive buffer.
711 *Buffer
= SerialPortReadRegister (SerialRegisterBase
, R_UART_RXBUF
);
719 Polls a serial device to see if there is any data waiting to be read.
721 Polls aserial device to see if there is any data waiting to be read.
722 If there is data waiting to be read from the serial device, then TRUE is returned.
723 If there is no data waiting to be read from the serial device, then FALSE is returned.
725 @retval TRUE Data is waiting to be read from the serial device.
726 @retval FALSE There is no data waiting to be read from the serial device.
735 UINTN SerialRegisterBase
;
737 SerialRegisterBase
= GetSerialRegisterBase ();
738 if (SerialRegisterBase
==0) {
743 // Read the serial port status
745 if ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & B_UART_LSR_RXRDY
) != 0) {
746 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
748 // Clear RTS to prevent peer from sending data
750 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) & ~B_UART_MCR_RTS
));
755 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
757 // Set RTS to let the peer send some data
759 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) | B_UART_MCR_RTS
));