MdePkg/Include/IndustryStandard/Cxl11.h

   1 /** @file
   2   CXL 1.1 Register definitions
   3
   4   This file contains the register definitions based on the Compute Express Link
   5   (CXL) Specification Revision 1.1.
   6
   7 Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
   8 SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10 **/
  11
  12 #ifndef _CXL11_H_
  13 #define _CXL11_H_
  14
  15 #include <IndustryStandard/Pci.h>
  16 //
  17 // DVSEC Vendor ID
  18 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58
  19 // (subject to change as per CXL assigned Vendor ID)
  20 //
  21 #define INTEL_CXL_DVSEC_VENDOR_ID                                       0x8086
  22
  23 //
  24 // CXL Flex Bus Device default device and function number
  25 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1
  26 //
  27 #define CXL_DEV_DEV                                                     0
  28 #define CXL_DEV_FUNC                                                    0
  29
  30 //
  31 // Ensure proper structure formats
  32 //
  33 #pragma pack(1)
  34
  35 ///
  36 /// The PCIe DVSEC for Flex Bus Device
  37 ///@{
  38 typedef union {
  39   struct {
  40     UINT16 CacheCapable                                         : 1; // bit 0
  41     UINT16 IoCapable                                            : 1; // bit 1
  42     UINT16 MemCapable                                           : 1; // bit 2
  43     UINT16 MemHwInitMode                                        : 1; // bit 3
  44     UINT16 HdmCount                                             : 2; // bit 4..5
  45     UINT16 Reserved1                                            : 8; // bit 6..13
  46     UINT16 ViralCapable                                         : 1; // bit 14
  47     UINT16 Reserved2                                            : 1; // bit 15
  48   } Bits;
  49   UINT16                                                        Uint16;
  50 } CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;
  51
  52 typedef union {
  53   struct {
  54     UINT16 CacheEnable                                          : 1; // bit 0
  55     UINT16 IoEnable                                             : 1; // bit 1
  56     UINT16 MemEnable                                            : 1; // bit 2
  57     UINT16 CacheSfCoverage                                      : 5; // bit 3..7
  58     UINT16 CacheSfGranularity                                   : 3; // bit 8..10
  59     UINT16 CacheCleanEviction                                   : 1; // bit 11
  60     UINT16 Reserved1                                            : 2; // bit 12..13
  61     UINT16 ViralEnable                                          : 1; // bit 14
  62     UINT16 Reserved2                                            : 1; // bit 15
  63   } Bits;
  64   UINT16                                                        Uint16;
  65 } CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;
  66
  67 typedef union {
  68   struct {
  69     UINT16 Reserved1                                            : 14; // bit 0..13
  70     UINT16 ViralStatus                                          : 1;  // bit 14
  71     UINT16 Reserved2                                            : 1;  // bit 15
  72   } Bits;
  73   UINT16                                                        Uint16;
  74 } CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;
  75
  76 typedef union {
  77   struct {
  78     UINT16 Reserved1                                            : 1;  // bit 0
  79     UINT16 Reserved2                                            : 1;  // bit 1
  80     UINT16 Reserved3                                            : 1;  // bit 2
  81     UINT16 Reserved4                                            : 13; // bit 3..15
  82   } Bits;
  83   UINT16                                                        Uint16;
  84 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;
  85
  86 typedef union {
  87   struct {
  88     UINT16 Reserved1                                            : 1;  // bit 0
  89     UINT16 Reserved2                                            : 1;  // bit 1
  90     UINT16 Reserved3                                            : 14; // bit 2..15
  91   } Bits;
  92   UINT16                                                        Uint16;
  93 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;
  94
  95 typedef union {
  96   struct {
  97     UINT16 ConfigLock                                           : 1;  // bit 0
  98     UINT16 Reserved1                                            : 15; // bit 1..15
  99   } Bits;
 100   UINT16                                                        Uint16;
 101 } CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;
 102
 103 typedef union {
 104   struct {
 105     UINT32 MemorySizeHigh                                       : 32; // bit 0..31
 106   } Bits;
 107   UINT32                                                        Uint32;
 108 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;
 109
 110 typedef union {
 111   struct {
 112     UINT32 MemoryInfoValid                                      : 1;  // bit 0
 113     UINT32 MemoryActive                                         : 1;  // bit 1
 114     UINT32 MediaType                                            : 3;  // bit 2..4
 115     UINT32 MemoryClass                                          : 3;  // bit 5..7
 116     UINT32 DesiredInterleave                                    : 3;  // bit 8..10
 117     UINT32 Reserved                                             : 17; // bit 11..27
 118     UINT32 MemorySizeLow                                        : 4;  // bit 28..31
 119   } Bits;
 120   UINT32                                                        Uint32;
 121 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;
 122
 123 typedef union {
 124   struct {
 125     UINT32 MemoryBaseHigh                                       : 32; // bit 0..31
 126   } Bits;
 127   UINT32                                                        Uint32;
 128 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;
 129
 130 typedef union {
 131   struct {
 132     UINT32 Reserved                                             : 28; // bit 0..27
 133     UINT32 MemoryBaseLow                                        : 4;  // bit 28..31
 134   } Bits;
 135   UINT32                                                        Uint32;
 136 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;
 137
 138
 139 typedef union {
 140   struct {
 141     UINT32 MemorySizeHigh                                       : 32; // bit 0..31
 142   } Bits;
 143   UINT32                                                        Uint32;
 144 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;
 145
 146 typedef union {
 147   struct {
 148     UINT32 MemoryInfoValid                                      : 1;  // bit 0
 149     UINT32 MemoryActive                                         : 1;  // bit 1
 150     UINT32 MediaType                                            : 3;  // bit 2..4
 151     UINT32 MemoryClass                                          : 3;  // bit 5..7
 152     UINT32 DesiredInterleave                                    : 3;  // bit 8..10
 153     UINT32 Reserved                                             : 17; // bit 11..27
 154     UINT32 MemorySizeLow                                        : 4;  // bit 28..31
 155   } Bits;
 156   UINT32                                                        Uint32;
 157 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;
 158
 159 typedef union {
 160   struct {
 161     UINT32 MemoryBaseHigh                                       : 32; // bit 0..31
 162   } Bits;
 163   UINT32                                                        Uint32;
 164 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;
 165
 166 typedef union {
 167   struct {
 168     UINT32 Reserved                                             : 28; // bit 0..27
 169     UINT32 MemoryBaseLow                                        : 4;  // bit 28..31
 170   } Bits;
 171   UINT32                                                        Uint32;
 172 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;
 173
 174 //
 175 // Flex Bus Device DVSEC ID
 176 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58
 177 //
 178 #define FLEX_BUS_DEVICE_DVSEC_ID                                0
 179
 180 //
 181 // PCIe DVSEC for Flex Bus Device
 182 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95
 183 //
 184 typedef struct {
 185   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;                           // offset 0
 186   PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1               DesignatedVendorSpecificHeader1;  // offset 4
 187   PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2               DesignatedVendorSpecificHeader2;  // offset 8
 188   CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY                          DeviceCapability;                 // offset 10
 189   CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL                             DeviceControl;                    // offset 12
 190   CXL_DVSEC_FLEX_BUS_DEVICE_STATUS                              DeviceStatus;                     // offset 14
 191   CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2                        DeviceControl2;                   // offset 16
 192   CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2                         DeviceStatus2;                    // offset 18
 193   CXL_DVSEC_FLEX_BUS_DEVICE_LOCK                                DeviceLock;                       // offset 20
 194   UINT16                                                        Reserved;                         // offset 22
 195   CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH                    DeviceRange1SizeHigh;             // offset 24
 196   CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW                     DeviceRange1SizeLow;              // offset 28
 197   CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH                    DeviceRange1BaseHigh;             // offset 32
 198   CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW                     DeviceRange1BaseLow;              // offset 36
 199   CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH                    DeviceRange2SizeHigh;             // offset 40
 200   CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW                     DeviceRange2SizeLow;              // offset 44
 201   CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH                    DeviceRange2BaseHigh;             // offset 48
 202   CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW                     DeviceRange2BaseLow;              // offset 52
 203 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE;
 204 ///@}
 205
 206 ///
 207 /// PCIe DVSEC for FLex Bus Port
 208 ///@{
 209 typedef union {
 210   struct {
 211     UINT16 CacheCapable                                         : 1;  // bit 0
 212     UINT16 IoCapable                                            : 1;  // bit 1
 213     UINT16 MemCapable                                           : 1;  // bit 2
 214     UINT16 Reserved                                             : 13; // bit 3..15
 215   } Bits;
 216   UINT16                                                        Uint16;
 217 } CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;
 218
 219 typedef union {
 220   struct {
 221     UINT16 CacheEnable                                          : 1; // bit 0
 222     UINT16 IoEnable                                             : 1; // bit 1
 223     UINT16 MemEnable                                            : 1; // bit 2
 224     UINT16 CxlSyncBypassEnable                                  : 1; // bit 3
 225     UINT16 DriftBufferEnable                                    : 1; // bit 4
 226     UINT16 Reserved                                             : 3; // bit 5..7
 227     UINT16 Retimer1Present                                      : 1; // bit 8
 228     UINT16 Retimer2Present                                      : 1; // bit 9
 229     UINT16 Reserved2                                            : 6; // bit 10..15
 230   } Bits;
 231   UINT16                                                        Uint16;
 232 } CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;
 233
 234 typedef union {
 235   struct {
 236     UINT16 CacheEnable                                          : 1; // bit 0
 237     UINT16 IoEnable                                             : 1; // bit 1
 238     UINT16 MemEnable                                            : 1; // bit 2
 239     UINT16 CxlSyncBypassEnable                                  : 1; // bit 3
 240     UINT16 DriftBufferEnable                                    : 1; // bit 4
 241     UINT16 Reserved                                             : 3; // bit 5..7
 242     UINT16 CxlCorrectableProtocolIdFramingError                 : 1; // bit 8
 243     UINT16 CxlUncorrectableProtocolIdFramingError               : 1; // bit 9
 244     UINT16 CxlUnexpectedProtocolIdDropped                       : 1; // bit 10
 245     UINT16 Reserved2                                            : 5; // bit 11..15
 246   } Bits;
 247   UINT16                                                        Uint16;
 248 } CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;
 249
 250 //
 251 // Flex Bus Port DVSEC ID
 252 // Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62
 253 //
 254 #define FLEX_BUS_PORT_DVSEC_ID                                  7
 255
 256 //
 257 // PCIe DVSEC for Flex Bus Port
 258 // Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99
 259 //
 260 typedef struct {
 261   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;                           // offset 0
 262   PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1               DesignatedVendorSpecificHeader1;  // offset 4
 263   PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2               DesignatedVendorSpecificHeader2;  // offset 8
 264   CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY                        PortCapability;                   // offset 10
 265   CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL                           PortControl;                      // offset 12
 266   CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS                            PortStatus;                       // offset 14
 267 } CXL_1_1_DVSEC_FLEX_BUS_PORT;
 268 ///@}
 269
 270 ///
 271 /// CXL 1.1 Upstream and Downstream Port Subsystem Component registers
 272 ///
 273
 274 /// The CXL.Cache and CXL.Memory Architectural register definitions
 275 /// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1
 276 ///@{
 277
 278 #define CXL_CAPABILITY_HEADER_OFFSET                            0
 279 typedef union {
 280   struct {
 281     UINT32 CxlCapabilityId                                      : 16; // bit 0..15
 282     UINT32 CxlCapabilityVersion                                 :  4; // bit 16..19
 283     UINT32 CxlCacheMemVersion                                   :  4; // bit 20..23
 284     UINT32 ArraySize                                            :  8; // bit 24..31
 285   } Bits;
 286   UINT32                                                        Uint32;
 287 } CXL_CAPABILITY_HEADER;
 288
 289 #define CXL_RAS_CAPABILITY_HEADER_OFFSET                        4
 290 typedef union {
 291   struct {
 292     UINT32 CxlCapabilityId                                      : 16; // bit 0..15
 293     UINT32 CxlCapabilityVersion                                 :  4; // bit 16..19
 294     UINT32 CxlRasCapabilityPointer                              : 12; // bit 20..31
 295   } Bits;
 296   UINT32                                                        Uint32;
 297 } CXL_RAS_CAPABILITY_HEADER;
 298
 299 #define CXL_SECURITY_CAPABILITY_HEADER_OFFSET                   8
 300 typedef union {
 301   struct {
 302     UINT32 CxlCapabilityId                                      : 16; // bit 0..15
 303     UINT32 CxlCapabilityVersion                                 :  4; // bit 16..19
 304     UINT32 CxlSecurityCapabilityPointer                         : 12; // bit 20..31
 305   } Bits;
 306   UINT32                                                        Uint32;
 307 } CXL_SECURITY_CAPABILITY_HEADER;
 308
 309 #define CXL_LINK_CAPABILITY_HEADER_OFFSET                       0xC
 310 typedef union {
 311   struct {
 312     UINT32 CxlCapabilityId                                      : 16; // bit 0..15
 313     UINT32 CxlCapabilityVersion                                 :  4; // bit 16..19
 314     UINT32 CxlLinkCapabilityPointer                             : 12; // bit 20..31
 315   } Bits;
 316   UINT32                                                        Uint32;
 317 } CXL_LINK_CAPABILITY_HEADER;
 318
 319 typedef union {
 320   struct {
 321     UINT32 CacheDataParity                                      :  1; // bit 0..0
 322     UINT32 CacheAddressParity                                   :  1; // bit 1..1
 323     UINT32 CacheByteEnableParity                                :  1; // bit 2..2
 324     UINT32 CacheDataEcc                                         :  1; // bit 3..3
 325     UINT32 MemDataParity                                        :  1; // bit 4..4
 326     UINT32 MemAddressParity                                     :  1; // bit 5..5
 327     UINT32 MemByteEnableParity                                  :  1; // bit 6..6
 328     UINT32 MemDataEcc                                           :  1; // bit 7..7
 329     UINT32 ReInitThreshold                                      :  1; // bit 8..8
 330     UINT32 RsvdEncodingViolation                                :  1; // bit 9..9
 331     UINT32 PoisonReceived                                       :  1; // bit 10..10
 332     UINT32 ReceiverOverflow                                     :  1; // bit 11..11
 333     UINT32 Reserved                                             : 20; // bit 12..31
 334   } Bits;
 335   UINT32                                                        Uint32;
 336 } CXL_1_1_UNCORRECTABLE_ERROR_STATUS;
 337
 338 typedef union {
 339   struct {
 340     UINT32 CacheDataParityMask                                  :  1; // bit 0..0
 341     UINT32 CacheAddressParityMask                               :  1; // bit 1..1
 342     UINT32 CacheByteEnableParityMask                            :  1; // bit 2..2
 343     UINT32 CacheDataEccMask                                     :  1; // bit 3..3
 344     UINT32 MemDataParityMask                                    :  1; // bit 4..4
 345     UINT32 MemAddressParityMask                                 :  1; // bit 5..5
 346     UINT32 MemByteEnableParityMask                              :  1; // bit 6..6
 347     UINT32 MemDataEccMask                                       :  1; // bit 7..7
 348     UINT32 ReInitThresholdMask                                  :  1; // bit 8..8
 349     UINT32 RsvdEncodingViolationMask                            :  1; // bit 9..9
 350     UINT32 PoisonReceivedMask                                   :  1; // bit 10..10
 351     UINT32 ReceiverOverflowMask                                 :  1; // bit 11..11
 352     UINT32 Reserved                                             : 20; // bit 12..31
 353   } Bits;
 354   UINT32                                                        Uint32;
 355 } CXL_1_1_UNCORRECTABLE_ERROR_MASK;
 356
 357 typedef union {
 358   struct {
 359     UINT32 CacheDataParitySeverity                              :  1; // bit 0..0
 360     UINT32 CacheAddressParitySeverity                           :  1; // bit 1..1
 361     UINT32 CacheByteEnableParitySeverity                        :  1; // bit 2..2
 362     UINT32 CacheDataEccSeverity                                 :  1; // bit 3..3
 363     UINT32 MemDataParitySeverity                                :  1; // bit 4..4
 364     UINT32 MemAddressParitySeverity                             :  1; // bit 5..5
 365     UINT32 MemByteEnableParitySeverity                          :  1; // bit 6..6
 366     UINT32 MemDataEccSeverity                                   :  1; // bit 7..7
 367     UINT32 ReInitThresholdSeverity                              :  1; // bit 8..8
 368     UINT32 RsvdEncodingViolationSeverity                        :  1; // bit 9..9
 369     UINT32 PoisonReceivedSeverity                               :  1; // bit 10..10
 370     UINT32 ReceiverOverflowSeverity                             :  1; // bit 11..11
 371     UINT32 Reserved                                             : 20; // bit 12..31
 372   } Bits;
 373   UINT32                                                        Uint32;
 374 } CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;
 375
 376 typedef union {
 377   struct {
 378     UINT32 CacheDataEcc                                         :  1; // bit 0..0
 379     UINT32 MemoryDataEcc                                        :  1; // bit 1..1
 380     UINT32 CrcThreshold                                         :  1; // bit 2..2
 381     UINT32 RetryThreshold                                       :  1; // bit 3..3
 382     UINT32 CachePoisonReceived                                  :  1; // bit 4..4
 383     UINT32 MemoryPoisonReceived                                 :  1; // bit 5..5
 384     UINT32 PhysicalLayerError                                   :  1; // bit 6..6
 385     UINT32 Reserved                                             : 25; // bit 7..31
 386   } Bits;
 387   UINT32                                                        Uint32;
 388 } CXL_CORRECTABLE_ERROR_STATUS;
 389
 390 typedef union {
 391   struct {
 392     UINT32 CacheDataEccMask                                     :  1; // bit 0..0
 393     UINT32 MemoryDataEccMask                                    :  1; // bit 1..1
 394     UINT32 CrcThresholdMask                                     :  1; // bit 2..2
 395     UINT32 RetryThresholdMask                                   :  1; // bit 3..3
 396     UINT32 CachePoisonReceivedMask                              :  1; // bit 4..4
 397     UINT32 MemoryPoisonReceivedMask                             :  1; // bit 5..5
 398     UINT32 PhysicalLayerErrorMask                               :  1; // bit 6..6
 399     UINT32 Reserved                                             : 25; // bit 7..31
 400   } Bits;
 401   UINT32                                                        Uint32;
 402 } CXL_CORRECTABLE_ERROR_MASK;
 403
 404 typedef union {
 405   struct {
 406     UINT32 FirstErrorPointer                                    :  4; // bit 0..3
 407     UINT32 Reserved1                                            :  5; // bit 4..8
 408     UINT32 MultipleHeaderRecordingCapability                    :  1; // bit 9..9
 409     UINT32 Reserved2                                            :  3; // bit 10..12
 410     UINT32 PoisonEnabled                                        :  1; // bit 13..13
 411     UINT32 Reserved3                                            : 18; // bit 14..31
 412   } Bits;
 413   UINT32                                                        Uint32;
 414 } CXL_ERROR_CAPABILITIES_AND_CONTROL;
 415
 416 typedef struct {
 417   CXL_1_1_UNCORRECTABLE_ERROR_STATUS                            UncorrectableErrorStatus;
 418   CXL_1_1_UNCORRECTABLE_ERROR_MASK                              UncorrectableErrorMask;
 419   CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY                          UncorrectableErrorSeverity;
 420   CXL_CORRECTABLE_ERROR_STATUS                                  CorrectableErrorStatus;
 421   CXL_CORRECTABLE_ERROR_MASK                                    CorrectableErrorMask;
 422   CXL_ERROR_CAPABILITIES_AND_CONTROL                            ErrorCapabilitiesAndControl;
 423   UINT32                                                        HeaderLog[16];
 424 } CXL_1_1_RAS_CAPABILITY_STRUCTURE;
 425
 426 typedef union {
 427   struct {
 428     UINT32 DeviceTrustLevel                                     :  2; // bit 0..1
 429     UINT32 Reserved                                             : 30; // bit 2..31
 430   } Bits;
 431   UINT32                                                        Uint32;
 432 } CXL_1_1_SECURITY_POLICY;
 433
 434 typedef struct {
 435   CXL_1_1_SECURITY_POLICY                                       SecurityPolicy;
 436 } CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;
 437
 438 typedef union {
 439   struct {
 440     UINT64 CxlLinkVersionSupported                              :  4; // bit 0..3
 441     UINT64 CxlLinkVersionReceived                               :  4; // bit 4..7
 442     UINT64 LlrWrapValueSupported                                :  8; // bit 8..15
 443     UINT64 LlrWrapValueReceived                                 :  8; // bit 16..23
 444     UINT64 NumRetryReceived                                     :  5; // bit 24..28
 445     UINT64 NumPhyReinitReceived                                 :  5; // bit 29..33
 446     UINT64 WrPtrReceived                                        :  8; // bit 34..41
 447     UINT64 EchoEseqReceived                                     :  8; // bit 42..49
 448     UINT64 NumFreeBufReceived                                   :  8; // bit 50..57
 449     UINT64 Reserved                                             :  6; // bit 58..63
 450   } Bits;
 451   UINT64                                                        Uint64;
 452 } CXL_LINK_LAYER_CAPABILITY;
 453
 454 typedef union {
 455   struct {
 456     UINT16 LlReset                                              :  1; // bit 0..0
 457     UINT16 LlInitStall                                          :  1; // bit 1..1
 458     UINT16 LlCrdStall                                           :  1; // bit 2..2
 459     UINT16 InitState                                            :  2; // bit 3..4
 460     UINT16 LlRetryBufferConsumed                                :  8; // bit 5..12
 461     UINT16 Reserved                                             :  3; // bit 13..15
 462   } Bits;
 463   UINT16                                                        Uint16;
 464 } CXL_LINK_LAYER_CONTROL_AND_STATUS;
 465
 466 typedef union {
 467   struct {
 468     UINT64 CacheReqCredits                                      : 10; // bit 0..9
 469     UINT64 CacheRspCredits                                      : 10; // bit 10..19
 470     UINT64 CacheDataCredits                                     : 10; // bit 20..29
 471     UINT64 MemReqRspCredits                                     : 10; // bit 30..39
 472     UINT64 MemDataCredits                                       : 10; // bit 40..49
 473   } Bits;
 474   UINT64                                                        Uint64;
 475 } CXL_LINK_LAYER_RX_CREDIT_CONTROL;
 476
 477 typedef union {
 478   struct {
 479     UINT64 CacheReqCredits                                      : 10; // bit 0..9
 480     UINT64 CacheRspCredits                                      : 10; // bit 10..19
 481     UINT64 CacheDataCredits                                     : 10; // bit 20..29
 482     UINT64 MemReqRspCredits                                     : 10; // bit 30..39
 483     UINT64 MemDataCredits                                       : 10; // bit 40..49
 484   } Bits;
 485   UINT64                                                        Uint64;
 486 } CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;
 487
 488 typedef union {
 489   struct {
 490     UINT64 CacheReqCredits                                      : 10; // bit 0..9
 491     UINT64 CacheRspCredits                                      : 10; // bit 10..19
 492     UINT64 CacheDataCredits                                     : 10; // bit 20..29
 493     UINT64 MemReqRspCredits                                     : 10; // bit 30..39
 494     UINT64 MemDataCredits                                       : 10; // bit 40..49
 495   } Bits;
 496   UINT64                                                        Uint64;
 497 } CXL_LINK_LAYER_TX_CREDIT_STATUS;
 498
 499 typedef union {
 500   struct {
 501     UINT32 AckForceThreshold                                    :  8; // bit 0..7
 502     UINT32 AckFLushRetimer                                      : 10; // bit 8..17
 503   } Bits;
 504   UINT32                                                        Uint32;
 505 } CXL_LINK_LAYER_ACK_TIMER_CONTROL;
 506
 507 typedef union {
 508   struct {
 509     UINT32 MdhDisable                                           :  1; // bit 0..0
 510     UINT32 Reserved                                             : 31; // bit 1..31
 511   } Bits;
 512   UINT32                                                        Uint32;
 513 } CXL_LINK_LAYER_DEFEATURE;
 514
 515 typedef struct {
 516   CXL_LINK_LAYER_CAPABILITY                                     LinkLayerCapability;
 517   CXL_LINK_LAYER_CONTROL_AND_STATUS                             LinkLayerControlStatus;
 518   CXL_LINK_LAYER_RX_CREDIT_CONTROL                              LinkLayerRxCreditControl;
 519   CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS                        LinkLayerRxCreditReturnStatus;
 520   CXL_LINK_LAYER_TX_CREDIT_STATUS                               LinkLayerTxCreditStatus;
 521   CXL_LINK_LAYER_ACK_TIMER_CONTROL                              LinkLayerAckTimerControl;
 522   CXL_LINK_LAYER_DEFEATURE                                      LinkLayerDefeature;
 523 } CXL_1_1_LINK_CAPABILITY_STRUCTURE;
 524
 525 #define CXL_IO_ARBITRATION_CONTROL_OFFSET                       0x180
 526 typedef union {
 527   struct {
 528     UINT32 Reserved1                                            :  4; // bit 0..3
 529     UINT32 WeightedRoundRobinArbitrationWeight                  :  4; // bit 4..7
 530     UINT32 Reserved2                                            : 24; // bit 8..31
 531   } Bits;
 532   UINT32                                                        Uint32;
 533 } CXL_IO_ARBITRATION_CONTROL;
 534
 535 #define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET             0x1C0
 536 typedef union {
 537   struct {
 538     UINT32 Reserved1                                            :  4; // bit 0..3
 539     UINT32 WeightedRoundRobinArbitrationWeight                  :  4; // bit 4..7
 540     UINT32 Reserved2                                            : 24; // bit 8..31
 541   } Bits;
 542   UINT32                                                        Uint32;
 543 } CXL_CACHE_MEMORY_ARBITRATION_CONTROL;
 544 ///@}
 545
 546 /// The CXL.RCRB base register definition
 547 /// Based on chapter 7.3 of Compute Express Link Specification Revision: 1.1
 548 ///@{
 549 typedef union {
 550   struct {
 551     UINT64 RcrbEnable                                           :  1; // bit 0..0
 552     UINT64 Reserved                                             : 12; // bit 1..12
 553     UINT64 RcrbBaseAddress                                      : 51; // bit 13..63
 554   } Bits;
 555   UINT64                                                        Uint64;
 556 } CXL_RCRB_BASE;
 557 ///@}
 558
 559 #pragma pack()
 560
 561 //
 562 // CXL Downstream / Upstream Port RCRB space register offsets
 563 // Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97
 564 //
 565 #define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET                                0x010
 566 #define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET                               0x014
 567 #define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET                   0x100
 568
 569 #endif