2 CXL 1.1 Register definitions
4 This file contains the register definitions based on the Compute Express Link
5 (CXL) Specification Revision 1.1.
7 Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
15 #include <IndustryStandard/Pci.h>
18 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58
19 // (subject to change as per CXL assigned Vendor ID)
21 #define INTEL_CXL_DVSEC_VENDOR_ID 0x8086
24 // CXL Flex Bus Device default device and function number
25 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1
28 #define CXL_DEV_FUNC 0
31 // Ensure proper structure formats
36 Macro used to verify the size of a data type at compile time and trigger a
37 STATIC_ASSERT() with an error message if the size of the data type does not
38 match the expected size.
40 @param TypeName Type name of data type to verify.
41 @param ExpectedSize The expected size, in bytes, of the data type specified
44 #define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \
46 sizeof (TypeName) == ExpectedSize, \
47 "Size of " #TypeName \
48 " does not meet CXL 1.1 Specification requirements." \
52 Macro used to verify the offset of a field in a data type at compile time and
53 trigger a STATIC_ASSERT() with an error message if the offset of the field in
54 the data type does not match the expected offset.
56 @param TypeName Type name of data type to verify.
57 @param FieldName Field name in the data type specified by TypeName to
59 @param ExpectedOffset The expected offset, in bytes, of the field specified
60 by TypeName and FieldName.
62 #define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) \
64 OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \
65 "Offset of " #TypeName "." #FieldName \
66 " does not meet CXL 1.1 Specification requirements." \
70 /// The PCIe DVSEC for Flex Bus Device
74 UINT16 CacheCapable
: 1; // bit 0
75 UINT16 IoCapable
: 1; // bit 1
76 UINT16 MemCapable
: 1; // bit 2
77 UINT16 MemHwInitMode
: 1; // bit 3
78 UINT16 HdmCount
: 2; // bit 4..5
79 UINT16 Reserved1
: 8; // bit 6..13
80 UINT16 ViralCapable
: 1; // bit 14
81 UINT16 Reserved2
: 1; // bit 15
84 } CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY
;
88 UINT16 CacheEnable
: 1; // bit 0
89 UINT16 IoEnable
: 1; // bit 1
90 UINT16 MemEnable
: 1; // bit 2
91 UINT16 CacheSfCoverage
: 5; // bit 3..7
92 UINT16 CacheSfGranularity
: 3; // bit 8..10
93 UINT16 CacheCleanEviction
: 1; // bit 11
94 UINT16 Reserved1
: 2; // bit 12..13
95 UINT16 ViralEnable
: 1; // bit 14
96 UINT16 Reserved2
: 1; // bit 15
99 } CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL
;
103 UINT16 Reserved1
: 14; // bit 0..13
104 UINT16 ViralStatus
: 1; // bit 14
105 UINT16 Reserved2
: 1; // bit 15
108 } CXL_DVSEC_FLEX_BUS_DEVICE_STATUS
;
112 UINT16 Reserved1
: 1; // bit 0
113 UINT16 Reserved2
: 1; // bit 1
114 UINT16 Reserved3
: 1; // bit 2
115 UINT16 Reserved4
: 13; // bit 3..15
118 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2
;
122 UINT16 Reserved1
: 1; // bit 0
123 UINT16 Reserved2
: 1; // bit 1
124 UINT16 Reserved3
: 14; // bit 2..15
127 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2
;
131 UINT16 ConfigLock
: 1; // bit 0
132 UINT16 Reserved1
: 15; // bit 1..15
135 } CXL_DVSEC_FLEX_BUS_DEVICE_LOCK
;
139 UINT32 MemorySizeHigh
: 32; // bit 0..31
142 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH
;
146 UINT32 MemoryInfoValid
: 1; // bit 0
147 UINT32 MemoryActive
: 1; // bit 1
148 UINT32 MediaType
: 3; // bit 2..4
149 UINT32 MemoryClass
: 3; // bit 5..7
150 UINT32 DesiredInterleave
: 3; // bit 8..10
151 UINT32 Reserved
: 17; // bit 11..27
152 UINT32 MemorySizeLow
: 4; // bit 28..31
155 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW
;
159 UINT32 MemoryBaseHigh
: 32; // bit 0..31
162 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH
;
166 UINT32 Reserved
: 28; // bit 0..27
167 UINT32 MemoryBaseLow
: 4; // bit 28..31
170 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW
;
174 UINT32 MemorySizeHigh
: 32; // bit 0..31
177 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH
;
181 UINT32 MemoryInfoValid
: 1; // bit 0
182 UINT32 MemoryActive
: 1; // bit 1
183 UINT32 MediaType
: 3; // bit 2..4
184 UINT32 MemoryClass
: 3; // bit 5..7
185 UINT32 DesiredInterleave
: 3; // bit 8..10
186 UINT32 Reserved
: 17; // bit 11..27
187 UINT32 MemorySizeLow
: 4; // bit 28..31
190 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW
;
194 UINT32 MemoryBaseHigh
: 32; // bit 0..31
197 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH
;
201 UINT32 Reserved
: 28; // bit 0..27
202 UINT32 MemoryBaseLow
: 4; // bit 28..31
205 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW
;
208 // Flex Bus Device DVSEC ID
209 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58
211 #define FLEX_BUS_DEVICE_DVSEC_ID 0
214 // PCIe DVSEC for Flex Bus Device
215 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95
218 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
; // offset 0
219 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1
; // offset 4
220 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2
; // offset 8
221 CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability
; // offset 10
222 CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl
; // offset 12
223 CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus
; // offset 14
224 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2
; // offset 16
225 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2
; // offset 18
226 CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock
; // offset 20
227 UINT16 Reserved
; // offset 22
228 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh
; // offset 24
229 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow
; // offset 28
230 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh
; // offset 32
231 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow
; // offset 36
232 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh
; // offset 40
233 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow
; // offset 44
234 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh
; // offset 48
235 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow
; // offset 52
236 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE
;
238 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, Header
, 0x00);
239 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DesignatedVendorSpecificHeader1
, 0x04);
240 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DesignatedVendorSpecificHeader2
, 0x08);
241 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceCapability
, 0x0A);
242 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceControl
, 0x0C);
243 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceStatus
, 0x0E);
244 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceControl2
, 0x10);
245 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceStatus2
, 0x12);
246 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceLock
, 0x14);
247 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceRange1SizeHigh
, 0x18);
248 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceRange1SizeLow
, 0x1C);
249 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceRange1BaseHigh
, 0x20);
250 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceRange1BaseLow
, 0x24);
251 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceRange2SizeHigh
, 0x28);
252 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceRange2SizeLow
, 0x2C);
253 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceRange2BaseHigh
, 0x30);
254 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, DeviceRange2BaseLow
, 0x34);
255 CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE
, 0x38);
259 /// PCIe DVSEC for FLex Bus Port
263 UINT16 CacheCapable
: 1; // bit 0
264 UINT16 IoCapable
: 1; // bit 1
265 UINT16 MemCapable
: 1; // bit 2
266 UINT16 Reserved
: 13; // bit 3..15
269 } CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY
;
273 UINT16 CacheEnable
: 1; // bit 0
274 UINT16 IoEnable
: 1; // bit 1
275 UINT16 MemEnable
: 1; // bit 2
276 UINT16 CxlSyncBypassEnable
: 1; // bit 3
277 UINT16 DriftBufferEnable
: 1; // bit 4
278 UINT16 Reserved
: 3; // bit 5..7
279 UINT16 Retimer1Present
: 1; // bit 8
280 UINT16 Retimer2Present
: 1; // bit 9
281 UINT16 Reserved2
: 6; // bit 10..15
284 } CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL
;
288 UINT16 CacheEnable
: 1; // bit 0
289 UINT16 IoEnable
: 1; // bit 1
290 UINT16 MemEnable
: 1; // bit 2
291 UINT16 CxlSyncBypassEnable
: 1; // bit 3
292 UINT16 DriftBufferEnable
: 1; // bit 4
293 UINT16 Reserved
: 3; // bit 5..7
294 UINT16 CxlCorrectableProtocolIdFramingError
: 1; // bit 8
295 UINT16 CxlUncorrectableProtocolIdFramingError
: 1; // bit 9
296 UINT16 CxlUnexpectedProtocolIdDropped
: 1; // bit 10
297 UINT16 Reserved2
: 5; // bit 11..15
300 } CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS
;
303 // Flex Bus Port DVSEC ID
304 // Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62
306 #define FLEX_BUS_PORT_DVSEC_ID 7
309 // PCIe DVSEC for Flex Bus Port
310 // Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99
313 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
; // offset 0
314 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1
; // offset 4
315 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2
; // offset 8
316 CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability
; // offset 10
317 CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl
; // offset 12
318 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus
; // offset 14
319 } CXL_1_1_DVSEC_FLEX_BUS_PORT
;
321 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT
, Header
, 0x00);
322 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT
, DesignatedVendorSpecificHeader1
, 0x04);
323 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT
, DesignatedVendorSpecificHeader2
, 0x08);
324 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT
, PortCapability
, 0x0A);
325 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT
, PortControl
, 0x0C);
326 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT
, PortStatus
, 0x0E);
327 CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT
, 0x10);
331 /// CXL 1.1 Upstream and Downstream Port Subsystem Component registers
334 /// The CXL.Cache and CXL.Memory Architectural register definitions
335 /// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1
338 #define CXL_CAPABILITY_HEADER_OFFSET 0
341 UINT32 CxlCapabilityId
: 16; // bit 0..15
342 UINT32 CxlCapabilityVersion
: 4; // bit 16..19
343 UINT32 CxlCacheMemVersion
: 4; // bit 20..23
344 UINT32 ArraySize
: 8; // bit 24..31
347 } CXL_CAPABILITY_HEADER
;
349 #define CXL_RAS_CAPABILITY_HEADER_OFFSET 4
352 UINT32 CxlCapabilityId
: 16; // bit 0..15
353 UINT32 CxlCapabilityVersion
: 4; // bit 16..19
354 UINT32 CxlRasCapabilityPointer
: 12; // bit 20..31
357 } CXL_RAS_CAPABILITY_HEADER
;
359 #define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8
362 UINT32 CxlCapabilityId
: 16; // bit 0..15
363 UINT32 CxlCapabilityVersion
: 4; // bit 16..19
364 UINT32 CxlSecurityCapabilityPointer
: 12; // bit 20..31
367 } CXL_SECURITY_CAPABILITY_HEADER
;
369 #define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC
372 UINT32 CxlCapabilityId
: 16; // bit 0..15
373 UINT32 CxlCapabilityVersion
: 4; // bit 16..19
374 UINT32 CxlLinkCapabilityPointer
: 12; // bit 20..31
377 } CXL_LINK_CAPABILITY_HEADER
;
381 UINT32 CacheDataParity
: 1; // bit 0..0
382 UINT32 CacheAddressParity
: 1; // bit 1..1
383 UINT32 CacheByteEnableParity
: 1; // bit 2..2
384 UINT32 CacheDataEcc
: 1; // bit 3..3
385 UINT32 MemDataParity
: 1; // bit 4..4
386 UINT32 MemAddressParity
: 1; // bit 5..5
387 UINT32 MemByteEnableParity
: 1; // bit 6..6
388 UINT32 MemDataEcc
: 1; // bit 7..7
389 UINT32 ReInitThreshold
: 1; // bit 8..8
390 UINT32 RsvdEncodingViolation
: 1; // bit 9..9
391 UINT32 PoisonReceived
: 1; // bit 10..10
392 UINT32 ReceiverOverflow
: 1; // bit 11..11
393 UINT32 Reserved
: 20; // bit 12..31
396 } CXL_1_1_UNCORRECTABLE_ERROR_STATUS
;
400 UINT32 CacheDataParityMask
: 1; // bit 0..0
401 UINT32 CacheAddressParityMask
: 1; // bit 1..1
402 UINT32 CacheByteEnableParityMask
: 1; // bit 2..2
403 UINT32 CacheDataEccMask
: 1; // bit 3..3
404 UINT32 MemDataParityMask
: 1; // bit 4..4
405 UINT32 MemAddressParityMask
: 1; // bit 5..5
406 UINT32 MemByteEnableParityMask
: 1; // bit 6..6
407 UINT32 MemDataEccMask
: 1; // bit 7..7
408 UINT32 ReInitThresholdMask
: 1; // bit 8..8
409 UINT32 RsvdEncodingViolationMask
: 1; // bit 9..9
410 UINT32 PoisonReceivedMask
: 1; // bit 10..10
411 UINT32 ReceiverOverflowMask
: 1; // bit 11..11
412 UINT32 Reserved
: 20; // bit 12..31
415 } CXL_1_1_UNCORRECTABLE_ERROR_MASK
;
419 UINT32 CacheDataParitySeverity
: 1; // bit 0..0
420 UINT32 CacheAddressParitySeverity
: 1; // bit 1..1
421 UINT32 CacheByteEnableParitySeverity
: 1; // bit 2..2
422 UINT32 CacheDataEccSeverity
: 1; // bit 3..3
423 UINT32 MemDataParitySeverity
: 1; // bit 4..4
424 UINT32 MemAddressParitySeverity
: 1; // bit 5..5
425 UINT32 MemByteEnableParitySeverity
: 1; // bit 6..6
426 UINT32 MemDataEccSeverity
: 1; // bit 7..7
427 UINT32 ReInitThresholdSeverity
: 1; // bit 8..8
428 UINT32 RsvdEncodingViolationSeverity
: 1; // bit 9..9
429 UINT32 PoisonReceivedSeverity
: 1; // bit 10..10
430 UINT32 ReceiverOverflowSeverity
: 1; // bit 11..11
431 UINT32 Reserved
: 20; // bit 12..31
434 } CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY
;
438 UINT32 CacheDataEcc
: 1; // bit 0..0
439 UINT32 MemoryDataEcc
: 1; // bit 1..1
440 UINT32 CrcThreshold
: 1; // bit 2..2
441 UINT32 RetryThreshold
: 1; // bit 3..3
442 UINT32 CachePoisonReceived
: 1; // bit 4..4
443 UINT32 MemoryPoisonReceived
: 1; // bit 5..5
444 UINT32 PhysicalLayerError
: 1; // bit 6..6
445 UINT32 Reserved
: 25; // bit 7..31
448 } CXL_CORRECTABLE_ERROR_STATUS
;
452 UINT32 CacheDataEccMask
: 1; // bit 0..0
453 UINT32 MemoryDataEccMask
: 1; // bit 1..1
454 UINT32 CrcThresholdMask
: 1; // bit 2..2
455 UINT32 RetryThresholdMask
: 1; // bit 3..3
456 UINT32 CachePoisonReceivedMask
: 1; // bit 4..4
457 UINT32 MemoryPoisonReceivedMask
: 1; // bit 5..5
458 UINT32 PhysicalLayerErrorMask
: 1; // bit 6..6
459 UINT32 Reserved
: 25; // bit 7..31
462 } CXL_CORRECTABLE_ERROR_MASK
;
466 UINT32 FirstErrorPointer
: 4; // bit 0..3
467 UINT32 Reserved1
: 5; // bit 4..8
468 UINT32 MultipleHeaderRecordingCapability
: 1; // bit 9..9
469 UINT32 Reserved2
: 3; // bit 10..12
470 UINT32 PoisonEnabled
: 1; // bit 13..13
471 UINT32 Reserved3
: 18; // bit 14..31
474 } CXL_ERROR_CAPABILITIES_AND_CONTROL
;
477 CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus
;
478 CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask
;
479 CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity
;
480 CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus
;
481 CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask
;
482 CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl
;
483 UINT32 HeaderLog
[16];
484 } CXL_1_1_RAS_CAPABILITY_STRUCTURE
;
486 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE
, UncorrectableErrorStatus
, 0x00);
487 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE
, UncorrectableErrorMask
, 0x04);
488 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE
, UncorrectableErrorSeverity
, 0x08);
489 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE
, CorrectableErrorStatus
, 0x0C);
490 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE
, CorrectableErrorMask
, 0x10);
491 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE
, ErrorCapabilitiesAndControl
, 0x14);
492 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE
, HeaderLog
, 0x18);
493 CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE
, 0x58);
497 UINT32 DeviceTrustLevel
: 2; // bit 0..1
498 UINT32 Reserved
: 30; // bit 2..31
501 } CXL_1_1_SECURITY_POLICY
;
504 CXL_1_1_SECURITY_POLICY SecurityPolicy
;
505 } CXL_1_1_SECURITY_CAPABILITY_STRUCTURE
;
507 CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE
, SecurityPolicy
, 0x0);
508 CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE
, 0x4);
512 UINT64 CxlLinkVersionSupported
: 4; // bit 0..3
513 UINT64 CxlLinkVersionReceived
: 4; // bit 4..7
514 UINT64 LlrWrapValueSupported
: 8; // bit 8..15
515 UINT64 LlrWrapValueReceived
: 8; // bit 16..23
516 UINT64 NumRetryReceived
: 5; // bit 24..28
517 UINT64 NumPhyReinitReceived
: 5; // bit 29..33
518 UINT64 WrPtrReceived
: 8; // bit 34..41
519 UINT64 EchoEseqReceived
: 8; // bit 42..49
520 UINT64 NumFreeBufReceived
: 8; // bit 50..57
521 UINT64 Reserved
: 6; // bit 58..63
524 } CXL_LINK_LAYER_CAPABILITY
;
528 UINT16 LlReset
: 1; // bit 0..0
529 UINT16 LlInitStall
: 1; // bit 1..1
530 UINT16 LlCrdStall
: 1; // bit 2..2
531 UINT16 InitState
: 2; // bit 3..4
532 UINT16 LlRetryBufferConsumed
: 8; // bit 5..12
533 UINT16 Reserved
: 3; // bit 13..15
536 } CXL_LINK_LAYER_CONTROL_AND_STATUS
;
540 UINT64 CacheReqCredits
: 10; // bit 0..9
541 UINT64 CacheRspCredits
: 10; // bit 10..19
542 UINT64 CacheDataCredits
: 10; // bit 20..29
543 UINT64 MemReqRspCredits
: 10; // bit 30..39
544 UINT64 MemDataCredits
: 10; // bit 40..49
547 } CXL_LINK_LAYER_RX_CREDIT_CONTROL
;
551 UINT64 CacheReqCredits
: 10; // bit 0..9
552 UINT64 CacheRspCredits
: 10; // bit 10..19
553 UINT64 CacheDataCredits
: 10; // bit 20..29
554 UINT64 MemReqRspCredits
: 10; // bit 30..39
555 UINT64 MemDataCredits
: 10; // bit 40..49
558 } CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS
;
562 UINT64 CacheReqCredits
: 10; // bit 0..9
563 UINT64 CacheRspCredits
: 10; // bit 10..19
564 UINT64 CacheDataCredits
: 10; // bit 20..29
565 UINT64 MemReqRspCredits
: 10; // bit 30..39
566 UINT64 MemDataCredits
: 10; // bit 40..49
569 } CXL_LINK_LAYER_TX_CREDIT_STATUS
;
573 UINT32 AckForceThreshold
: 8; // bit 0..7
574 UINT32 AckFLushRetimer
: 10; // bit 8..17
577 } CXL_LINK_LAYER_ACK_TIMER_CONTROL
;
581 UINT32 MdhDisable
: 1; // bit 0..0
582 UINT32 Reserved
: 31; // bit 1..31
585 } CXL_LINK_LAYER_DEFEATURE
;
588 CXL_LINK_LAYER_CAPABILITY LinkLayerCapability
;
589 CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus
;
590 CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl
;
591 CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus
;
592 CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus
;
593 CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl
;
594 CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature
;
595 } CXL_1_1_LINK_CAPABILITY_STRUCTURE
;
597 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE
, LinkLayerCapability
, 0x00);
598 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE
, LinkLayerControlStatus
, 0x08);
599 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE
, LinkLayerRxCreditControl
, 0x10);
600 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE
, LinkLayerRxCreditReturnStatus
, 0x18);
601 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE
, LinkLayerTxCreditStatus
, 0x20);
602 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE
, LinkLayerAckTimerControl
, 0x28);
603 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE
, LinkLayerDefeature
, 0x30);
604 CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE
, 0x38);
606 #define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180
609 UINT32 Reserved1
: 4; // bit 0..3
610 UINT32 WeightedRoundRobinArbitrationWeight
: 4; // bit 4..7
611 UINT32 Reserved2
: 24; // bit 8..31
614 } CXL_IO_ARBITRATION_CONTROL
;
616 CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL
, 0x4);
618 #define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0
621 UINT32 Reserved1
: 4; // bit 0..3
622 UINT32 WeightedRoundRobinArbitrationWeight
: 4; // bit 4..7
623 UINT32 Reserved2
: 24; // bit 8..31
626 } CXL_CACHE_MEMORY_ARBITRATION_CONTROL
;
628 CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL
, 0x4);
632 /// The CXL.RCRB base register definition
633 /// Based on chapter 7.3 of Compute Express Link Specification Revision: 1.1
637 UINT64 RcrbEnable
: 1; // bit 0..0
638 UINT64 Reserved
: 12; // bit 1..12
639 UINT64 RcrbBaseAddress
: 51; // bit 13..63
644 CXL_11_SIZE_ASSERT (CXL_RCRB_BASE
, 0x8);
651 // CXL Downstream / Upstream Port RCRB space register offsets
652 // Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97
654 #define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010
655 #define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014
656 #define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100