2 Definitions based on NVMe spec. version 1.1.
4 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
5 Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
8 @par Specification Reference:
10 NVMe Specification 1.4
11 NVMe Specification 2.0
21 // controller register offsets
23 #define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
24 #define NVME_VER_OFFSET 0x0008 // Version
25 #define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
26 #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
27 #define NVME_CC_OFFSET 0x0014 // Controller Configuration
28 #define NVME_CSTS_OFFSET 0x001c // Controller Status
29 #define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
30 #define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
31 #define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
32 #define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
33 #define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information
34 #define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select
35 #define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location
36 #define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
37 #define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
40 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
41 // Get the doorbell stride bit shift value from the controller capabilities.
43 #define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
44 #define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
49 // 3.1.1 Offset 00h: CAP - Controller Capabilities
52 UINT16 Mqes
; // Maximum Queue Entries Supported
53 UINT8 Cqr
: 1; // Contiguous Queues Required
54 UINT8 Ams
: 2; // Arbitration Mechanism Supported
58 UINT16 Nssrs
: 1; // NVM Subsystem Reset Supported NSSRS
59 UINT16 Css
: 8; // Command Sets Supported - Bit 37
60 UINT16 Bps
: 1; // Boot Partition Support - Bit 45 in NVMe1.4
70 // 3.1.2 Offset 08h: VS - Version
73 UINT16 Mnr
; // Minor version number
74 UINT16 Mjr
; // Major version number
78 // 3.1.5 Offset 14h: CC - Controller Configuration
81 UINT16 En
: 1; // Enable
83 UINT16 Css
: 3; // I/O Command Set Selected
84 UINT16 Mps
: 4; // Memory Page Size
85 UINT16 Ams
: 3; // Arbitration Mechanism Selected
86 UINT16 Shn
: 2; // Shutdown Notification
87 UINT8 Iosqes
: 4; // I/O Submission Queue Entry Size
88 UINT8 Iocqes
: 4; // I/O Completion Queue Entry Size
91 #define NVME_CC_SHN_NORMAL_SHUTDOWN 1
92 #define NVME_CC_SHN_ABRUPT_SHUTDOWN 2
95 // 3.1.6 Offset 1Ch: CSTS - Controller Status
98 UINT32 Rdy
: 1; // Ready
99 UINT32 Cfs
: 1; // Controller Fatal Status
100 UINT32 Shst
: 2; // Shutdown Status
101 UINT32 Nssro
: 1; // NVM Subsystem Reset Occurred
104 #define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
105 #define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
107 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
110 UINT16 Asqs
: 12; // Submission Queue Size
112 UINT16 Acqs
: 12; // Completion Queue Size
117 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
119 #define NVME_ASQ UINT64
121 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
123 #define NVME_ACQ UINT64
126 // 3.1.13 Offset 40h: BPINFO - Boot Partition Information
129 UINT32 Bpsz
: 15; // Boot Partition Size
131 UINT32 Brs
: 2; // Boot Read Status
133 UINT32 Abpid
: 1; // Active Boot Partition ID
137 // 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select
140 UINT32 Bprsz
: 10; // Boot Partition Read Size
141 UINT32 Bprof
: 20; // Boot Partition Read Offset
143 UINT32 Bpid
: 1; // Boot Partition Identifier
147 // 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optional)
151 UINT64 Bmbba
: 52; // Boot Partition Memory Buffer Base Address
155 // 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
163 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
171 // NVM command set structures
179 UINT64 Slba
; /* Starting Sector Address */
183 UINT16 Nlb
; /* Number of Sectors */
185 UINT16 Prinfo
: 4; /* Protection Info Check */
186 UINT16 Fua
: 1; /* Force Unit Access */
187 UINT16 Lr
: 1; /* Limited Retry */
191 UINT32 Af
: 4; /* Access Frequency */
192 UINT32 Al
: 2; /* Access Latency */
193 UINT32 Sr
: 1; /* Sequential Request */
194 UINT32 In
: 1; /* Incompressible */
199 UINT32 Eilbrt
; /* Expected Initial Logical Block Reference Tag */
203 UINT16 Elbat
; /* Expected Logical Block Application Tag */
204 UINT16 Elbatm
; /* Expected Logical Block Application Tag Mask */
214 UINT64 Slba
; /* Starting Sector Address */
218 UINT16 Nlb
; /* Number of Sectors */
220 UINT16 Prinfo
: 4; /* Protection Info Check */
221 UINT16 Fua
: 1; /* Force Unit Access */
222 UINT16 Lr
: 1; /* Limited Retry */
226 UINT32 Af
: 4; /* Access Frequency */
227 UINT32 Al
: 2; /* Access Latency */
228 UINT32 Sr
: 1; /* Sequential Request */
229 UINT32 In
: 1; /* Incompressible */
234 UINT32 Ilbrt
; /* Initial Logical Block Reference Tag */
238 UINT16 Lbat
; /* Logical Block Application Tag */
239 UINT16 Lbatm
; /* Logical Block Application Tag Mask */
249 UINT32 Flush
; /* Flush */
253 // Write Uncorrectable command
259 UINT64 Slba
; /* Starting LBA */
263 UINT32 Nlb
: 16; /* Number of Logical Blocks */
265 } NVME_WRITE_UNCORRECTABLE
;
268 // Write Zeroes command
274 UINT64 Slba
; /* Starting LBA */
278 UINT16 Nlb
; /* Number of Logical Blocks */
280 UINT16 Prinfo
: 4; /* Protection Info Check */
281 UINT16 Fua
: 1; /* Force Unit Access */
282 UINT16 Lr
: 1; /* Limited Retry */
290 UINT32 Ilbrt
; /* Initial Logical Block Reference Tag */
294 UINT16 Lbat
; /* Logical Block Application Tag */
295 UINT16 Lbatm
; /* Logical Block Application Tag Mask */
305 UINT64 Slba
; /* Starting LBA */
309 UINT16 Nlb
; /* Number of Logical Blocks */
311 UINT16 Prinfo
: 4; /* Protection Info Check */
312 UINT16 Fua
: 1; /* Force Unit Access */
313 UINT16 Lr
: 1; /* Limited Retry */
321 UINT32 Eilbrt
; /* Expected Initial Logical Block Reference Tag */
325 UINT16 Elbat
; /* Expected Logical Block Application Tag */
326 UINT16 Elbatm
; /* Expected Logical Block Application Tag Mask */
333 NVME_WRITE_UNCORRECTABLE WriteUncorrectable
;
334 NVME_WRITE_ZEROES WriteZeros
;
335 NVME_COMPARE Compare
;
339 UINT16 Mp
; /* Maximum Power */
340 UINT8 Rsvd1
; /* Reserved as of Nvm Express 1.1 Spec */
341 UINT8 Mps
: 1; /* Max Power Scale */
342 UINT8 Nops
: 1; /* Non-Operational State */
343 UINT8 Rsvd2
: 6; /* Reserved as of Nvm Express 1.1 Spec */
344 UINT32 Enlat
; /* Entry Latency */
345 UINT32 Exlat
; /* Exit Latency */
346 UINT8 Rrt
: 5; /* Relative Read Throughput */
347 UINT8 Rsvd3
: 3; /* Reserved as of Nvm Express 1.1 Spec */
348 UINT8 Rrl
: 5; /* Relative Read Latency */
349 UINT8 Rsvd4
: 3; /* Reserved as of Nvm Express 1.1 Spec */
350 UINT8 Rwt
: 5; /* Relative Write Throughput */
351 UINT8 Rsvd5
: 3; /* Reserved as of Nvm Express 1.1 Spec */
352 UINT8 Rwl
: 5; /* Relative Write Latency */
353 UINT8 Rsvd6
: 3; /* Reserved as of Nvm Express 1.1 Spec */
354 UINT8 Rsvd7
[16]; /* Reserved as of Nvm Express 1.1 Spec */
358 // Identify Controller Data
362 // Controller Capabilities and Features 0-255
364 UINT16 Vid
; /* PCI Vendor ID */
365 UINT16 Ssvid
; /* PCI sub-system vendor ID */
366 UINT8 Sn
[20]; /* Product serial number */
368 UINT8 Mn
[40]; /* Product model number */
369 UINT8 Fr
[8]; /* Firmware Revision */
370 UINT8 Rab
; /* Recommended Arbitration Burst */
371 UINT8 Ieee_oui
[3]; /* Organization Unique Identifier */
372 UINT8 Cmic
; /* Multi-interface Capabilities */
373 UINT8 Mdts
; /* Maximum Data Transfer Size */
374 UINT8 Cntlid
[2]; /* Controller ID */
375 UINT8 Rsvd1
[176]; /* Reserved as of Nvm Express 1.1 Spec */
377 // Admin Command Set Attributes
379 UINT16 Oacs
; /* Optional Admin Command Support */
380 #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3
381 #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2
382 #define FORMAT_NVM_SUPPORTED BIT1
383 #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
384 UINT8 Acl
; /* Abort Command Limit */
385 UINT8 Aerl
; /* Async Event Request Limit */
386 UINT8 Frmw
; /* Firmware updates */
387 UINT8 Lpa
; /* Log Page Attributes */
388 UINT8 Elpe
; /* Error Log Page Entries */
389 UINT8 Npss
; /* Number of Power States Support */
390 UINT8 Avscc
; /* Admin Vendor Specific Command Configuration */
391 UINT8 Apsta
; /* Autonomous Power State Transition Attributes */
393 // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec
395 UINT16 Wctemp
; /* Warning Composite Temperature Threshold */
396 UINT16 Cctemp
; /* Critical Composite Temperature Threshold */
397 UINT16 Mtfa
; /* Maximum Time for Firmware Activation */
398 UINT32 Hmpre
; /* Host Memory Buffer Preferred Size */
399 UINT32 Hmmin
; /* Host Memory Buffer Minimum Size */
400 UINT8 Tnvmcap
[16]; /* Total NVM Capacity */
401 UINT8 Unvmcap
[16]; /* Unallocated NVM Capacity */
402 UINT32 Rpmbs
; /* Replay Protected Memory Block Support */
403 UINT16 Edstt
; /* Extended Device Self-test Time */
404 UINT8 Dsto
; /* Device Self-test Options */
405 UINT8 Fwug
; /* Firmware Update Granularity */
406 UINT8 Rsvd2
[192]; /* Reserved as of Nvm Express 1.4 Spec */
408 // NVM Command Set Attributes
410 UINT8 Sqes
; /* Submission Queue Entry Size */
411 UINT8 Cqes
; /* Completion Queue Entry Size */
412 UINT16 Rsvd3
; /* Reserved as of Nvm Express 1.1 Spec */
413 UINT32 Nn
; /* Number of Namespaces */
414 UINT16 Oncs
; /* Optional NVM Command Support */
415 UINT16 Fuses
; /* Fused Operation Support */
416 UINT8 Fna
; /* Format NVM Attributes */
417 UINT8 Vwc
; /* Volatile Write Cache */
418 UINT16 Awun
; /* Atomic Write Unit Normal */
419 UINT16 Awupf
; /* Atomic Write Unit Power Fail */
420 UINT8 Nvscc
; /* NVM Vendor Specific Command Configuration */
421 UINT8 Rsvd4
; /* Reserved as of Nvm Express 1.1 Spec */
422 UINT16 Acwu
; /* Atomic Compare & Write Unit */
423 UINT16 Rsvd5
; /* Reserved as of Nvm Express 1.1 Spec */
424 UINT32 Sgls
; /* SGL Support */
425 UINT8 Rsvd6
[164]; /* Reserved as of Nvm Express 1.1 Spec */
427 // I/O Command set Attributes
429 UINT8 Rsvd7
[1344]; /* Reserved as of Nvm Express 1.1 Spec */
431 // Power State Descriptors
433 NVME_PSDESCRIPTOR PsDescriptor
[32];
435 UINT8 VendorData
[1024]; /* Vendor specific data */
436 } NVME_ADMIN_CONTROLLER_DATA
;
439 UINT16 Ms
; /* Metadata Size */
440 UINT8 Lbads
; /* LBA Data Size */
441 UINT8 Rp
: 2; /* Relative Performance */
442 #define LBAF_RP_BEST 00b
443 #define LBAF_RP_BETTER 01b
444 #define LBAF_RP_GOOD 10b
445 #define LBAF_RP_DEGRADED 11b
446 UINT8 Rsvd1
: 6; /* Reserved as of Nvm Express 1.1 Spec */
450 // Identify Namespace Data
454 // NVM Command Set Specific
456 UINT64 Nsze
; /* Namespace Size (total number of blocks in formatted namespace) */
457 UINT64 Ncap
; /* Namespace Capacity (max number of logical blocks) */
458 UINT64 Nuse
; /* Namespace Utilization */
459 UINT8 Nsfeat
; /* Namespace Features */
460 UINT8 Nlbaf
; /* Number of LBA Formats */
461 UINT8 Flbas
; /* Formatted LBA size */
462 UINT8 Mc
; /* Metadata Capabilities */
463 UINT8 Dpc
; /* End-to-end Data Protection capabilities */
464 UINT8 Dps
; /* End-to-end Data Protection Type Settings */
465 UINT8 Nmic
; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
466 UINT8 Rescap
; /* Reservation Capabilities */
467 UINT8 Rsvd1
[88]; /* Reserved as of Nvm Express 1.1 Spec */
468 UINT64 Eui64
; /* IEEE Extended Unique Identifier */
472 NVME_LBAFORMAT LbaFormat
[16];
474 UINT8 Rsvd2
[192]; /* Reserved as of Nvm Express 1.1 Spec */
475 UINT8 VendorData
[3712]; /* Vendor specific data */
476 } NVME_ADMIN_NAMESPACE_DATA
;
479 // RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Spec
482 UINT8 Bppe
; /* Boot Partition Protection Enable */
483 UINT8 Bpl
; /* Boot Partition Lock */
484 UINT8 Nwpac
; /* Namespace Write Protection Authentication Control */
485 UINT8 Rsvd1
[509]; /* Reserved as of Nvm Express 1.4 Spec */
486 } NVME_RPMB_CONFIGURATION_DATA
;
488 #define RPMB_FRAME_STUFF_BYTES 223
491 // RPMB Data Frame as of Nvm Express 1.4 Spec
494 UINT8 Sbakamc
[RPMB_FRAME_STUFF_BYTES
]; /* [222-N:00] Stuff Bytes */
495 /* [222:222-(N-1)] Authentication Key or Message Authentication Code (MAC) */
496 UINT8 Rpmbt
; /* RPMB Target */
498 UINT32 Wcounter
; /* Write Counter */
499 UINT32 Address
; /* Starting address of data to be programmed to or read from the RPMB. */
500 UINT32 Scount
; /* Sector Count */
502 UINT16 Rpmessage
; /* Request/Response Message */
503 // UINT8 *Data; /* Data to be written or read by signed access where M = 512 * Sector Count. */
504 } NVME_RPMB_DATA_FRAME
;
507 // RPMB Device Configuration Block Data Structure.
508 // (ref. NVMe Base spec. v2.0 Figure 460).
511 UINT8 BPPEnable
; /* Boot Partition Protection Enabled */
512 UINT8 BPLock
; /* Boot Partition Lock */
513 UINT8 NameSpaceWrP
; /* Namespace Write Protection */
514 UINT8 Rsvd1
[509]; /* Reserved as of Nvm Express 2.0 Spec */
518 // RPMB Request and Response Message Types.
519 // (ref. NVMe Base spec. v2.0 Figure 461).
521 #define NVME_RPMB_AUTHKEY_PROGRAM 0x0001
522 #define NVME_RPMB_COUNTER_READ 0x0002
523 #define NVME_RPMB_AUTHDATA_WRITE 0x0003
524 #define NVME_RPMB_AUTHDATA_READ 0x0004
525 #define NVME_RPMB_RESULT_READ 0x0005
526 #define NVME_RPMB_DCB_WRITE 0x0006
527 #define NVME_RPMB_DCB_READ 0x0007
528 #define NVME_RPMB_AUTHKEY_PROGRAM_RESPONSE 0x0100
529 #define NVME_RPMB_COUNTER_READ_RESPONSE 0x0200
530 #define NVME_RPMB_AUTHDATA_WRITE_RESPONSE 0x0300
531 #define NVME_RPMB_AUTHDATA_READ_RESPONSE 0x0400
532 #define NVME_RPMB_DCB_WRITE_RESPONSE 0x0600
533 #define NVME_RPMB_DCB_READ_RESPONSE 0x0700
536 // RPMB Operation Result.
537 // (ref. NVMe Base spec. v2.0 Figure 462).
539 #define NVME_RPMB_RESULT_SUCCESS 0x00
540 #define NVME_RPMB_RESULT_GENERAL_FAILURE 0x01
541 #define NVME_RPMB_RESULT_AHTHENTICATION_FAILURE 0x02
542 #define NVME_RPMB_RESULT_COUNTER_FAILURE 0x03
543 #define NVME_RPMB_RESULT_ADDRESS_FAILURE 0x04
544 #define NVME_RPMB_RESULT_WRITE_FAILURE 0x05
545 #define NVME_RPMB_RESULT_READ_FAILURE 0x06
546 #define NVME_RPMB_RESULT_AUTHKEY_NOT_PROGRAMMED 0x07
547 #define NVME_RPMB_RESULT_INVALID_DCB 0x08
550 // Get Log Page - Boot Partition Log Header.
551 // (ref. NVMe Base spec. v2.0 Figure 262).
554 UINT8 LogIdentifier
; /* Log Identifier, shall be set to 15h */
556 UINT32 Bpsz
: 15; /* Boot Partition Size */
558 UINT32 Abpid
: 1; /* Active Boot Partition ID */
560 } NVME_BOOT_PARTITION_HEADER
;
563 // NvmExpress Admin Identify Cmd
571 } NVME_ADMIN_IDENTIFY
;
574 // NvmExpress Admin Create I/O Completion Queue
580 UINT32 Qid
: 16; /* Queue Identifier */
581 UINT32 Qsize
: 16; /* Queue Size */
586 UINT32 Pc
: 1; /* Physically Contiguous */
587 UINT32 Ien
: 1; /* Interrupts Enabled */
588 UINT32 Rsvd1
: 14; /* reserved as of Nvm Express 1.1 Spec */
589 UINT32 Iv
: 16; /* Interrupt Vector for MSI-X or MSI*/
593 // NvmExpress Admin Create I/O Submission Queue
599 UINT32 Qid
: 16; /* Queue Identifier */
600 UINT32 Qsize
: 16; /* Queue Size */
605 UINT32 Pc
: 1; /* Physically Contiguous */
606 UINT32 Qprio
: 2; /* Queue Priority */
607 UINT32 Rsvd1
: 13; /* Reserved as of Nvm Express 1.1 Spec */
608 UINT32 Cqid
: 16; /* Completion Queue ID */
612 // NvmExpress Admin Delete I/O Completion Queue
623 // NvmExpress Admin Delete I/O Submission Queue
634 // NvmExpress Admin Abort Command
640 UINT32 Sqid
: 16; /* Submission Queue identifier */
641 UINT32 Cid
: 16; /* Command Identifier */
645 // NvmExpress Admin Firmware Activate Command
651 UINT32 Fs
: 3; /* Submission Queue identifier */
652 UINT32 Aa
: 2; /* Command Identifier */
654 } NVME_ADMIN_FIRMWARE_ACTIVATE
;
657 // NvmExpress Admin Firmware Image Download Command
663 UINT32 Numd
; /* Number of Dwords */
667 UINT32 Ofst
; /* Offset */
668 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD
;
671 // NvmExpress Admin Get Features Command
677 UINT32 Fid
: 8; /* Feature Identifier */
678 UINT32 Sel
: 3; /* Select */
680 } NVME_ADMIN_GET_FEATURES
;
683 // NvmExpress Admin Get Log Page Command
689 UINT32 Lid
: 8; /* Log Page Identifier */
690 #define LID_ERROR_INFO 0x1
691 #define LID_SMART_INFO 0x2
692 #define LID_FW_SLOT_INFO 0x3
693 #define LID_BP_INFO 0x15
695 UINT32 Numd
: 12; /* Number of Dwords */
696 UINT32 Rsvd2
: 4; /* Reserved as of Nvm Express 1.1 Spec */
697 } NVME_ADMIN_GET_LOG_PAGE
;
700 // NvmExpress Admin Set Features Command
706 UINT32 Fid
: 8; /* Feature Identifier */
708 UINT32 Sv
: 1; /* Save */
709 } NVME_ADMIN_SET_FEATURES
;
712 // NvmExpress Admin Format NVM Command
718 UINT32 Lbaf
: 4; /* LBA Format */
719 UINT32 Ms
: 1; /* Metadata Settings */
720 UINT32 Pi
: 3; /* Protection Information */
721 UINT32 Pil
: 1; /* Protection Information Location */
722 UINT32 Ses
: 3; /* Secure Erase Settings */
724 } NVME_ADMIN_FORMAT_NVM
;
727 // NvmExpress Admin Security Receive Command
734 UINT32 Spsp
: 16; /* SP Specific */
735 UINT32 Secp
: 8; /* Security Protocol */
739 UINT32 Al
; /* Allocation Length */
740 } NVME_ADMIN_SECURITY_RECEIVE
;
743 // NvmExpress Admin Security Send Command
750 UINT32 Spsp
: 16; /* SP Specific */
751 UINT32 Secp
: 8; /* Security Protocol */
755 UINT32 Tl
; /* Transfer Length */
756 } NVME_ADMIN_SECURITY_SEND
;
759 NVME_ADMIN_IDENTIFY Identify
;
760 NVME_ADMIN_CRIOCQ CrIoCq
;
761 NVME_ADMIN_CRIOSQ CrIoSq
;
762 NVME_ADMIN_DEIOCQ DeIoCq
;
763 NVME_ADMIN_DEIOSQ DeIoSq
;
764 NVME_ADMIN_ABORT Abort
;
765 NVME_ADMIN_FIRMWARE_ACTIVATE Activate
;
766 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload
;
767 NVME_ADMIN_GET_FEATURES GetFeatures
;
768 NVME_ADMIN_GET_LOG_PAGE GetLogPage
;
769 NVME_ADMIN_SET_FEATURES SetFeatures
;
770 NVME_ADMIN_FORMAT_NVM FormatNvm
;
771 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive
;
772 NVME_ADMIN_SECURITY_SEND SecuritySend
;
785 NVME_ADMIN_CMD Admin
; // Union of Admin commands
786 NVME_CMD Nvm
; // Union of Nvm commands
795 // CDW 0, Common to all commands
798 UINT8 Fuse
: 2; // Fused Operation
800 UINT8 Psdt
: 1; // PRP or SGL for Data Transfer
801 UINT16 Cid
; // Command Identifier
806 UINT32 Nsid
; // Namespace Identifier
816 UINT64 Mptr
; // Metadata Pointer
821 UINT64 Prp
[2]; // First and second PRP entries
823 NVME_PAYLOAD Payload
;
841 UINT16 Sqhd
; // Submission Queue Head Pointer
842 UINT16 Sqid
; // Submission Queue Identifier
846 UINT16 Cid
; // Command Identifier
847 UINT16 Pt
: 1; // Phase Tag
848 UINT16 Sc
: 8; // Status Code
849 UINT16 Sct
: 3; // Status Code Type
851 UINT16 Mo
: 1; // More
852 UINT16 Dnr
: 1; // Do Not Retry
856 // Nvm Express Admin cmd opcodes
858 #define NVME_ADMIN_DEIOSQ_CMD 0x00
859 #define NVME_ADMIN_CRIOSQ_CMD 0x01
860 #define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02
861 #define NVME_ADMIN_DEIOCQ_CMD 0x04
862 #define NVME_ADMIN_CRIOCQ_CMD 0x05
863 #define NVME_ADMIN_IDENTIFY_CMD 0x06
864 #define NVME_ADMIN_ABORT_CMD 0x08
865 #define NVME_ADMIN_SET_FEATURES_CMD 0x09
866 #define NVME_ADMIN_GET_FEATURES_CMD 0x0A
867 #define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C
868 #define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D
869 #define NVME_ADMIN_FW_COMMIT_CMD 0x10
870 #define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11
871 #define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15
872 #define NVME_ADMIN_FORMAT_NVM_CMD 0x80
873 #define NVME_ADMIN_SECURITY_SEND_CMD 0x81
874 #define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82
876 #define NVME_IO_FLUSH_OPC 0
877 #define NVME_IO_WRITE_OPC 1
878 #define NVME_IO_READ_OPC 2
881 DeleteIOSubmissionQueueOpcode
= NVME_ADMIN_DEIOSQ_CMD
,
882 CreateIOSubmissionQueueOpcode
= NVME_ADMIN_CRIOSQ_CMD
,
883 GetLogPageOpcode
= NVME_ADMIN_GET_LOG_PAGE_CMD
,
884 DeleteIOCompletionQueueOpcode
= NVME_ADMIN_DEIOCQ_CMD
,
885 CreateIOCompletionQueueOpcode
= NVME_ADMIN_CRIOCQ_CMD
,
886 IdentifyOpcode
= NVME_ADMIN_IDENTIFY_CMD
,
887 AbortOpcode
= NVME_ADMIN_ABORT_CMD
,
888 SetFeaturesOpcode
= NVME_ADMIN_SET_FEATURES_CMD
,
889 GetFeaturesOpcode
= NVME_ADMIN_GET_FEATURES_CMD
,
890 AsyncEventRequestOpcode
= NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD
,
891 NamespaceManagementOpcode
= NVME_ADMIN_NAMESACE_MANAGEMENT_CMD
,
892 FirmwareCommitOpcode
= NVME_ADMIN_FW_COMMIT_CMD
,
893 FirmwareImageDownloadOpcode
= NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD
,
894 NamespaceAttachmentOpcode
= NVME_ADMIN_NAMESACE_ATTACHMENT_CMD
,
895 FormatNvmOpcode
= NVME_ADMIN_FORMAT_NVM_CMD
,
896 SecuritySendOpcode
= NVME_ADMIN_SECURITY_SEND_CMD
,
897 SecurityReceiveOpcode
= NVME_ADMIN_SECURITY_RECEIVE_CMD
898 } NVME_ADMIN_COMMAND_OPCODE
;
901 // Controller or Namespace Structure (CNS) field
902 // (ref. spec. v1.1 figure 82).
905 IdentifyNamespaceCns
= 0x0,
906 IdentifyControllerCns
= 0x1,
907 IdentifyActiveNsListCns
= 0x2
908 } NVME_ADMIN_IDENTIFY_CNS
;
912 // (ref. spec. 1.1 figure 60).
915 ActivateActionReplace
= 0x0,
916 ActivateActionReplaceActivate
= 0x1,
917 ActivateActionActivate
= 0x2
918 } NVME_FW_ACTIVATE_ACTION
;
922 // (ref. spec. 1.1 Figure 60).
925 FirmwareSlotCtrlChooses
= 0x0,
933 } NVME_FW_ACTIVATE_SLOT
;
936 // Get Log Page ? Log Page Identifiers
937 // (ref. spec. v1.1 Figure 73).
940 ErrorInfoLogID
= LID_ERROR_INFO
,
941 SmartHealthInfoLogID
= LID_SMART_INFO
,
942 FirmwareSlotInfoLogID
= LID_FW_SLOT_INFO
946 // Get Log Page ? Firmware Slot Information Log
947 // (ref. spec. v1.1 Figure 77).
951 // Indicates the firmware slot from which the actively running firmware revision was loaded.
953 UINT8 ActivelyRunningFwSlot
: 3;
956 // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
958 UINT8 NextActiveFwSlot
: 3;
960 } NVME_ACTIVE_FW_INFO
;
963 // Get Log Page ? Firmware Slot Information Log
964 // (ref. spec. v1.1 Figure 77).
968 // Specifies information about the active firmware revision.
970 NVME_ACTIVE_FW_INFO ActiveFwInfo
;
973 // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
975 CHAR8 FwRevisionSlot
[7][8];
976 UINT8 Reserved2
[448];
977 } NVME_FW_SLOT_INFO_LOG
;
980 // SMART / Health Information (Log Identifier 02h)
981 // (ref. spec. v1.1 5.10.1.2)
985 // This field indicates critical warnings for the state of the controller.
987 UINT8 CriticalWarningAvailableSpare
: 1;
988 UINT8 CriticalWarningTemperature
: 1;
989 UINT8 CriticalWarningReliability
: 1;
990 UINT8 CriticalWarningMediaReadOnly
: 1;
991 UINT8 CriticalWarningVolatileBackup
: 1;
992 UINT8 CriticalWarningReserved
: 3;
994 // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
996 UINT16 CompositeTemp
;
998 // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
1000 UINT8 AvailableSpare
;
1002 // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
1004 UINT8 AvailableSpareThreshold
;
1006 // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
1008 UINT8 PercentageUsed
;
1009 UINT8 Reserved1
[26];
1011 // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
1013 UINT8 DataUnitsRead
[16];
1015 // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
1017 UINT8 DataUnitsWritten
[16];
1019 // Contains the number of read commands completed by the controller.
1021 UINT8 HostReadCommands
[16];
1023 // Contains the number of write commands completed by the controller.
1025 UINT8 HostWriteCommands
[16];
1027 // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
1029 UINT8 ControllerBusyTime
[16];
1031 // Contains the number of power cycles.
1033 UINT8 PowerCycles
[16];
1035 // Contains the number of power-on hours.
1037 UINT8 PowerOnHours
[16];
1039 // Contains the number of unsafe shutdowns.
1041 UINT8 UnsafeShutdowns
[16];
1043 // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
1045 UINT8 MediaAndDataIntegrityErrors
[16];
1047 // Contains the number of Error Information log entries over the life of the controller.
1049 UINT8 NumberErrorInformationLogEntries
[16];
1051 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
1053 UINT32 WarningCompositeTemperatureTime
;
1055 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
1057 UINT32 CriticalCompositeTemperatureTime
;
1059 // Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
1061 UINT16 TemperatureSensor
[8];
1062 UINT8 Reserved2
[296];
1063 } NVME_SMART_HEALTH_INFO_LOG
;