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2 Main PAL API's defined in IPF PAL Spec.
4 Copyright (c) 2006 - 2007, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 // CacheType of PAL_CACHE_FLUSH.
22 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
23 #define PAL_CACHE_FLUSH_DATA_ALL 2
24 #define PAL_CACHE_FLUSH_ALL 3
25 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
29 // Bitmask of Opearation of PAL_CACHE_FLUSH.
31 #define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
32 #define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
36 Flush the instruction or data caches. It is required by IPF.
37 The PAL procedure supports the Static Registers calling
38 convention. It could be called at virtual mode and physical
41 @param Index Index of PAL_CACHE_FLUSH within the
42 list of PAL procedures.
44 @param CacheType Unsigned 64-bit integer indicating
47 @param Operation Formatted bit vector indicating the
48 operation of this call.
50 @param ProgressIndicator Unsigned 64-bit integer specifying
51 the starting position of the flush
54 @return R9 Unsigned 64-bit integer specifying the vector
55 number of the pending interrupt.
57 @return R10 Unsigned 64-bit integer specifying the
58 starting position of the flush operation.
60 @return R11 Unsigned 64-bit integer specifying the vector
61 number of the pending interrupt.
63 @return Status 2 - Call completed without error, but a PMI
64 was taken during the execution of this
67 @return Status 1 - Call has not completed flushing due to
70 @return Status 0 - Call completed without error
72 @return Status -2 - Invalid argument
74 @return Status -3 - Call completed with error
77 #define PAL_CACHE_FLUSH 1
81 // Attributes of PAL_CACHE_CONFIG_INFO1
83 #define PAL_CACHE_ATTR_WT 0
84 #define PAL_CACHE_ATTR_WB 1
87 // PAL_CACHE_CONFIG_INFO1.StoreHint
89 #define PAL_CACHE_STORE_TEMPORAL 0
90 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
93 // PAL_CACHE_CONFIG_INFO1.StoreHint
95 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
96 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
99 // PAL_CACHE_CONFIG_INFO1.StoreHint
101 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
102 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
103 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
106 // Detail the characteristics of a given processor controlled
107 // cache in the cache hierarchy.
110 UINT64 IsUnified
: 1;
111 UINT64 Attributes
: 2;
112 UINT64 Associativity
:8;
115 UINT64 StoreLatency
:8;
118 } PAL_CACHE_INFO_RETURN1
;
121 // Detail the characteristics of a given processor controlled
122 // cache in the cache hierarchy.
126 UINT64 AliasBoundary
:8;
129 } PAL_CACHE_INFO_RETURN2
;
133 Return detailed instruction or data cache information. It is
134 required by IPF. The PAL procedure supports the Static
135 Registers calling convention. It could be called at virtual
136 mode and physical mode.
138 @param Index Index of PAL_CACHE_INFO within the list of
141 @param CacheLevel Unsigned 64-bit integer specifying the
142 level in the cache hierarchy for which
143 information is requested. This value must
144 be between 0 and one less than the value
145 returned in the cache_levels return value
146 from PAL_CACHE_SUMMARY.
148 @param CacheType Unsigned 64-bit integer with a value of 1
149 for instruction cache and 2 for data or
150 unified cache. All other values are
153 @param Reserved Should be 0.
156 @return R9 Detail the characteristics of a given
157 processor controlled cache in the cache
158 hierarchy. See PAL_CACHE_INFO_RETURN1.
160 @return R10 Detail the characteristics of a given
161 processor controlled cache in the cache
162 hierarchy. See PAL_CACHE_INFO_RETURN2.
164 @return R11 Reserved with 0.
167 @return Status 0 - Call completed without error
169 @return Status -2 - Invalid argument
171 @return Status -3 - Call completed with error
174 #define PAL_CACHE_INFO 2
179 // Level of PAL_CACHE_INIT.
181 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
184 // Restrict of PAL_CACHE_INIT.
186 #define PAL_CACHE_INIT_NO_RESTRICT 0
187 #define PAL_CACHE_INIT_RESTRICTED 1
191 Initialize the instruction or data caches. It is required by
192 IPF. The PAL procedure supports the Static Registers calling
193 convention. It could be called at physical mode.
195 @param Index Index of PAL_CACHE_INIT within the list of PAL
198 @param Level Unsigned 64-bit integer containing the level of
199 cache to initialize. If the cache level can be
200 initialized independently, only that level will
201 be initialized. Otherwise
202 implementation-dependent side-effects will
205 @param CacheType Unsigned 64-bit integer with a value of 1 to
206 initialize the instruction cache, 2 to
207 initialize the data cache, or 3 to
208 initialize both. All other values are
211 @param Restrict Unsigned 64-bit integer with a value of 0 or
212 1. All other values are reserved. If
213 restrict is 1 and initializing the specified
214 level and cache_type of the cache would
215 cause side-effects, PAL_CACHE_INIT will
216 return -4 instead of initializing the cache.
219 @return Status 0 - Call completed without error
221 @return Status -2 - Invalid argument
223 @return Status -3 - Call completed with error.
225 @return Status -4 - Call could not initialize the specified
226 level and cache_type of the cache without
227 side-effects and restrict was 1.
230 #define PAL_CACHE_INIT 3
234 // PAL_CACHE_PROTECTION.Method.
236 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
237 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
238 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
239 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
244 // PAL_CACHE_PROTECTION.TagOrData.
246 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
247 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
248 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
249 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
252 // 32-bit protection information structures.
261 } PAL_CACHE_PROTECTION
;
265 Return instruction or data cache protection information. It is
266 required by IPF. The PAL procedure supports the Static
267 Registers calling convention. It could be called at physical
268 mode and Virtual mode.
270 @param Index Index of PAL_CACHE_PROT_INFO within the list of
273 @param CacheLevel Unsigned 64-bit integer specifying the level
274 in the cache hierarchy for which information
275 is requested. This value must be between 0
276 and one less than the value returned in the
277 cache_levels return value from
280 @param CacheType Unsigned 64-bit integer with a value of 1
281 for instruction cache and 2 for data or
282 unified cache. All other values are
285 @return R9 Detail the characteristics of a given
286 processor controlled cache in the cache
287 hierarchy. See PAL_CACHE_PROTECTION[0..1].
289 @return R10 Detail the characteristics of a given
290 processor controlled cache in the cache
291 hierarchy. See PAL_CACHE_PROTECTION[2..3].
293 @return R11 Detail the characteristics of a given
294 processor controlled cache in the cache
295 hierarchy. See PAL_CACHE_PROTECTION[4..5].
298 @return Status 0 - Call completed without error
300 @return Status -2 - Invalid argument
302 @return Status -3 - Call completed with error.
305 #define PAL_CACHE_PROT_INFO 38
320 Returns information on which logical processors share caches.
323 @param CallingConvention Static Registers
325 @param Mode Physical/Virtual
328 #define PAL_CACHE_SHARED_INFO 43
333 Return a summary of the cache hierarchy. It is required by
336 @param CallingConvention Static Registers
338 @param Mode Physical/Virtual
341 #define PAL_CACHE_SUMMARY 4
345 Return a list of supported memory attributes.. It is required
348 @param CallingConvention Static Registers
350 @param Mode Physical/Virtual
353 #define PAL_MEM_ATTRIB 5
357 Used in architected sequence to transition pages from a
358 cacheable, speculative attribute to an uncacheable attribute.
359 It is required by IPF.
361 @param CallingConvention Static Registers
363 @param Mode Physical/Virtual
366 #define PAL_PREFETCH_VISIBILITY 41
370 Return information needed for ptc.e instruction to purge
371 entire TC. It is required by IPF.
373 @param CallingConvention Static Registers
375 @param Mode Physical/Virtual
378 #define PAL_PTCE_INFO 6
382 Return detailed information about virtual memory features
383 supported in the processor. It is required by IPF.
385 @param CallingConvention Static Registers
387 @param Mode Physical/Virtual
390 #define PAL_VM_INFO 7
395 Return virtual memory TC and hardware walker page sizes
396 supported in the processor. It is required by IPF.
398 @param CallingConvention Static Registers
403 #define PAL_VM_PAGE_SIZE 34
407 Return summary information about virtual memory features
408 supported in the processor. It is required by IPF.
410 @param CallingConvention Static Registers
412 @param Mode Physical/Virtual
415 #define PAL_VM_SUMMARY 8
419 Read contents of a translation register. It is required by
422 @param CallingConvention Stacked Register
427 #define PAL_VM_TR_READ 261
431 Return configurable processor bus interface features and their
432 current settings. It is required by IPF.
434 @param CallingConvention Static Registers
439 #define PAL_BUS_GET_FEATURES 9
444 Enable or disable configurable features in processor bus
445 interface. It is required by IPF.
447 @param CallingConvention Static Registers
452 #define PAL_BUS_SET_FEATURES 10
457 Return the number of instruction and data breakpoint
458 registers. It is required by IPF.
460 @param CallingConvention Static Registers
462 @param Mode Physical/Virtual
465 #define PAL_DEBUG_INFO 11
469 Return the fixed component of a processor¡¯s directed address.
470 It is required by IPF.
472 @param CallingConvention Static Registers
474 @param Mode Physical/Virtual
477 #define PAL_FIXED_ADDR 12
481 Return the frequency of the output clock for use by the
482 platform, if generated by the processor. It is optinal.
484 @param CallingConvention Static Registers
486 @param Mode Physical/Virtual
489 #define PAL_FREQ_BASE 13
493 Return ratio of processor, bus, and interval time counter to
494 processor input clock or output clock for platform use, if
495 generated by the processor. It is required by IPF.
497 @param CallingConvention Static Registers
499 @param Mode Physical/Virtual
502 #define PAL_FREQ_RATIOS 14
506 Return information on which logical processors map to a
507 physical processor die. It is optinal.
509 @param CallingConvention Static Registers
511 @param Mode Physical/Virtual
514 #define PAL_LOGICAL_TO_PHYSICAL 42
518 Return the number and type of performance monitors. It is
521 @param CallingConvention Static Registers
523 @param Mode Physical/Virtual
526 #define PAL_PERF_MON_INFO 15
530 Specify processor interrupt block address and I/O port space
531 address. It is required by IPF.
533 @param CallingConvention Static Registers
535 @param Mode Physical/Virtual
538 #define PAL_PLATFORM_ADDR 16
543 Return configurable processor features and their current
544 setting. It is required by IPF.
546 @param CallingConvention Static Registers
548 @param Mode Physical/Virtual
551 #define PAL_PROC_GET_FEATURES 17
556 Enable or disable configurable processor features. It is
559 @param CallingConvention Static Registers
564 #define PAL_PROC_SET_FEATURES 18
568 Return AR and CR register information. It is required by IPF.
570 @param CallingConvention Static Registers
572 @param Mode Physical/Virtual
575 #define PAL_REGISTER_INFO 39
579 Return RSE information. It is required by
582 @param CallingConvention Static Registers
584 @param Mode Physical/Virtual
587 #define PAL_RSE_INFO 19
591 Return version of PAL code. It is required by IPF.
593 @param CallingConvention Static Registers
595 @param Mode Physical/Virtual
598 #define PAL_VERSION 20
602 Clear all error information from processor error logging
603 registers. It is required by IPF.
605 @param CallingConvention Static Registers
607 @param Mode Physical/Virtual
610 #define PAL_MC_CLEAR_LOG 21
614 Ensure that all operations that could cause an MCA have
615 completed. It is required by IPF.
617 @param CallingConvention Static Registers
619 @param Mode Physical/Virtual
622 #define PAL_MC_DRAIN 22
626 Return Processor Dynamic State for logging by SAL. It is
629 @param CallingConvention Static Registers
634 #define PAL_MC_DYNAMIC_STATE 24
638 Return Processor Machine Check Information and Processor
639 Static State for logging by SAL. It is required by IPF.
641 @param CallingConvention Static Registers
643 @param Mode Physical/Virtual
646 #define PAL_MC_ERROR_INFO 25 Req. Static Both
650 Set/Reset Expected Machine Check Indicator. It is required by
653 @param CallingConvention Static Registers
658 #define PAL_MC_EXPECTED 23
662 Register min-state save area with PAL for machine checks and
663 inits. It is required by IPF.
665 @param CallingConvention Static Registers
670 #define PAL_MC_REGISTER_MEM 27
674 Restore minimal architected state and return to interrupted
675 process. It is required by IPF.
677 @param CallingConvention Static Registers
682 #define PAL_MC_RESUME 26
686 Enter the low-power HALT state or an implementation-dependent
687 low-power state. It is optinal.
689 @param CallingConvention Static Registers
699 Return the low power capabilities of the processor. It is
702 @param CallingConvention Stacked Register
704 @param Mode Physical/Virtual
707 #define PAL_HALT_INFO 257
712 Enter the low power LIGHT HALT state. It is required by
715 @param CallingConvention Static Registers
717 @param Mode Physical/Virtual
720 #define PAL_HALT_LIGHT 29
724 Initialize tags and data of a cache line for processor
725 testing. It is required by IPF.
727 @param CallingConvention Static Registers
732 #define PAL_CACHE_LINE_INIT 31
736 Read tag and data of a cache line for diagnostic testing. It
739 @param CallingConvention Satcked Register
744 #define PAL_CACHE_READ 259
748 Write tag and data of a cache for diagnostic testing. It is
751 @param CallingConvention Satcked Registers
756 #define PAL_CACHE_WRITE 260
760 Returns alignment and size requirements needed for the memory
761 buffer passed to the PAL_TEST_PROC procedure as well as
762 information on self-test control words for the processor self
763 tests. It is required by IPF.
765 @param CallingConvention Static Registers
770 #define PAL_TEST_INFO 37
774 Perform late processor self test. It is required by
777 @param CallingConvention Stacked Registers
782 #define PAL_TEST_PROC 258
786 Return information needed to relocate PAL procedures and PAL
787 PMI code to memory. It is required by IPF.
789 @param CallingConvention Static Registers
794 #define PAL_COPY_INFO 30
798 Relocate PAL procedures and PAL PMI code to memory. It is
801 @param CallingConvention Stacked Registers
806 #define PAL_COPY_PAL 256
810 Enter IA-32 System environment. It is optional.
812 @param CallingConvention Static Registers
817 #define PAL_ENTER_IA_32_ENV 33
821 Register PMI memory entrypoints with processor. It is required
824 @param CallingConvention Static Registers
829 #define PAL_PMI_ENTRYPOINT 32