2 Main PAL API's defined in Intel Itanium Architecture Software Developer\92s Manual.
4 Copyright (c) 2006 - 2008, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
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10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #define PAL_SUCCESS 0x0
21 // CacheType of PAL_CACHE_FLUSH.
23 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
24 #define PAL_CACHE_FLUSH_DATA_ALL 2
25 #define PAL_CACHE_FLUSH_ALL 3
26 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
30 // Bitmask of Opearation of PAL_CACHE_FLUSH.
32 #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0
33 #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0
34 #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1
35 #define PAL_CACHE_FLUSH_NO_INTERRUPT 0
38 PAL Procedure - PAL_CACHE_FLUSH.
40 Flush the instruction or data caches. It is required by IPF.
41 The PAL procedure supports the Static Registers calling
42 convention. It could be called at virtual mode and physical
45 @param Index Index of PAL_CACHE_FLUSH within the
46 list of PAL procedures.
47 @param CacheType Unsigned 64-bit integer indicating
49 @param Operation Formatted bit vector indicating the
50 operation of this call.
51 @param ProgressIndicator Unsigned 64-bit integer specifying
52 the starting position of the flush
55 @retval 2 Call completed without error, but a PMI
56 was taken during the execution of this
58 @retval 1 Call has not completed flushing due to
60 @retval 0 Call completed without error
61 @retval -2 Invalid argument
62 @retval -3 Call completed with error
64 @return R9 Unsigned 64-bit integer specifying the vector
65 number of the pending interrupt.
66 @return R10 Unsigned 64-bit integer specifying the
67 starting position of the flush operation.
68 @return R11 Unsigned 64-bit integer specifying the vector
69 number of the pending interrupt.
72 #define PAL_CACHE_FLUSH 1
76 // Attributes of PAL_CACHE_CONFIG_INFO1
78 #define PAL_CACHE_ATTR_WT 0
79 #define PAL_CACHE_ATTR_WB 1
82 // PAL_CACHE_CONFIG_INFO1.StoreHint
84 #define PAL_CACHE_STORE_TEMPORAL 0
85 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
88 // PAL_CACHE_CONFIG_INFO1.StoreHint
90 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
91 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
94 // PAL_CACHE_CONFIG_INFO1.StoreHint
96 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
97 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
98 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
101 // Detail the characteristics of a given processor controlled
102 // cache in the cache hierarchy.
105 UINT64 IsUnified
: 1;
106 UINT64 Attributes
: 2;
107 UINT64 Associativity
:8;
110 UINT64 StoreLatency
:8;
113 } PAL_CACHE_INFO_RETURN1
;
116 // Detail the characteristics of a given processor controlled
117 // cache in the cache hierarchy.
121 UINT64 AliasBoundary
:8;
124 } PAL_CACHE_INFO_RETURN2
;
127 PAL Procedure - PAL_CACHE_INFO.
129 Return detailed instruction or data cache information. It is
130 required by IPF. The PAL procedure supports the Static
131 Registers calling convention. It could be called at virtual
132 mode and physical mode.
134 @param Index Index of PAL_CACHE_INFO within the list of
136 @param CacheLevel Unsigned 64-bit integer specifying the
137 level in the cache hierarchy for which
138 information is requested. This value must
139 be between 0 and one less than the value
140 returned in the cache_levels return value
141 from PAL_CACHE_SUMMARY.
142 @param CacheType Unsigned 64-bit integer with a value of 1
143 for instruction cache and 2 for data or
144 unified cache. All other values are
146 @param Reserved Should be 0.
148 @retval 0 Call completed without error
149 @retval -2 Invalid argument
150 @retval -3 Call completed with error
152 @return R9 Detail the characteristics of a given
153 processor controlled cache in the cache
154 hierarchy. See PAL_CACHE_INFO_RETURN1.
155 @return R10 Detail the characteristics of a given
156 processor controlled cache in the cache
157 hierarchy. See PAL_CACHE_INFO_RETURN2.
158 @return R11 Reserved with 0.
161 #define PAL_CACHE_INFO 2
166 // Level of PAL_CACHE_INIT.
168 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
173 #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1
174 #define PAL_CACHE_INIT_TYPE_DATA 0x2
175 #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3
178 // Restrict of PAL_CACHE_INIT.
180 #define PAL_CACHE_INIT_NO_RESTRICT 0
181 #define PAL_CACHE_INIT_RESTRICTED 1
184 PAL Procedure - PAL_CACHE_INIT.
186 Initialize the instruction or data caches. It is required by
187 IPF. The PAL procedure supports the Static Registers calling
188 convention. It could be called at physical mode.
190 @param Index Index of PAL_CACHE_INIT within the list of PAL
192 @param Level Unsigned 64-bit integer containing the level of
193 cache to initialize. If the cache level can be
194 initialized independently, only that level will
195 be initialized. Otherwise
196 implementation-dependent side-effects will
198 @param CacheType Unsigned 64-bit integer with a value of 1 to
199 initialize the instruction cache, 2 to
200 initialize the data cache, or 3 to
201 initialize both. All other values are
203 @param Restrict Unsigned 64-bit integer with a value of 0 or
204 1. All other values are reserved. If
205 restrict is 1 and initializing the specified
206 level and cache_type of the cache would
207 cause side-effects, PAL_CACHE_INIT will
208 return -4 instead of initializing the cache.
210 @retval 0 Call completed without error
211 @retval -2 Invalid argument
212 @retval -3 Call completed with error.
213 @retval -4 Call could not initialize the specified
214 level and cache_type of the cache without
215 side-effects and restrict was 1.
218 #define PAL_CACHE_INIT 3
222 // PAL_CACHE_PROTECTION.Method.
224 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
225 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
226 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
227 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
232 // PAL_CACHE_PROTECTION.TagOrData.
234 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
235 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
236 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
237 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
240 // 32-bit protection information structures.
249 } PAL_CACHE_PROTECTION
;
252 PAL Procedure - PAL_CACHE_PROT_INFO.
254 Return instruction or data cache protection information. It is
255 required by IPF. The PAL procedure supports the Static
256 Registers calling convention. It could be called at physical
257 mode and Virtual mode.
259 @param Index Index of PAL_CACHE_PROT_INFO within the list of
261 @param CacheLevel Unsigned 64-bit integer specifying the level
262 in the cache hierarchy for which information
263 is requested. This value must be between 0
264 and one less than the value returned in the
265 cache_levels return value from
267 @param CacheType Unsigned 64-bit integer with a value of 1
268 for instruction cache and 2 for data or
269 unified cache. All other values are
272 @retval 0 Call completed without error
273 @retval -2 Invalid argument
274 @retval -3 Call completed with error.
276 @return R9 Detail the characteristics of a given
277 processor controlled cache in the cache
278 hierarchy. See PAL_CACHE_PROTECTION[0..1].
279 @return R10 Detail the characteristics of a given
280 processor controlled cache in the cache
281 hierarchy. See PAL_CACHE_PROTECTION[2..3].
282 @return R11 Detail the characteristics of a given
283 processor controlled cache in the cache
284 hierarchy. See PAL_CACHE_PROTECTION[4..5].
287 #define PAL_CACHE_PROT_INFO 38
291 @param ThreadId The thread identifier of the logical
292 processor for which information is being
293 returned. This value will be unique on a per
296 @param CoreId The core identifier of the logical processor
297 for which information is being returned.
298 This value will be unique on a per physical
299 processor package basis.
303 UINT64 ThreadId
: 16;
304 UINT64 Reserved1
: 16;
306 UINT64 Reserved2
: 16;
307 } PAL_PCOC_N_CACHE_INFO1
;
311 @param LogicalAddress Logical address: geographical address
312 of the logical processor for which
313 information is being returned. This is
314 the same value that is returned by the
315 PAL_FIXED_ADDR procedure when it is
316 called on the logical processor.
320 UINT64 LogicalAddress
: 16;
321 UINT64 Reserved1
: 16;
322 UINT64 Reserved2
: 32;
323 } PAL_PCOC_N_CACHE_INFO2
;
326 PAL Procedure - PAL_CACHE_SHARED_INFO.
328 Returns information on which logical processors share caches.
329 It is optional. The PAL procedure supports the Static
330 Registers calling convention. It could be called at physical
331 mode and Virtual mode.
333 @param Index Index of PAL_CACHE_SHARED_INFO within the list
335 @param CacheLevel Unsigned 64-bit integer specifying the
336 level in the cache hierarchy for which
337 information is requested. This value must
338 be between 0 and one less than the value
339 returned in the cache_levels return value
340 from PAL_CACHE_SUMMARY.
341 @param CacheType Unsigned 64-bit integer with a value of 1
342 for instruction cache and 2 for data or
343 unified cache. All other values are
345 @param ProcNumber Unsigned 64-bit integer that specifies for
346 which logical processor information is
347 being requested. This input argument must
348 be zero for the first call to this
349 procedure and can be a maximum value of
350 one less than the number of logical
351 processors sharing this cache, which is
352 returned by the num_shared return value.
354 @retval 0 Call completed without error
355 @retval -1 Unimplemented procedure
356 @retval -2 Invalid argument
357 @retval -3 Call completed with error.
359 @return R9 Unsigned integer that returns the number of
360 logical processors that share the processor
361 cache level and type, for which information was
363 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
364 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
367 #define PAL_CACHE_SHARED_INFO 43
371 PAL Procedure - PAL_CACHE_SUMMARY.
373 Return a summary of the cache hierarchy. It is required by
374 IPF. The PAL procedure supports the Static Registers calling
375 convention. It could be called at physical mode and Virtual
378 @param Index Index of PAL_CACHE_SUMMARY within the list of
381 @retval 0 Call completed without error
382 @retval -2 Invalid argument
383 @retval -3 Call completed with error.
385 @return R9 CacheLevels Unsigned 64-bit integer denoting the
386 number of levels of cache
387 implemented by the processor.
388 Strictly, this is the number of
389 levels for which the cache
390 controller is integrated into the
391 processor (the cache SRAMs may be
392 external to the processor).
393 @return R10 UniqueCaches Unsigned 64-bit integer denoting the
394 number of unique caches implemented
395 by the processor. This has a maximum
396 of 2*cache_levels, but may be less
397 if any of the levels in the cache
398 hierarchy are unified caches or do
399 not have both instruction and data
403 #define PAL_CACHE_SUMMARY 4
407 // Virtual Memory Attributes implemented by processor.
409 #define PAL_MEMORY_ATTR_WB 0
410 #define PAL_MEMORY_ATTR_WC 6
411 #define PAL_MEMORY_ATTR_UC 4
412 #define PAL_MEMORY_ATTR_UCE 5
413 #define PAL_MEMORY_ATTR_NATPAGE 7
416 PAL Procedure - PAL_MEM_ATTRIB.
418 Return a list of supported memory attributes.. It is required
419 by IPF. The PAL procedure supports the Static Registers calling
420 convention. It could be called at physical mode and Virtual
423 @param Index Index of PAL_MEM_ATTRIB within the list of PAL
426 @retval 0 Call completed without error
427 @retval -2 Invalid argument
428 @retval -3 Call completed with error.
430 @return R9 Attributes 8-bit vector of memory attributes
431 implemented by processor. See Virtual
432 Memory Attributes above.
436 #define PAL_MEM_ATTRIB 5
439 PAL Procedure - PAL_PREFETCH_VISIBILITY.
441 Used in architected sequence to transition pages from a
442 cacheable, speculative attribute to an uncacheable attribute.
443 It is required by IPF. The PAL procedure supports the Static
444 Registers calling convention. It could be called at physical
445 mode and Virtual mode.
447 @param Index Index of PAL_PREFETCH_VISIBILITY within the list
449 @param TransitionType Unsigned integer specifying the type
450 of memory attribute transition that is
453 @retval 1 Call completed without error; this
454 call is not necessary on remote
456 @retval 0 Call completed without error
457 @retval -2 Invalid argument
458 @retval -3 Call completed with error.
461 #define PAL_PREFETCH_VISIBILITY 41
464 PAL Procedure - PAL_PTCE_INFO.
466 Return information needed for ptc.e instruction to purge
467 entire TC. It is required by IPF. The PAL procedure supports
468 the Static Registers calling convention. It could be called at
469 physical mode and Virtual mode.
471 @param Index Index of PAL_PTCE_INFO within the list
474 @retval 0 Call completed without error
475 @retval -2 Invalid argument
476 @retval -3 Call completed with error.
478 @return R9 Unsigned 64-bit integer denoting the beginning
479 address to be used by the first PTCE instruction
481 @return R10 Two unsigned 32-bit integers denoting the loop
482 counts of the outer (loop 1) and inner (loop 2)
483 purge loops. count1 (loop 1) is contained in bits
484 63:32 of the parameter, and count2 (loop 2) is
485 contained in bits 31:0 of the parameter.
486 @return R11 Two unsigned 32-bit integers denoting the loop
487 strides of the outer (loop 1) and inner (loop 2)
488 purge loops. stride1 (loop 1) is contained in bits
489 63:32 of the parameter, and stride2 (loop 2) is
490 contained in bits 31:0 of the parameter.
493 #define PAL_PTCE_INFO 6
499 @param NumberSets Unsigned 8-bit integer denoting the number
500 of hash sets for the specified level
501 (1=fully associative)
503 @param NumberWays Unsigned 8-bit integer denoting the
504 associativity of the specified level
507 @param NumberEntries Unsigned 16-bit integer denoting the
508 number of entries in the specified TC.
511 @param PageSizeIsOptimized Flag denoting whether the
512 specified level is optimized for
513 the region's preferred page size
514 (1=optimized) tc_pages indicates
515 which page sizes are usable by
516 this translation cache.
518 @param TcIsUnified Flag denoting whether the specified TC is
521 @param EntriesReduction Flag denoting whether installed
522 translation registers will reduce
523 the number of entries within the
530 UINT64 NumberEntries
:16;
531 UINT64 PageSizeIsOptimized
:1;
532 UINT64 TcIsUnified
:1;
533 UINT64 EntriesReduction
:1;
537 PAL Procedure - PAL_VM_INFO.
539 Return detailed information about virtual memory features
540 supported in the processor. It is required by IPF. The PAL
541 procedure supports the Static Registers calling convention. It
542 could be called at physical mode and Virtual mode.
544 @param Index Index of PAL_VM_INFO within the list
546 @param TcLevel Unsigned 64-bit integer specifying the level
547 in the TLB hierarchy for which information is
548 required. This value must be between 0 and one
549 less than the value returned in the
550 vm_info_1.num_tc_levels return value from
552 @param TcType Unsigned 64-bit integer with a value of 1 for
553 instruction translation cache and 2 for data
554 or unified translation cache. All other values
557 @retval 0 Call completed without error
558 @retval -2 Invalid argument
559 @retval -3 Call completed with error.
561 @return R9 8-byte formatted value returning information
562 about the specified TC. See PAL_TC_INFO above.
563 @return R10 64-bit vector containing a bit for each page
564 size supported in the specified TC, where bit
565 position n indicates a page size of 2**n.
568 #define PAL_VM_INFO 7
572 PAL Procedure - PAL_VM_PAGE_SIZE.
574 Return virtual memory TC and hardware walker page sizes
575 supported in the processor. It is required by IPF. The PAL
576 procedure supports the Static Registers calling convention. It
577 could be called at physical mode and Virtual mode.
579 @param Index Index of PAL_VM_PAGE_SIZE within the list
582 @retval 0 Call completed without error
583 @retval -2 Invalid argument
584 @retval -3 Call completed with error.
586 @return R9 64-bit vector containing a bit for each
587 architected page size that is supported for
588 TLB insertions and region registers.
589 @return R10 64-bit vector containing a bit for each
590 architected page size supported for TLB purge
594 #define PAL_VM_PAGE_SIZE 34
598 @param WalkerPresent 1-bit flag indicating whether a hardware
599 TLB walker is implemented (1 = walker
602 @param WidthOfPhysicalAddress Unsigned 7-bit integer
603 denoting the number of bits of
604 physical address implemented.
606 @param WidthOfKey Unsigned 8-bit integer denoting the number
607 of bits mplemented in the PKR.key field.
609 @param MaxPkrIndex Unsigned 8-bit integer denoting the
610 maximum PKR index (number of PKRs-1).
612 @param HashTagId Unsigned 8-bit integer which uniquely
613 identifies the processor hash and tag
616 @param MaxDtrIndex Unsigned 8 bit integer denoting the
617 maximum data translation register index
618 (number of dtr entries - 1).
620 @param MaxItrIndex Unsigned 8 bit integer denoting the
621 maximum instruction translation register
622 index (number of itr entries - 1).
624 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the
625 number of unique TCs implemented.
629 @param NumberOfTcLevels Unsigned 8-bit integer denoting the
634 UINT64 WalkerPresent
:1;
635 UINT64 WidthOfPhysicalAddress
: 7;
637 UINT64 MaxPkrIndex
:8;
639 UINT64 MaxDtrIndex
:8;
640 UINT64 MaxItrIndex
:8;
641 UINT64 NumberOfUniqueTc
:8;
642 UINT64 NumberOfTcLevels
:8;
647 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting
648 is the total number of virtual
651 @param WidthOfRid Unsigned 8-bit integer denoting the number
652 of bits implemented in the RR.rid field.
654 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the
655 maximum number of concurrent outstanding
656 TLB purges allowed by the processor. A
657 value of 0 indicates one outstanding
658 purge allowed. A value of 216-1
659 indicates no limit on outstanding
660 purges. All other values indicate the
661 actual number of concurrent outstanding
666 UINT64 WidthOfVirtualAddress
:8;
668 UINT64 MaxPurgedTlbs
:16;
673 PAL Procedure - PAL_VM_SUMMARY.
675 Return summary information about virtual memory features
676 supported in the processor. It is required by IPF. The PAL
677 procedure supports the Static Registers calling convention. It
678 could be called at physical mode and Virtual mode.
680 @param Index Index of PAL_VM_SUMMARY within the list
683 @retval 0 Call completed without error
684 @retval -2 Invalid argument
685 @retval -3 Call completed with error.
687 @return R9 8-byte formatted value returning global virtual
688 memory information. See PAL_VM_INFO1 above.
689 @return R10 8-byte formatted value returning global virtual
690 memory information. See PAL_VM_INFO2 above.
693 #define PAL_VM_SUMMARY 8
697 // Bit mask of TR_valid flag.
699 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
700 #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
701 #define PAL_TR_DIRTY_IS_VALID BIT2
702 #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
706 PAL Procedure - PAL_VM_TR_READ.
708 Read contents of a translation register. It is required by
709 IPF. The PAL procedure supports the Stacked Register calling
710 convention. It could be called at physical mode.
712 @param Index Index of PAL_VM_TR_READ within the list
714 @param RegNumber Unsigned 64-bit number denoting which TR to
716 @param TrType Unsigned 64-bit number denoting whether to
717 read an ITR (0) or DTR (1). All other values
719 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
720 which translation data is returned.
722 @retval 0 Call completed without error
723 @retval -2 Invalid argument
724 @retval -3 Call completed with error.
726 @return R9 Formatted bit vector denoting which fields are
727 valid. See TR_valid above.
730 #define PAL_VM_TR_READ 261
736 // Bit Mask of Processor Bus Fesatures .
741 When 0, bus data errors are detected and single bit errors are
742 corrected. When 1, no error detection or correction is done.
745 #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
750 When 0, bus address errors are signalled on the bus. When 1,
751 no bus errors are signalled on the bus. If Disable Bus Address
752 Error Checking is 1, this bit is ignored.
755 #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
762 When 0, bus errors are detected, single bit errors are
763 corrected., and a CMCI or MCA is generated internally to the
764 processor. When 1, no bus address errors are detected or
768 #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
773 When 0, bus protocol errors (BINIT#) are signaled by the
774 processor on the bus. When 1, bus protocol errors (BINIT#) are
775 not signaled on the bus. If Disable Bus Initialization Event
776 Checking is 1, this bit is ignored.
779 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
784 When 0, bus protocol errors (BINIT#) are detected and sampled
785 and an MCA is generated internally to the processor. When 1,
786 the processor will ignore bus protocol error conditions
790 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
796 When 0, BERR# is signalled if a bus error is detected. When 1,
797 bus errors are not signalled on the bus.
800 #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
807 When 0, BERR# is signalled when internal processor requestor
808 initiated bus errors are detected. When 1, internal requester
809 bus errors are not signalled on the bus.
812 #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
817 When 0, the processor takes an MCA if BERR# is asserted. When
818 1, the processor ignores the BERR# signal.
821 #define PAL_BUS_DISABLE_ERROR_CHECK BIT56
826 When 0, the processor asserts BINIT# if it detects a parity
827 error on the signals which identify the transactions to which
828 this is a response. When 1, the processor ignores parity on
832 #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
837 When 0, the in-order transaction queue is limited only by the
838 number of hardware entries. When 1, the processor's in-order
839 transactions queue is limited to one entry.
842 #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
846 Enable a bus cache line replacement transaction when a cache
847 line in the exclusive state is replaced from the highest level
848 processor cache and is not present in the lower level processor
849 caches. When 0, no bus cache line replacement transaction will
850 be seen on the bus. When 1, bus cache line replacement
851 transactions will be seen on the bus when the above condition is
855 #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
860 Enable a bus cache line replacement transaction when a cache
861 line in the shared or exclusive state is replaced from the
862 highest level processor cache and is not present in the lower
863 level processor caches.
864 When 0, no bus cache line replacement transaction will be seen
865 on the bus. When 1, bus cache line replacement transactions
866 will be seen on the bus when the above condition is detected.
869 #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
875 When 0, the data bus is configured at the 2x data transfer
876 rate.When 1, the data bus is configured at the 1x data
877 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
878 processor executes locked transactions atomically. When 1, the
879 processor masks the bus lock signal and executes locked
880 transactions as a non-atomic series of transactions.
883 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
887 When 0, the processor will deassert bus request when finished
888 with each transaction. When 1, the processor will continue to
889 assert bus request after it has finished, if it was the last
890 agent to own the bus and if there are no other pending
894 #define PAL_BUS_REQUEST_BUS_PARKING BIT29
898 PAL Procedure - PAL_BUS_GET_FEATURES.
900 Return configurable processor bus interface features and their
901 current settings. It is required by IPF. The PAL procedure
902 supports the Stacked Register calling convention. It could be
903 called at physical mode.
905 @param Index Index of PAL_BUS_GET_FEATURES within the list
908 @retval 0 Call completed without error
909 @retval -2 Invalid argument
910 @retval -3 Call completed with error.
912 @return R9 64-bit vector of features implemented.
913 (1=implemented, 0=not implemented)
914 @return R10 64-bit vector of current feature settings.
915 @return R11 64-bit vector of features controllable by
916 software. (1=controllable, 0= not controllable)
919 #define PAL_BUS_GET_FEATURES 9
922 PAL Procedure - PAL_BUS_SET_FEATURES.
924 Enable or disable configurable features in processor bus
925 interface. It is required by IPF. It is required by IPF. The PAL procedure
926 supports the Static Registers calling convention. It could be
927 called at physical mode.
929 @param Index Index of PAL_BUS_SET_FEATURES within the list
931 @param FeatureSelect 64-bit vector denoting desired state of
932 each feature (1=select, 0=non-select).
934 @retval 0 Call completed without error
935 @retval -2 Invalid argument
936 @retval -3 Call completed with error.
939 #define PAL_BUS_SET_FEATURES 10
943 PAL Procedure - PAL_DEBUG_INFO.
945 Return the number of instruction and data breakpoint
946 registers. It is required by IPF. It is required by IPF. The
947 PAL procedure supports the Static Registers calling
948 convention. It could be called at physical mode and virtual
951 @param Index Index of PAL_DEBUG_INFO within the list of PAL
954 @retval 0 Call completed without error
955 @retval -2 Invalid argument
956 @retval -3 Call completed with error.
958 @return R9 Unsigned 64-bit integer denoting the number of
959 pairs of instruction debug registers implemented
961 @return R10 Unsigned 64-bit integer denoting the number of
962 pairs of data debug registers implemented by the
966 #define PAL_DEBUG_INFO 11
969 PAL Procedure - PAL_FIXED_ADDR.
971 Return the fixed component of a processor's directed address.
972 It is required by IPF. It is required by IPF. The PAL
973 procedure supports the Static Registers calling convention. It
974 could be called at physical mode and virtual mode.
976 @param Index Index of PAL_FIXED_ADDR within the list of PAL
979 @retval 0 Call completed without error
980 @retval -2 Invalid argument
981 @retval -3 Call completed with error.
983 @return R9 Fixed geographical address of this processor.
986 #define PAL_FIXED_ADDR 12
989 PAL Procedure - PAL_FREQ_BASE.
991 Return the frequency of the output clock for use by the
992 platform, if generated by the processor. It is optinal. The
993 PAL procedure supports the Static Registers calling
994 convention. It could be called at physical mode and virtual
997 @param Index Index of PAL_FREQ_BASE within the list of PAL
1000 @retval 0 Call completed without error
1001 @retval -1 Unimplemented procedure
1002 @retval -2 Invalid argument
1003 @retval -3 Call completed with error.
1005 @return R9 Base frequency of the platform if generated by the
1009 #define PAL_FREQ_BASE 13
1013 PAL Procedure - PAL_FREQ_RATIOS.
1015 Return ratio of processor, bus, and interval time counter to
1016 processor input clock or output clock for platform use, if
1017 generated by the processor. It is required by IPF. The PAL
1018 procedure supports the Static Registers calling convention. It
1019 could be called at physical mode and virtual mode.
1021 @param Index Index of PAL_FREQ_RATIOS within the list of PAL
1024 @retval 0 Call completed without error
1025 @retval -2 Invalid argument
1026 @retval -3 Call completed with error.
1028 @return R9 Ratio of the processor frequency to the input
1029 clock of the processor, if the platform clock is
1030 generated externally or to the output clock to the
1031 platform, if the platform clock is generated by
1033 @return R10 Ratio of the bus frequency to the input clock of
1034 the processor, if the platform clock is generated
1035 externally or to the output clock to the platform,
1036 if the platform clock is generated by the
1038 @return R11 Ratio of the interval timer counter rate to input
1039 clock of the processor, if the platform clock is
1040 generated externally or to the output clock to the
1041 platform, if the platform clock is generated by
1045 #define PAL_FREQ_RATIOS 14
1049 @param NumberOfLogicalProcessors Total number of logical
1050 processors on this physical
1051 processor package that are
1054 @param ThreadsPerCore Number of threads per core.
1056 @param CoresPerProcessor Total number of cores on this
1057 physical processor package.
1059 @param PhysicalProcessorPackageId Physical processor package
1060 identifier which was
1061 assigned at reset by the
1063 controller. This value may
1064 or may not be unique
1065 across the entire platform
1066 since it depends on the
1067 platform vendor's policy.
1070 UINT64 NumberOfLogicalProcessors
:16;
1071 UINT64 ThreadsPerCore
:8;
1073 UINT64 CoresPerProcessor
;
1075 UINT64 PhysicalProcessorPackageId
:8;
1077 } PAL_LOGICAL_PROCESSPR_OVERVIEW
;
1081 @param ThreadId The thread identifier of the logical
1082 processor for which information is being
1083 returned. This value will be unique on a per
1086 @param CoreId The core identifier of the logical processor
1087 for which information is being returned.
1088 This value will be unique on a per physical
1089 processor package basis.
1094 UINT64 Reserved1
:16;
1096 UINT64 Reserved2
:16;
1097 } PAL_LOGICAL_PROCESSORN_INFO1
;
1102 @param LogicalAddress Geographical address of the logical
1103 processor for which information is being
1104 returned. This is the same value that is
1105 returned by the PAL_FIXED_ADDR procedure
1106 when it is called on the logical
1112 UINT64 LogicalAddress
:16;
1114 } PAL_LOGICAL_PROCESSORN_INFO2
;
1117 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
1119 Return information on which logical processors map to a
1120 physical processor die. It is optinal. The PAL procedure
1121 supports the Static Registers calling convention. It could be
1122 called at physical mode and virtual mode.
1124 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
1126 @param ProcessorNumber Signed 64-bit integer that specifies
1127 for which logical processor
1128 information is being requested. When
1129 this input argument is -1, information
1130 is returned about the logical
1131 processor on which the procedure call
1132 is made. This input argument must be
1133 in the range of 1 up to one less than
1134 the number of logical processors
1135 returned by num_log in the
1136 log_overview return value.
1138 @retval 0 Call completed without error
1139 @retval -1 Unimplemented procedure
1140 @retval -2 Invalid argument
1141 @retval -3 Call completed with error.
1143 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
1144 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
1145 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
1148 #define PAL_LOGICAL_TO_PHYSICAL 42
1153 @param NumberOfPmcPairs Unsigned 8-bit number defining the
1154 number of generic PMC/PMD pairs.
1156 @param WidthOfCounter Unsigned 8-bit number in the range
1157 0:60 defining the number of
1158 implemented counter bits.
1160 @param TypeOfCycleCounting Unsigned 8-bit number defining the
1161 event type for counting processor
1165 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
1167 event type for retired
1168 instruction bundles.
1172 UINT64 NumberOfPmcPairs
:8;
1173 UINT64 WidthOfCounter
:8;
1174 UINT64 TypeOfCycleCounting
:8;
1175 UINT64 TypeOfRetiredInstructionBundle
:8;
1177 } PAL_PERFORMANCE_INFO
;
1180 PAL Procedure - PAL_PERF_MON_INFO.
1182 Return the number and type of performance monitors. It is
1183 required by IPF. The PAL procedure supports the Static
1184 Registers calling convention. It could be called at physical
1185 mode and virtual mode.
1187 @param Index Index of PAL_PERF_MON_INFO within the list of
1189 @param PerformanceBuffer An address to an 8-byte aligned
1190 128-byte memory buffer.
1192 @retval 0 Call completed without error
1193 @retval -2 Invalid argument
1194 @retval -3 Call completed with error.
1196 @return R9 Information about the performance monitors
1197 implemented. See PAL_PERFORMANCE_INFO;
1200 #define PAL_PERF_MON_INFO 15
1202 #define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0
1203 #define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1
1206 PAL Procedure - PAL_PLATFORM_ADDR.
1208 Specify processor interrupt block address and I/O port space
1209 address. It is required by IPF. The PAL procedure supports the
1210 Static Registers calling convention. It could be called at
1211 physical mode and virtual mode.
1213 @param Index Index of PAL_PLATFORM_ADDR within the list of
1215 @param Type Unsigned 64-bit integer specifying the type of
1216 block. 0 indicates that the processor interrupt
1217 block pointer should be initialized. 1 indicates
1218 that the processor I/O block pointer should be
1220 @param Address Unsigned 64-bit integer specifying the address
1221 to which the processor I/O block or interrupt
1222 block shall be set. The address must specify
1223 an implemented physical address on the
1224 processor model, bit 63 is ignored.
1226 @retval 0 Call completed without error
1227 @retval -1 Unimplemented procedure.
1228 @retval -2 Invalid argument
1229 @retval -3 Call completed with error.
1232 #define PAL_PLATFORM_ADDR 16
1237 @param EnableBerrPromotion Bit63. Enable BERR promotion. When
1238 1, the Bus Error (BERR) signal is
1239 promoted to the Bus Initialization
1240 (BINIT) signal, and the BINIT pin
1241 is asserted on the occurrence of
1242 each Bus Error. Setting this bit
1243 has no effect if BINIT signalling
1245 PAL_BUS_GET/SET_FEATURES)
1247 @param EnableMcaPromotion Bit62, Enable MCA promotion. When
1248 1, machine check aborts (MCAs) are
1249 promoted to the Bus Error signal,
1250 and the BERR pin is assert on each
1251 occurrence of an MCA. Setting this
1252 bit has no effect if BERR
1253 signalling is disabled. (See
1254 PAL_BUS_GET/SET_FEATURES)
1256 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
1257 promotion. When 1, machine
1258 check aborts (MCAs) are
1260 Initialization signal, and
1261 the BINIT pin is assert on
1262 each occurrence of an MCA.
1263 Setting this bit has no
1264 effect if BINIT signalling
1266 PAL_BUS_GET/SET_FEATURES)
1268 @param EnableCmciPromotion Bit60, Enable CMCI promotion When
1269 1, Corrected Machine Check
1270 Interrupts (CMCI) are promoted to
1271 MCAs. They are also further
1272 promoted to BERR if bit 39, Enable
1273 MCA promotion, is also set and
1274 they are promoted to BINIT if bit
1275 38, Enable MCA to BINIT promotion,
1276 is also set. This bit has no
1277 effect if MCA signalling is
1279 PAL_BUS_GET/SET_FEATURES)
1281 @param DisableCache Bit59, Disable Cache. When 0, the
1282 processor performs cast outs on
1283 cacheable pages and issues and responds
1284 to coherency requests normally. When 1,
1285 the processor performs a memory access
1286 for each reference regardless of cache
1287 contents and issues no coherence
1288 requests and responds as if the line
1289 were not present. Cache contents cannot
1290 be relied upon when the cache is
1291 disabled. WARNING: Semaphore
1292 instructions may not be atomic or may
1293 cause Unsupported Data Reference faults
1294 if caches are disabled.
1296 @param DisableCoherency Bit58, Disable Coherency. When 0,
1297 the processor uses normal coherency
1298 requests and responses. When 1, the
1299 processor answers all requests as if
1300 the line were not present.
1302 @param DisableDPM Bit57, Disable Dynamic Power Management
1303 (DPM). When 0, the hardware may reduce
1304 power consumption by removing the clock
1305 input from idle functional units. When 1,
1306 all functional units will receive clock
1307 input, even when idle.
1309 @param DisableBinitWithTimeout Bit56, Disable a BINIT on
1310 internal processor time-out.
1311 When 0, the processor may
1312 generate a BINIT on an
1313 internal processor time-out.
1314 When 1, the processor will not
1315 generate a BINIT on an
1316 internal processor time-out.
1317 The event is silently ignored.
1320 @param EnableEnvNotification Bit55, Enable external
1321 notification when the processor
1322 detects hardware errors caused
1323 by environmental factors that
1325 deterministic behavior of the
1326 processor. When 1, this bit will
1327 enable external notification,
1328 when 0 external notification is
1329 not provided. The type of
1330 external notification of these
1331 errors is processor-dependent. A
1332 loss of processor deterministic
1333 behavior is considered to have
1335 environmentally induced errors
1336 cause the processor to deviate
1337 from its normal execution and
1338 eventually causes different
1339 behavior which can be observed
1340 at the processor bus pins.
1341 Processor errors that do not
1342 have this effects (i.e.,
1343 software induced machine checks)
1344 may or may not be promoted
1345 depending on the processor
1348 @param EnableVmsw Bit54, Enable the use of the vmsw
1349 instruction. When 0, the vmsw instruction
1350 causes a Virtualization fault when
1351 executed at the most privileged level.
1352 When 1, this bit will enable normal
1353 operation of the vmsw instruction.
1355 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
1356 on data-poisoning event
1357 detection. When 0, a CMCI
1358 will be signaled on error
1359 detection. When 1, an MCA
1360 will be signaled on error
1361 detection. If this feature
1362 is not supported, then the
1363 corresponding argument is
1364 ignored when calling
1365 PAL_PROC_SET_FEATURES. Note
1366 that the functionality of
1367 this bit is independent of
1368 the setting in bit 60
1369 (Enable CMCI promotion), and
1370 that the bit 60 setting does
1371 not affect CMCI signaling
1372 for data-poisoning related
1373 events. Volume 2: Processor
1374 Abstraction Layer 2:431
1375 PAL_PROC_GET_FEATURES
1377 @param DisablePState Bit52, Disable P-states. When 1, the PAL
1378 P-state procedures (PAL_PSTATE_INFO,
1379 PAL_SET_PSTATE, PAL_GET_PSTATE) will
1380 return with a status of -1
1381 (Unimplemented procedure).
1383 @param DisableBranchPrediction Bit47, Disable Dynamic branch
1384 prediction. When 0, the
1385 processor may predict branch
1386 targets and speculatively
1387 execute, but may not commit
1388 results. When 1, the processor
1389 must wait until branch targets
1390 are known to execute.
1392 @param DisableDynamicInsCachePrefetch Bit46, Disable
1393 DynamicInstruction Cache
1394 Prefetch. When 0, the
1395 processor may prefetch
1397 instruction which has
1398 not been executed, but
1401 instructions may not be
1402 fetched until needed or
1403 hinted for execution.
1404 (Prefetch for a hinted
1405 branch is allowed even
1406 when dynamic instruction
1410 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
1411 Data Cache Prefetch.
1412 When 0, the processor
1413 may prefetch into the
1414 caches any data which
1415 has not been accessed
1417 execution, but which
1419 accessed. When 1, no
1421 until it is needed for
1422 instruction execution
1426 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous
1427 Deferral. When 1, the
1428 processor may optionally
1429 defer speculative loads
1430 that do not encounter any
1431 exception conditions, but
1433 implementation-dependent
1434 conditions (e.g., cache
1435 miss). When 0, spontaneous
1436 deferral is disabled.
1438 @param DisableDynamicPrediction Bit43, Disable Dynamic
1439 Predicate Prediction. When
1440 0, the processor may predict
1441 predicate results and
1442 execute speculatively, but
1443 may not commit results until
1444 the actual predicates are
1445 known. When 1, the processor
1446 shall not execute predicated
1447 instructions until the
1448 actual predicates are known.
1450 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
1451 Denotes whether XR1 XR3 are
1452 implemented for machine check
1453 recovery. This feature may only be
1454 interrogated by PAL_PROC_GET_FEATURES.
1455 It may not be enabled or disabled by
1456 PAL_PROC_SET_FEATURES. The
1457 corresponding argument is ignored.
1459 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
1460 implemented. Denotes whether XIP, XPSR,
1461 and XFS are implemented for machine
1462 check recovery. This feature may only be
1463 interrogated by PAL_PROC_GET_FEATURES.
1464 It may not be enabled or disabled by
1465 PAL_PROC_SET_FEATURES. The corresponding
1466 argument is ignored.
1468 @param NoVM Bit40, No Virtual Machine features implemented.
1469 Denotes whether PSR.vm is implemented. This
1470 feature may only be interrogated by
1471 PAL_PROC_GET_FEATURES. It may not be enabled or
1472 disabled by PAL_PROC_SET_FEATURES. The
1473 corresponding argument is ignored.
1475 @param NoVariablePState Bit39, No Variable P-state
1476 performance: A value of 1, indicates
1477 that a processor implements
1478 techniques to optimize performance
1479 for the given P-state power budget
1480 by dynamically varying the
1481 frequency, such that maximum
1482 performance is achieved for the
1483 power budget. A value of 0,
1484 indicates that P-states have no
1485 frequency variation or very small
1486 frequency variations for their given
1487 power budget. This feature may only
1489 PAL_PROC_GET_FEATURES. it may not be
1490 enabled or disabled by
1491 PAL_PROC_SET_FEATURES. The
1492 corresponding argument is ignored.
1495 @param NoSimpleImpInUndefinedIns Bit38, No Simple
1497 unimplemented instruction
1498 addresses. Denotes how an
1499 unimplemented instruction
1500 address is recorded in IIP
1502 Instruction Address trap or
1503 fault. When 1, the full
1504 unimplemented address is
1505 recorded in IIP; when 0, the
1506 address is sign extended
1507 (virtual addresses) or zero
1509 addresses). This feature may
1510 only be interrogated by
1511 PAL_PROC_GET_FEATURES. It
1512 may not be enabled or
1514 PAL_PROC_SET_FEATURES. The
1515 corresponding argument is
1518 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
1519 present. Denotes the absence of INIT,
1520 PMI, LINT0 and LINT1 pins on the
1521 processor. When 1, the pins are absent.
1522 When 0, the pins are present. This
1523 feature may only be interrogated by
1524 PAL_PROC_GET_FEATURES. It may not be
1525 enabled or disabled by
1526 PAL_PROC_SET_FEATURES. The corresponding
1527 argument is ignored.
1529 @param FaultInUndefinedIns Bit36, No Unimplemented
1530 instruction address reported as
1531 fault. Denotes how the processor
1532 reports the detection of
1533 unimplemented instruction
1534 addresses. When 1, the processor
1535 reports an Unimplemented
1536 Instruction Address fault on the
1537 unimplemented address; when 0, it
1538 reports an Unimplemented
1539 Instruction Address trap on the
1540 previous instruction in program
1541 order. This feature may only be
1543 PAL_PROC_GET_FEATURES. It may not
1544 be enabled or disabled by
1545 PAL_PROC_SET_FEATURES. The
1546 corresponding argument is
1551 UINT64 Reserved1
:36;
1552 UINT64 FaultInUndefinedIns
:1;
1553 UINT64 NoPresentPmi
:1;
1554 UINT64 NoSimpleImpInUndefinedIns
:1;
1555 UINT64 NoVariablePState
:1;
1557 UINT64 NoXipXpsrXfs
:1;
1558 UINT64 NoXr1ThroughXr3
:1;
1559 UINT64 DisableDynamicPrediction
:1;
1560 UINT64 DisableSpontaneousDeferral
:1;
1561 UINT64 DisableDynamicDataCachePrefetch
:1;
1562 UINT64 DisableDynamicInsCachePrefetch
:1;
1563 UINT64 DisableBranchPrediction
:1;
1565 UINT64 DisablePState
:1;
1566 UINT64 EnableMcaOnDataPoisoning
:1;
1567 UINT64 EnableVmsw
:1;
1568 UINT64 EnableEnvNotification
:1;
1569 UINT64 DisableBinitWithTimeout
:1;
1570 UINT64 DisableDPM
:1;
1571 UINT64 DisableCoherency
:1;
1572 UINT64 DisableCache
:1;
1573 UINT64 EnableCmciPromotion
:1;
1574 UINT64 EnableMcaToBinitPromotion
:1;
1575 UINT64 EnableMcaPromotion
:1;
1576 UINT64 EnableBerrPromotion
:1;
1577 } PAL_PROCESSOR_FEATURES
;
1580 PAL Procedure - PAL_PROC_GET_FEATURES.
1582 Return configurable processor features and their current
1583 setting. It is required by IPF. The PAL procedure supports the
1584 Static Registers calling convention. It could be called at
1585 physical mode and virtual mode.
1587 @param Index Index of PAL_PROC_GET_FEATURES within the list of
1589 @param Reserved Reserved parameter.
1590 @param FeatureSet Feature set information is being requested
1593 @retval 1 Call completed without error; The
1594 feature_set passed is not supported but a
1595 feature_set of a larger value is supported.
1596 @retval 0 Call completed without error
1597 @retval -2 Invalid argument
1598 @retval -3 Call completed with error.
1599 @retval -8 feature_set passed is beyond the maximum
1600 feature_set supported
1602 @return R9 64-bit vector of features implemented. See
1603 PAL_PROCESSOR_FEATURES.
1604 @return R10 64-bit vector of current feature settings. See
1605 PAL_PROCESSOR_FEATURES.
1606 @return R11 64-bit vector of features controllable by
1610 #define PAL_PROC_GET_FEATURES 17
1614 PAL Procedure - PAL_PROC_SET_FEATURES.
1616 Enable or disable configurable processor features. It is
1617 required by IPF. The PAL procedure supports the Static
1618 Registers calling convention. It could be called at physical
1621 @param Index Index of PAL_PROC_SET_FEATURES within the list of
1623 @param FeatureSelect 64-bit vector denoting desired state of
1624 each feature (1=select, 0=non-select).
1625 @param FeatureSet Feature set to apply changes to. See
1626 PAL_PROC_GET_FEATURES for more information
1629 @retval 1 Call completed without error; The
1630 feature_set passed is not supported but a
1631 feature_set of a larger value is supported
1632 @retval 0 Call completed without error
1633 @retval -2 Invalid argument
1634 @retval -3 Call completed with error.
1635 @retval -8 feature_set passed is beyond the maximum
1636 feature_set supported
1639 #define PAL_PROC_SET_FEATURES 18
1643 // Value of PAL_REGISTER_INFO.InfoRequest.
1645 #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
1646 #define PAL_APPLICATION_REGISTER_READABLE 1
1647 #define PAL_CONTROL_REGISTER_IMPLEMENTED 2
1648 #define PAL_CONTROL_REGISTER_READABLE 3
1652 PAL Procedure - PAL_REGISTER_INFO.
1654 Return AR and CR register information. It is required by IPF.
1655 The PAL procedure supports the Static Registers calling
1656 convention. It could be called at physical mode and virtual
1659 @param Index Index of PAL_REGISTER_INFO within the list of
1661 @param InfoRequest Unsigned 64-bit integer denoting what
1662 register information is requested. See
1663 PAL_REGISTER_INFO.InfoRequest above.
1665 @retval 0 Call completed without error
1666 @retval -2 Invalid argument
1667 @retval -3 Call completed with error.
1669 @return R9 64-bit vector denoting information for registers
1670 0-63. Bit 0 is register 0, bit 63 is register 63.
1671 @return R10 64-bit vector denoting information for registers
1672 64-127. Bit 0 is register 64, bit 63 is register
1676 #define PAL_REGISTER_INFO 39
1679 PAL Procedure - PAL_RSE_INFO.
1681 Return RSE information. It is required by IPF. The PAL
1682 procedure supports the Static Registers calling convention. It
1683 could be called at physical mode and virtual mode.
1685 @param Index Index of PAL_RSE_INFO within the list of
1687 @param InfoRequest Unsigned 64-bit integer denoting what
1688 register information is requested. See
1689 PAL_REGISTER_INFO.InfoRequest above.
1691 @retval 0 Call completed without error
1692 @retval -2 Invalid argument
1693 @retval -3 Call completed with error.
1695 @return R9 Number of physical stacked general registers.
1696 @return R10 RSE hints supported by processor.
1699 #define PAL_RSE_INFO 19
1703 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1704 number that provides identification
1705 information about the PAL_B firmware.
1707 @param PalVendor Is an unsigned 8-bit integer indicating the
1708 vendor of the PAL code.
1710 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1711 number that provides identification
1712 information about the PAL_A firmware. In
1713 the split PAL_A model, this return value
1714 is the version number of the
1715 processor-specific PAL_A. The generic
1716 PAL_A version is not returned by this
1717 procedure in the split PAL_A model.
1721 UINT64 VersionOfPalB
:16;
1724 UINT64 VersionOfPalA
:16;
1725 UINT64 Reserved2
:16;
1729 PAL Procedure - PAL_VERSION.
1731 Return version of PAL code. It is required by IPF. The PAL
1732 procedure supports the Static Registers calling convention. It
1733 could be called at physical mode and virtual mode.
1735 @param Index Index of PAL_VERSION within the list of
1737 @param InfoRequest Unsigned 64-bit integer denoting what
1738 register information is requested. See
1739 PAL_REGISTER_INFO.InfoRequest above.
1741 @retval 0 Call completed without error
1742 @retval -2 Invalid argument
1743 @retval -3 Call completed with error.
1745 @return R9 8-byte formatted value returning the minimum PAL
1746 version needed for proper operation of the
1747 processor. See PAL_VERSION_INFO above.
1748 @return R10 8-byte formatted value returning the current PAL
1749 version running on the processor. See
1750 PAL_VERSION_INFO above.
1753 #define PAL_VERSION 20
1758 // Vectors of PAL_MC_CLEAR_LOG.pending
1760 #define PAL_MC_PENDING BIT0
1761 #define PAL_INIT_PENDING BIT1
1764 PAL Procedure - PAL_MC_CLEAR_LOG.
1766 Clear all error information from processor error logging
1767 registers. It is required by IPF. The PAL procedure supports
1768 the Static Registers calling convention. It could be called at
1769 physical mode and virtual mode.
1771 @param Index Index of PAL_MC_CLEAR_LOG within the list of
1774 @retval 0 Call completed without error
1775 @retval -2 Invalid argument
1776 @retval -3 Call completed with error.
1778 @return R9 64-bit vector denoting whether an event is
1779 pending. See PAL_MC_CLEAR_LOG.pending above.
1782 #define PAL_MC_CLEAR_LOG 21
1785 PAL Procedure - PAL_MC_DRAIN.
1787 Ensure that all operations that could cause an MCA have
1788 completed. It is required by IPF. The PAL procedure supports
1789 the Static Registers calling convention. It could be called at
1790 physical mode and virtual mode.
1792 @param Index Index of PAL_MC_DRAIN within the list of PAL
1795 @retval 0 Call completed without error
1796 @retval -2 Invalid argument
1797 @retval -3 Call completed with error.
1800 #define PAL_MC_DRAIN 22
1804 PAL Procedure - PAL_MC_DYNAMIC_STATE.
1806 Return Processor Dynamic State for logging by SAL. It is
1807 optional. The PAL procedure supports the Static Registers
1808 calling convention. It could be called at physical mode.
1810 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
1812 @param Offset Offset of the next 8 bytes of Dynamic Processor
1813 State to return. (multiple of 8).
1815 @retval 0 Call completed without error
1816 @retval -1 Unimplemented procedure.
1817 @retval -2 Invalid argument
1818 @retval -3 Call completed with error.
1820 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
1821 Processor State returned.
1822 @return R10 Next 8 bytes of Dynamic Processor State.
1825 #define PAL_MC_DYNAMIC_STATE 24
1830 // Values of PAL_MC_ERROR_INFO.InfoIndex.
1832 #define PAL_PROCESSOR_ERROR_MAP 0
1833 #define PAL_PROCESSOR_STATE_PARAM 1
1834 #define PAL_STRUCTURE_SPECIFIC_ERROR 2
1838 @param CoreId Bit3:0, Processor core ID (default is 0 for
1839 processors with a single core)
1841 @param ThreadId Bit7:4, Logical thread ID (default is 0 for
1842 processors that execute a single thread)
1844 @param InfoOfInsCache Bit11:8, Error information is
1845 available for 1st, 2nd, 3rd, and 4th
1846 level instruction caches.
1848 @param InfoOfDataCache Bit15:12, Error information is
1849 available for 1st, 2nd, 3rd, and 4th
1850 level data/unified caches.
1852 @param InfoOfInsTlb Bit19:16 Error information is available
1853 for 1st, 2nd, 3rd, and 4th level
1856 @param InfoOfDataTlb Bit23:20, Error information is available
1857 for 1st, 2nd, 3rd, and 4th level
1860 @param InfoOfProcessorBus Bit27:24 Error information is
1861 available for the 1st, 2nd, 3rd,
1862 and 4th level processor bus
1865 @param InfoOfRegisterFile Bit31:28 Error information is
1866 available on register file
1869 @param InfoOfMicroArch Bit47:32, Error information is
1870 available on micro-architectural
1877 UINT64 InfoOfInsCache
:4;
1878 UINT64 InfoOfDataCache
:4;
1879 UINT64 InfoOfInsTlb
:4;
1880 UINT64 InfoOfDataTlb
:4;
1881 UINT64 InfoOfProcessorBus
:4;
1882 UINT64 InfoOfRegisterFile
:4;
1883 UINT64 InfoOfMicroArch
:4;
1885 } PAL_MC_ERROR_INFO_LEVEL_INDEX
;
1888 // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
1890 #define PAL_ERR_INFO_BY_LEVEL_INDEX 0
1891 #define PAL_ERR_INFO_TARGET_ADDRESS 1
1892 #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
1893 #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
1894 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
1898 @param Operation Bit3:0, Type of cache operation that caused
1899 the machine check: 0 - unknown or internal
1900 error 1 - load 2 - store 3 - instruction
1901 fetch or instruction prefetch 4 - data
1902 prefetch (both hardware and software) 5 -
1903 snoop (coherency check) 6 - cast out
1904 (explicit or implicit write-back of a cache
1905 line) 7 - move in (cache line fill)
1907 @param FailedCacheLevel Bit5:4 Level of cache where the
1908 error occurred. A value of 0
1909 indicates the first level of cache.
1911 @param FailedInDataPart Bit8, Failure located in the data
1912 part of the cache line.
1914 @param FailedInTagPart Bit9, Failure located in the tag part
1917 @param FailedInDataCache Bit10, Failure located in the data
1920 @param FailedInInsCache Bit11, Failure located in the
1924 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
1925 line is held shared. 2 - cache line is held
1926 exclusive. 3 - cache line is modified. All other
1927 values are reserved.
1929 @param MesiIsValid Bit15, The mesi field in the cache_check
1932 @param FailedWay Bit20:16, Failure located in the way of
1933 the cache indicated by this value.
1935 @param WayIndexIsValid Bit21, The way and index field in the
1936 cache_check parameter is valid.
1938 @param MultipleBitsError Bit23, A multiple-bit error was
1939 detected, and data was poisoned for
1940 the corresponding cache line during
1943 @param IndexOfCacheLineError Bit51:32, Index of the cache
1944 line where the error occurred.
1946 @param InstructionSet Bit54, Instruction set. If this value
1947 is set to zero, the instruction that
1948 generated the machine check was an
1949 Intel Itanium instruction. If this bit
1950 is set to one, the instruction that
1951 generated the machine check was IA-32
1954 @param InstructionSetIsValid Bit55, The is field in the
1955 cache_check parameter is valid.
1957 @param PrivilegeLevel Bit57:56, Privilege level. The
1958 privilege level of the instruction
1959 bundle responsible for generating the
1962 @param PrivilegeLevelIsValide Bit58, The pl field of the
1963 cache_check parameter is
1966 @param McCorrected Bit59, Machine check corrected: This bit
1967 is set to one to indicate that the machine
1968 check has been corrected.
1970 @param TargetAddressIsValid Bit60, Target address is valid:
1971 This bit is set to one to
1972 indicate that a valid target
1973 address has been logged.
1975 @param RequesterIdentifier Bit61, Requester identifier: This
1976 bit is set to one to indicate that
1977 a valid requester identifier has
1980 @param ResponserIdentifier Bit62, Responder identifier: This
1981 bit is set to one to indicate that
1982 a valid responder identifier has
1985 @param PreciseInsPointer Bit63, Precise instruction pointer.
1986 This bit is set to one to indicate
1987 that a valid precise instruction
1988 pointer has been logged.
1993 UINT64 FailedCacheLevel
:2;
1995 UINT64 FailedInDataPart
:1;
1996 UINT64 FailedInTagPart
:1;
1997 UINT64 FailedInDataCache
:1;
1998 UINT64 FailedInInsCache
:1;
2000 UINT64 MesiIsValid
:1;
2002 UINT64 WayIndexIsValid
:1;
2005 UINT64 MultipleBitsError
:1;
2007 UINT64 IndexOfCacheLineError
:20;
2009 UINT64 InstructionSet
:1;
2010 UINT64 InstructionSetIsValid
:1;
2012 UINT64 PrivilegeLevel
:2;
2013 UINT64 PrivilegeLevelIsValide
:1;
2015 UINT64 McCorrected
:1;
2017 UINT64 TargetAddressIsValid
:1;
2018 UINT64 RequesterIdentifier
:1;
2019 UINT64 ResponserIdentifier
:1;
2020 UINT64 PreciseInsPointer
:1;
2022 } PAL_CACHE_CHECK_INFO
;
2026 @param FailedSlot Bit7:0, Slot number of the translation
2027 register where the failure occurred.
2029 @param FailedSlotIsValid Bit8, The tr_slot field in the
2030 TLB_check parameter is valid.
2032 @param TlbLevel Bit11:10, The level of the TLB where the
2033 error occurred. A value of 0 indicates the
2036 @param FailedInDataTr Bit16, Error occurred in the data
2037 translation registers.
2039 @param FailedInInsTr Bit17, Error occurred in the instruction
2040 translation registers
2042 @param FailedInDataTc Bit18, Error occurred in data
2045 @param FailedInInsTc Bit19, Error occurred in the instruction
2048 @param FailedOperation Bit23:20, Type of cache operation that
2049 caused the machine check: 0 - unknown
2050 1 - TLB access due to load instruction
2051 2 - TLB access due to store
2052 instruction 3 - TLB access due to
2053 instruction fetch or instruction
2054 prefetch 4 - TLB access due to data
2055 prefetch (both hardware and software)
2056 5 - TLB shoot down access 6 - TLB
2057 probe instruction (probe, tpa) 7 -
2058 move in (VHPT fill) 8 - purge (insert
2059 operation that purges entries or a TLB
2060 purge instruction) All other values
2063 @param InstructionSet Bit54, Instruction set. If this value
2064 is set to zero, the instruction that
2065 generated the machine check was an
2066 Intel Itanium instruction. If this bit
2067 is set to one, the instruction that
2068 generated the machine check was IA-32
2071 @param InstructionSetIsValid Bit55, The is field in the
2072 TLB_check parameter is valid.
2074 @param PrivelegeLevel Bit57:56, Privilege level. The
2075 privilege level of the instruction
2076 bundle responsible for generating the
2079 @param PrivelegeLevelIsValid Bit58, The pl field of the
2080 TLB_check parameter is valid.
2082 @param McCorrected Bit59, Machine check corrected: This bit
2083 is set to one to indicate that the machine
2084 check has been corrected.
2086 @param TargetAddressIsValid Bit60, Target address is valid:
2087 This bit is set to one to
2088 indicate that a valid target
2089 address has been logged.
2091 @param RequesterIdentifier Bit61 Requester identifier: This
2092 bit is set to one to indicate that
2093 a valid requester identifier has
2096 @param ResponserIdentifier Bit62, Responder identifier: This
2097 bit is set to one to indicate that
2098 a valid responder identifier has
2101 @param PreciseInsPointer Bit63 Precise instruction pointer.
2102 This bit is set to one to indicate
2103 that a valid precise instruction
2104 pointer has been logged.
2107 UINT64 FailedSlot
:8;
2108 UINT64 FailedSlotIsValid
:1;
2109 UINT64 Reserved1
:1;
2111 UINT64 Reserved2
:4;
2112 UINT64 FailedInDataTr
:1;
2113 UINT64 FailedInInsTr
:1;
2114 UINT64 FailedInDataTc
:1;
2115 UINT64 FailedInInsTc
:1;
2116 UINT64 FailedOperation
:4;
2117 UINT64 Reserved3
:30;
2118 UINT64 InstructionSet
:1;
2119 UINT64 InstructionSetIsValid
:1;
2120 UINT64 PrivelegeLevel
:2;
2121 UINT64 PrivelegeLevelIsValid
:1;
2122 UINT64 McCorrected
:1;
2123 UINT64 TargetAddressIsValid
:1;
2124 UINT64 RequesterIdentifier
:1;
2125 UINT64 ResponserIdentifier
:1;
2126 UINT64 PreciseInsPointer
:1;
2127 } PAL_TLB_CHECK_INFO
;
2130 PAL Procedure - PAL_MC_ERROR_INFO.
2132 Return Processor Machine Check Information and Processor
2133 Static State for logging by SAL. It is required by IPF. The
2134 PAL procedure supports the Static Registers calling
2135 convention. It could be called at physical and virtual mode.
2137 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
2139 @param InfoIndex Unsigned 64-bit integer identifying the
2140 error information that is being requested.
2141 See PAL_MC_ERROR_INFO.InfoIndex.
2142 @param LevelIndex 8-byte formatted value identifying the
2143 structure to return error information
2144 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
2145 @param ErrorTypeIndex Unsigned 64-bit integer denoting the
2146 type of error information that is
2147 being requested for the structure
2148 identified in LevelIndex.
2150 @retval 0 Call completed without error
2151 @retval -2 Invalid argument
2152 @retval -3 Call completed with error.
2153 @retval -6 Argument was valid, but no error
2154 information was available
2156 @return R9 Error information returned. The format of this
2157 value is dependant on the input values passed.
2158 @return R10 If this value is zero, all the error information
2159 specified by err_type_index has been returned. If
2160 this value is one, more structure-specific error
2161 information is available and the caller needs to
2162 make this procedure call again with level_index
2163 unchanged and err_type_index, incremented.
2166 #define PAL_MC_ERROR_INFO 25
2169 PAL Procedure - PAL_MC_EXPECTED.
2171 Set/Reset Expected Machine Check Indicator. It is required by
2172 IPF. The PAL procedure supports the Static Registers calling
2173 convention. It could be called at physical mode.
2175 @param Index Index of PAL_MC_EXPECTED within the list of PAL
2177 @param Expected Unsigned integer with a value of 0 or 1 to
2178 set or reset the hardware resource
2179 PALE_CHECK examines for expected machine
2182 @retval 0 Call completed without error
2183 @retval -2 Invalid argument
2184 @retval -3 Call completed with error.
2186 @return R9 Unsigned integer denoting whether a machine check
2187 was previously expected.
2190 #define PAL_MC_EXPECTED 23
2193 PAL Procedure - PAL_MC_REGISTER_MEM.
2195 Register min-state save area with PAL for machine checks and
2196 inits. It is required by IPF. The PAL procedure supports the
2197 Static Registers calling convention. It could be called at
2200 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
2202 @param Address Physical address of the buffer to be
2203 registered with PAL.
2205 @retval 0 Call completed without error
2206 @retval -2 Invalid argument
2207 @retval -3 Call completed with error.
2210 #define PAL_MC_REGISTER_MEM 27
2213 PAL Procedure - PAL_MC_RESUME.
2215 Restore minimal architected state and return to interrupted
2216 process. It is required by IPF. The PAL procedure supports the
2217 Static Registers calling convention. It could be called at
2220 @param Index Index of PAL_MC_RESUME within the list of PAL
2222 @param SetCmci Unsigned 64 bit integer denoting whether to
2223 set the CMC interrupt. A value of 0 indicates
2224 not to set the interrupt, a value of 1
2225 indicated to set the interrupt, and all other
2226 values are reserved.
2227 @param SavePtr Physical address of min-state save area used
2228 to used to restore processor state.
2229 @param NewContext Unsigned 64-bit integer denoting whether
2230 the caller is returning to a new context.
2231 A value of 0 indicates the caller is
2232 returning to the interrupted context, a
2233 value of 1 indicates that the caller is
2234 returning to a new context.
2236 @retval -2 Invalid argument
2237 @retval -3 Call completed with error.
2240 #define PAL_MC_RESUME 26
2243 PAL Procedure - PAL_HALT.
2245 Enter the low-power HALT state or an implementation-dependent
2246 low-power state. It is optinal. The PAL procedure supports the
2247 Static Registers calling convention. It could be called at
2250 @param Index Index of PAL_HALT within the list of PAL
2252 @param HaltState Unsigned 64-bit integer denoting low power
2254 @param IoDetailPtr 8-byte aligned physical address pointer to
2255 information on the type of I/O
2256 (load/store) requested.
2258 @retval 0 Call completed without error
2259 @retval -1 Unimplemented procedure
2260 @retval -2 Invalid argument
2261 @retval -3 Call completed with error.
2263 @return R9 Value returned if a load instruction is requested
2264 in the io_detail_ptr
2271 PAL Procedure - PAL_HALT_INFO.
2273 Return the low power capabilities of the processor. It is
2274 required by IPF. The PAL procedure supports the
2275 Stacked Registers calling convention. It could be called at
2276 physical and virtual mode.
2278 @param Index Index of PAL_HALT_INFO within the list of PAL
2280 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
2281 on an 8-byte boundary.
2283 @retval 0 Call completed without error
2284 @retval -2 Invalid argument
2285 @retval -3 Call completed with error.
2288 #define PAL_HALT_INFO 257
2292 PAL Procedure - PAL_HALT_LIGHT.
2294 Enter the low power LIGHT HALT state. It is required by
2295 IPF. The PAL procedure supports the Static Registers calling
2296 convention. It could be called at physical and virtual mode.
2298 @param Index Index of PAL_HALT_LIGHT within the list of PAL
2301 @retval 0 Call completed without error
2302 @retval -2 Invalid argument
2303 @retval -3 Call completed with error.
2306 #define PAL_HALT_LIGHT 29
2309 PAL Procedure - PAL_CACHE_LINE_INIT.
2311 Initialize tags and data of a cache line for processor
2312 testing. It is required by IPF. The PAL procedure supports the
2313 Static Registers calling convention. It could be called at
2314 physical and virtual mode.
2316 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
2318 @param Address Unsigned 64-bit integer value denoting the
2319 physical address from which the physical page
2320 number is to be generated. The address must be
2321 an implemented physical address, bit 63 must
2323 @param DataValue 64-bit data value which is used to
2324 initialize the cache line.
2326 @retval 0 Call completed without error
2327 @retval -2 Invalid argument
2328 @retval -3 Call completed with error.
2331 #define PAL_CACHE_LINE_INIT 31
2334 PAL Procedure - PAL_CACHE_READ.
2336 Read tag and data of a cache line for diagnostic testing. It
2337 is optional. The PAL procedure supports the
2338 Satcked Registers calling convention. It could be called at
2341 @param Index Index of PAL_CACHE_READ within the list of PAL
2343 @param LineId 8-byte formatted value describing where in the
2344 cache to read the data.
2345 @param Address 64-bit 8-byte aligned physical address from
2346 which to read the data. The address must be an
2347 implemented physical address on the processor
2348 model with bit 63 set to zero.
2350 @retval 1 The word at address was found in the
2351 cache, but the line was invalid.
2352 @retval 0 Call completed without error
2353 @retval -2 Invalid argument
2354 @retval -3 Call completed with error.
2355 @retval -5 The word at address was not found in the
2357 @retval -7 The operation requested is not supported
2358 for this cache_type and level.
2360 @return R9 Right-justified value returned from the cache
2362 @return R10 The number of bits returned in data.
2363 @return R11 The status of the cache line.
2366 #define PAL_CACHE_READ 259
2370 PAL Procedure - PAL_CACHE_WRITE.
2372 Write tag and data of a cache for diagnostic testing. It is
2373 optional. The PAL procedure supports the Satcked Registers
2374 calling convention. It could be called at physical mode.
2376 @param Index Index of PAL_CACHE_WRITE within the list of PAL
2378 @param LineId 8-byte formatted value describing where in the
2379 cache to write the data.
2380 @param Address 64-bit 8-byte aligned physical address at
2381 which the data should be written. The address
2382 must be an implemented physical address on the
2383 processor model with bit 63 set to 0.
2384 @param Data Unsigned 64-bit integer value to write into
2385 the specified part of the cache.
2387 @retval 0 Call completed without error
2388 @retval -2 Invalid argument
2389 @retval -3 Call completed with error.
2390 @retval -7 The operation requested is not supported
2391 for this cache_type and level.
2394 #define PAL_CACHE_WRITE 260
2397 PAL Procedure - PAL_TEST_INFO.
2399 Returns alignment and size requirements needed for the memory
2400 buffer passed to the PAL_TEST_PROC procedure as well as
2401 information on self-test control words for the processor self
2402 tests. It is required by IPF. The PAL procedure supports the
2403 Static Registers calling convention. It could be called at
2406 @param Index Index of PAL_TEST_INFO within the list of PAL
2408 @param TestPhase Unsigned integer that specifies which phase
2409 of the processor self-test information is
2410 being requested on. A value of 0 indicates
2411 the phase two of the processor self-test and
2412 a value of 1 indicates phase one of the
2413 processor self-test. All other values are
2416 @retval 0 Call completed without error
2417 @retval -2 Invalid argument
2418 @retval -3 Call completed with error.
2420 @return R9 Unsigned 64-bit integer denoting the number of
2421 bytes of main memory needed to perform the second
2422 phase of processor self-test.
2423 @return R10 Unsigned 64-bit integer denoting the alignment
2424 required for the memory buffer.
2425 @return R11 48-bit wide bit-field indicating if control of
2426 the processor self-tests is supported and which
2427 bits of the test_control field are defined for
2431 #define PAL_TEST_INFO 37
2435 @param BufferSize Indicates the size in bytes of the memory
2436 buffer that is passed to this procedure.
2437 BufferSize must be greater than or equal in
2438 size to the bytes_needed return value from
2439 PAL_TEST_INFO, otherwise this procedure will
2440 return with an invalid argument return
2443 @param TestPhase Defines which phase of the processor
2444 self-tests are requested to be run. A value
2445 of zero indicates to run phase two of the
2446 processor self-tests. Phase two of the
2447 processor self-tests are ones that require
2448 external memory to execute correctly. A
2449 value of one indicates to run phase one of
2450 the processor self-tests. Phase one of the
2451 processor self-tests are tests run during
2452 PALE_RESET and do not depend on external
2453 memory to run correctly. When the caller
2454 requests to have phase one of the processor
2455 self-test run via this procedure call, a
2456 memory buffer may be needed to save and
2457 restore state as required by the PAL calling
2458 conventions. The procedure PAL_TEST_INFO
2459 informs the caller about the requirements of
2464 UINT64 BufferSize
:56;
2466 } PAL_TEST_INFO_INFO
;
2470 @param TestControl This is an ordered implementation-specific
2471 control word that allows the user control
2472 over the length and runtime of the
2473 processor self-tests. This control word is
2474 ordered from the longest running tests up
2475 to the shortest running tests with bit 0
2476 controlling the longest running test. PAL
2477 may not implement all 47-bits of the
2478 test_control word. PAL communicates if a
2479 bit provides control by placing a zero in
2480 that bit. If a bit provides no control,
2481 PAL will place a one in it. PAL will have
2482 two sets of test_control bits for the two
2483 phases of the processor self-test. PAL
2484 provides information about implemented
2485 test_control bits at the hand-off from PAL
2486 to SAL for the firmware recovery check.
2487 These test_control bits provide control
2488 for phase one of processor self-test. It
2489 also provides this information via the PAL
2490 procedure call PAL_TEST_INFO for both the
2491 phase one and phase two processor tests
2492 depending on which information the caller
2493 is requesting. PAL interprets these bits
2494 as input parameters on two occasions. The
2495 first time is when SAL passes control back
2496 to PAL after the firmware recovery check.
2497 The second time is when a call to
2498 PAL_TEST_PROC is made. When PAL interprets
2499 these bits it will only interpret
2500 implemented test_control bits and will
2501 ignore the values located in the
2502 unimplemented test_control bits. PAL
2503 interprets the implemented bits such that
2504 if a bit contains a zero, this indicates
2505 to run the test. If a bit contains a one,
2506 this indicates to PAL to skip the test. If
2507 the cs bit indicates that control is not
2508 available, the test_control bits will be
2509 ignored or generate an illegal argument in
2510 procedure calls if the caller sets these
2513 @param ControlSupport This bit defines if an implementation
2514 supports control of the PAL self-tests
2515 via the self-test control word. If
2516 this bit is 0, the implementation does
2517 not support control of the processor
2518 self-tests via the self-test control
2519 word. If this bit is 1, the
2520 implementation does support control of
2521 the processor self-tests via the
2522 self-test control word. If control is
2523 not supported, GR37 will be ignored at
2524 the hand-off between SAL and PAL after
2525 the firmware recovery check and the
2526 PAL procedures related to the
2527 processor self-tests may return
2528 illegal arguments if a user tries to
2529 use the self-test control features.
2533 UINT64 TestControl
:47;
2534 UINT64 ControlSupport
:1;
2536 } PAL_SELF_TEST_CONTROL
;
2540 @param Attributes Specifies the memory attributes that are
2541 allowed to be used with the memory buffer
2542 passed to this procedure. The attributes
2543 parameter is a vector where each bit
2544 represents one of the virtual memory
2545 attributes defined by the architecture.See
2546 MEMORY_AATRIBUTES. The caller is required
2547 to support the cacheable attribute for the
2548 memory buffer, otherwise an invalid
2549 argument will be returned.
2552 @param TestControl Is the self-test control word
2553 corresponding to the test_phase passed.
2554 This test_control directs the coverage and
2555 runtime of the processor self-tests
2556 specified by the test_phase input
2557 argument. Information on if this
2558 feature is implemented and the number of
2559 bits supported can be obtained by the
2560 PAL_TEST_INFO procedure call. If this
2561 feature is implemented by the processor,
2562 the caller can selectively skip parts of
2563 the processor self-test by setting
2564 test_control bits to a one. If a bit has a
2565 zero, this test will be run. The values in
2566 the unimplemented bits are ignored. If
2567 PAL_TEST_INFO indicated that the self-test
2568 control word is not implemented, this
2569 procedure will return with an invalid
2570 argument status if the caller sets any of
2571 the test_control bits. See
2572 PAL_SELF_TEST_CONTROL.
2575 UINT64 Attributes
:8;
2577 UINT64 TestControl
:48;
2581 PAL Procedure - PAL_TEST_PROC.
2583 Perform late processor self test. It is required by IPF. The
2584 PAL procedure supports the Static Registers calling
2585 convention. It could be called at physical mode.
2587 @param Index Index of PAL_TEST_PROC within the list of PAL
2589 @param TestAddress 64-bit physical address of main memory
2590 area to be used by processor self-test.
2591 The memory region passed must be
2592 cacheable, bit 63 must be zero.
2593 @param TestInfo Input argument specifying the size of the
2594 memory buffer passed and the phase of the
2595 processor self-test that should be run. See
2597 @param TestParam Input argument specifying the self-test
2598 control word and the allowable memory
2599 attributes that can be used with the memory
2600 buffer. See PAL_TEST_CONTROL.
2602 @retval 1 Call completed without error, but hardware
2603 failures occurred during self-test.
2604 @retval 0 Call completed without error
2605 @retval -2 Invalid argument
2606 @retval -3 Call completed with error.
2608 @return R9 Formatted 8-byte value denoting the state of the
2609 processor after self-test
2612 #define PAL_TEST_PROC 258
2616 @param NumberOfInterruptControllers Number of interrupt
2617 controllers currently
2618 enabled on the system.
2620 @param NumberOfProcessors Number of processors currently
2621 enabled on the system.
2625 UINT32 NumberOfInterruptControllers
;
2626 UINT32 NumberOfProcessors
;
2627 } PAL_PLATFORM_INFO
;
2630 PAL Procedure - PAL_COPY_INFO.
2632 Return information needed to relocate PAL procedures and PAL
2633 PMI code to memory. It is required by IPF. The PAL procedure
2634 supports the Static Registers calling convention. It could be
2635 called at physical mode.
2637 @param Index Index of PAL_COPY_INFO within the list of PAL
2639 @param CopyType Unsigned integer denoting type of procedures
2640 for which copy information is requested.
2641 @param PlatformInfo 8-byte formatted value describing the
2642 number of processors and the number of
2643 interrupt controllers currently enabled
2644 on the system. See PAL_PLATFORM_INFO.
2645 @param McaProcStateInfo Unsigned integer denoting the number
2646 of bytes that SAL needs for the
2647 min-state save area for each
2650 @retval 0 Call completed without error
2651 @retval -2 Invalid argument
2652 @retval -3 Call completed with error.
2654 @return R9 Unsigned integer denoting the number of bytes of
2655 PAL information that must be copied to main
2657 @return R10 Unsigned integer denoting the starting alignment
2658 of the data to be copied.
2661 #define PAL_COPY_INFO 30
2664 PAL Procedure - PAL_COPY_PAL.
2666 Relocate PAL procedures and PAL PMI code to memory. It is
2667 required by IPF. The PAL procedure supports the Stacked
2668 Registers calling convention. It could be called at physical
2671 @param Index Index of PAL_COPY_PAL within the list of PAL
2673 @param TargetAddress Physical address of a memory buffer to
2674 copy relocatable PAL procedures and PAL
2676 @param AllocSize Unsigned integer denoting the size of the
2677 buffer passed by SAL for the copy operation.
2678 @param CopyOption Unsigned integer indicating whether
2679 relocatable PAL code and PAL PMI code
2680 should be copied from firmware address
2681 space to main memory.
2683 @retval 0 Call completed without error
2684 @retval -2 Invalid argument
2685 @retval -3 Call completed with error.
2687 @return R9 Unsigned integer denoting the offset of PAL_PROC
2688 in the relocatable segment copied.
2691 #define PAL_COPY_PAL 256
2694 PAL Procedure - PAL_ENTER_IA_32_ENV.
2696 Enter IA-32 System environment. It is optional. The PAL
2697 procedure supports the Static Registers calling convention.
2698 It could be called at physical mode.
2700 Note: Since this is a special call, it does not follow the PAL
2701 static register calling convention. GR28 contains the index of
2702 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
2703 input arguments including GR29-GR31 are setup by SAL to values
2704 as required by the IA-32 operating system defined in Table
2705 11-67. The registers that are designated as preserved, scratch,
2706 input arguments and procedure return values by the static
2707 procedure calling convention are not followed by this call. For
2708 instance, GR5 and GR6 need not be preserved since these are
2709 regarded as scratch by the IA-32 operating system. Note: In an
2710 MP system, this call must be COMPLETED on the first CPU to enter
2711 the IA-32 System Environment (may or may not be the BSP) prior
2712 to being called on the remaining processors in the MP system.
2714 @param Index GR28 contains the index of the
2715 PAL_ENTER_IA_32_ENV call within the list of PAL
2719 @retval The status is returned in GR4.
2720 -1 - Un-implemented procedure 0 JMPE detected
2723 0 - 1 SAL allocated buffer for IA-32 System
2724 Environment operation is too small
2726 2 - IA-32 Firmware Checksum Error
2728 3 - SAL allocated buffer for IA-32 System
2729 Environment operation is not properly aligned
2731 4 - Error in SAL MP Info Table
2733 5 - Error in SAL Memory Descriptor Table
2735 6 - Error in SAL System Table
2737 7 - Inconsistent IA-32 state
2739 8 - IA-32 Firmware Internal Error
2741 9 - IA-32 Soft Reset (Note: remaining register
2742 state is undefined for this termination
2745 10 - Machine Check Error
2747 11 - Error in SAL I/O Intercept Table
2749 12 - Processor exit due to other processor in
2750 MP system terminating the IA32 system
2751 environment. (Note: remaining register state
2752 is undefined for this termination reason.)
2754 13 - Itanium architecture-based state
2755 corruption by either SAL PMI handler or I/O
2756 Intercept callback function.
2760 #define PAL_ENTER_IA_32_ENV 33
2763 PAL Procedure - PAL_PMI_ENTRYPOINT.
2765 Register PMI memory entrypoints with processor. It is required
2766 by IPF. The PAL procedure supports the Stacked Registers
2767 calling convention. It could be called at physical mode.
2769 @param Index Index of PAL_PMI_ENTRYPOINT within the list of
2771 @param SalPmiEntry 256-byte aligned physical address of SAL
2772 PMI entrypoint in memory.
2774 @retval 0 Call completed without error
2775 @retval -2 Invalid argument
2776 @retval -3 Call completed with error.
2779 #define PAL_PMI_ENTRYPOINT 32
2784 The ASCII brand identification string will be copied to the
2785 address specified in the address input argument. The processor
2786 brand identification string is defined to be a maximum of 128
2787 characters long; 127 bytes will contain characters and the 128th
2788 byte is defined to be NULL (0). A processor may return less than
2789 the 127 ASCII characters as long as the string is null
2790 terminated. The string length will be placed in the brand_info
2794 #define PAL_BRAND_INFO_ID_REQUEST 0
2797 PAL Procedure - PAL_BRAND_INFO.
2799 Provides processor branding information. It is optional by
2800 IPF. The PAL procedure supports the Stacked Registers calling
2801 convention. It could be called at physical and Virtual mode.
2803 @param Index Index of PAL_BRAND_INFO within the list of PAL
2805 @param InfoRequest Unsigned 64-bit integer specifying the
2806 information that is being requested. (See
2807 PAL_BRAND_INFO_ID_REQUEST)
2808 @param Address Unsigned 64-bit integer specifying the
2809 address of the 128-byte block to which the
2810 processor brand string shall be written.
2812 @retval 0 Call completed without error
2813 @retval -1 Unimplemented procedure
2814 @retval -2 Invalid argument
2815 @retval -3 Call completed with error.
2816 @retval -6 Input argument is not implemented.
2818 @return R9 Brand information returned. The format of this
2819 value is dependent on the input values passed.
2822 #define PAL_BRAND_INFO 274
2825 PAL Procedure - PAL_GET_HW_POLICY.
2827 Returns the current hardware resource sharing policy of the
2828 processor. It is optional by IPF. The PAL procedure supports
2829 the Static Registers calling convention. It could be called at
2830 physical and Virtual mode.
2833 @param Index Index of PAL_GET_HW_POLICY within the list of PAL
2835 @param ProcessorNumber Unsigned 64-bit integer that specifies
2836 for which logical processor
2837 information is being requested. This
2838 input argument must be zero for the
2839 first call to this procedure and can
2840 be a maximum value of one less than
2841 the number of logical processors
2842 impacted by the hardware resource
2843 sharing policy, which is returned by
2844 the R10 return value.
2846 @retval 0 Call completed without error
2847 @retval -1 Unimplemented procedure
2848 @retval -2 Invalid argument
2849 @retval -3 Call completed with error.
2850 @retval -9 Call requires PAL memory buffer.
2852 @return R9 Unsigned 64-bit integer representing the current
2853 hardware resource sharing policy.
2854 @return R10 Unsigned 64-bit integer that returns the number
2855 of logical processors impacted by the policy
2857 @return R11 Unsigned 64-bit integer containing the logical
2858 address of one of the logical processors
2859 impacted by policy modification.
2862 #define PAL_GET_HW_POLICY 48
2866 // Value of PAL_SET_HW_POLICY.Policy
2868 #define PAL_SET_HW_POLICY_PERFORMANCE 0
2869 #define PAL_SET_HW_POLICY_FAIRNESS 1
2870 #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
2871 #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
2874 PAL Procedure - PAL_SET_HW_POLICY.
2876 Sets the current hardware resource sharing policy of the
2877 processor. It is optional by IPF. The PAL procedure supports
2878 the Static Registers calling convention. It could be called at
2879 physical and Virtual mode.
2881 @param Index Index of PAL_SET_HW_POLICY within the list of PAL
2883 @param Policy Unsigned 64-bit integer specifying the hardware
2884 resource sharing policy the caller is setting.
2885 See Value of PAL_SET_HW_POLICY.Policy above.
2887 @retval 1 Call completed successfully but could not
2888 change the hardware policy since a
2889 competing logical processor is set in
2890 exclusive high priority.
2891 @retval 0 Call completed without error
2892 @retval -1 Unimplemented procedure
2893 @retval -2 Invalid argument
2894 @retval -3 Call completed with error.
2895 @retval -9 Call requires PAL memory buffer.
2898 #define PAL_SET_HW_POLICY 49
2903 @param Mode Bit2:0, Indicates the mode of operation for this
2904 procedure: 0 - Query mode 1 - Error inject mode
2905 (err_inj should also be specified) 2 - Cancel
2906 outstanding trigger. All other fields in
2907 PAL_MC_ERROR_TYPE_INFO,
2908 PAL_MC_ERROR_STRUCTURE_INFO and
2909 PAL_MC_ERROR_DATA_BUFFER are ignored. All other
2910 values are reserved.
2912 @param ErrorInjection Bit5:3, indicates the mode of error
2913 injection: 0 - Error inject only (no
2914 error consumption) 1 - Error inject
2915 and consume All other values are
2919 @param ErrorSeverity Bit7:6, indicates the severity desired
2920 for error injection/query. Definitions
2921 of the different error severity types
2922 0 - Corrected error 1 - Recoverable
2923 error 2 - Fatal error 3 - Reserved
2926 @param ErrorStructure Bit12:8, Indicates the structure
2927 identification for error
2928 injection/query: 0 - Any structure
2929 (cannot be used during query mode).
2930 When selected, the structure type used
2931 for error injection is determined by
2932 PAL. 1 - Cache 2 - TLB 3 - Register
2933 file 4 - Bus/System interconnect 5-15
2934 - Reserved 16-31 - Processor
2935 specific error injection
2936 capabilities.ErrorDataBuffer is used
2937 to specify error types. Please refer
2938 to the processor specific
2939 documentation for additional details.
2941 @param StructureHierarchy Bit15:13, Indicates the structure
2943 injection/query: 0 - Any level of
2944 hierarchy (cannot be used during
2945 query mode). When selected, the
2946 structure hierarchy used for error
2947 injection is determined by PAL. 1
2948 - Error structure hierarchy
2949 level-1 2 - Error structure
2950 hierarchy level-2 3 - Error
2951 structure hierarchy level-3 4 -
2952 Error structure hierarchy level-4
2953 All other values are reserved.
2954 Reserved 63:16 Reserved
2959 UINT64 ErrorInjection
:3;
2960 UINT64 ErrorSeverity
:2;
2961 UINT64 ErrorStructure
:5;
2962 UINT64 StructureHierarchy
:3;
2964 } PAL_MC_ERROR_TYPE_INFO
;
2968 @param StructInfoIsValid Bit0 When 1, indicates that the
2969 structure information fields
2970 (c_t,cl_p,cl_id) are valid and
2971 should be used for error injection.
2972 When 0, the structure information
2973 fields are ignored, and the values
2974 of these fields used for error
2976 implementation-specific.
2978 @param CacheType Bit2:1 Indicates which cache should be used
2979 for error injection: 0 - Reserved 1 -
2980 Instruction cache 2 - Data or unified cache
2984 @param PortionOfCacheLine Bit5:3 Indicates the portion of the
2985 cache line where the error should
2986 be injected: 0 - Reserved 1 - Tag
2987 2 - Data 3 - mesi All other
2988 values are reserved.
2990 @param Mechanism Bit8:6 Indicates which mechanism is used to
2991 identify the cache line to be used for error
2992 injection: 0 - Reserved 1 - Virtual address
2993 provided in the inj_addr field of the buffer
2994 pointed to by err_data_buffer should be used
2995 to identify the cache line for error
2996 injection. 2 - Physical address provided in
2997 the inj_addr field of the buffer pointed to
2998 by err_data_buffershould be used to identify
2999 the cache line for error injection. 3 - way
3000 and index fields provided in err_data_buffer
3001 should be used to identify the cache line
3002 for error injection. All other values are
3005 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a
3006 multiple bit, non-correctable
3007 error should be injected in the
3008 cache line specified by cl_id.
3009 If this injected error is not
3010 consumed, it may eventually
3011 cause a data-poisoning event
3012 resulting in a corrected error
3013 signal, when the associated
3014 cache line is cast out (implicit
3015 or explicit write-back of the
3016 cache line). The error severity
3017 specified by err_sev in
3018 err_type_info must be set to 0
3019 (corrected error) when this bit
3023 @param TrigerInfoIsValid Bit32 When 1, indicates that the
3024 trigger information fields (trigger,
3025 trigger_pl) are valid and should be
3026 used for error injection. When 0,
3027 the trigger information fields are
3028 ignored and error injection is
3029 performed immediately.
3031 @param Triger Bit36:33 Indicates the operation type to be
3032 used as the error trigger condition. The
3033 address corresponding to the trigger is
3034 specified in the trigger_addr field of the
3035 buffer pointed to by err_data_buffer: 0 -
3036 Instruction memory access. The trigger match
3037 conditions for this operation type are similar
3038 to the IBR address breakpoint match conditions
3039 1 - Data memory access. The trigger match
3040 conditions for this operation type are similar
3041 to the DBR address breakpoint match conditions
3042 All other values are reserved.
3044 @param PrivilegeOfTriger Bit39:37 Indicates the privilege
3045 level of the context during which
3046 the error should be injected: 0 -
3047 privilege level 0 1 - privilege
3048 level 1 2 - privilege level 2 3 -
3049 privilege level 3 All other values
3050 are reserved. If the implementation
3051 does not support privilege level
3052 qualifier for triggers (i.e. if
3053 trigger_pl is 0 in the capabilities
3054 vector), this field is ignored and
3055 triggers can be taken at any
3060 UINT64 StructInfoIsValid
:1;
3062 UINT64 PortionOfCacheLine
:3;
3064 UINT64 DataPoisonOfCacheLine
:1;
3065 UINT64 Reserved1
:22;
3066 UINT64 TrigerInfoIsValid
:1;
3068 UINT64 PrivilegeOfTriger
:3;
3069 UINT64 Reserved2
:24;
3070 } PAL_MC_ERROR_STRUCT_INFO
;
3074 Buffer Pointed to by err_data_buffer - TLB
3078 UINT64 TrigerAddress
;
3079 UINT64 VirtualPageNumber
:52;
3082 UINT64 Reserved2
:40;
3083 } PAL_MC_ERROR_DATA_BUFFER_TLB
;
3086 PAL Procedure - PAL_MC_ERROR_INJECT.
3088 Injects the requested processor error or returns information
3089 on the supported injection capabilities for this particular
3090 processor implementation. It is optional by IPF. The PAL
3091 procedure supports the Stacked Registers calling convention.
3092 It could be called at physical and Virtual mode.
3094 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
3096 @param ErrorTypeInfo Unsigned 64-bit integer specifying the
3097 first level error information which
3098 identifies the error structure and
3099 corresponding structure hierarchy, and
3101 @param ErrorStructInfo Unsigned 64-bit integer identifying
3102 the optional structure specific
3103 information that provides the second
3104 level details for the requested error.
3105 @param ErrorDataBuffer 64-bit physical address of a buffer
3106 providing additional parameters for
3107 the requested error. The address of
3108 this buffer must be 8-byte aligned.
3110 @retval 0 Call completed without error
3111 @retval -1 Unimplemented procedure
3112 @retval -2 Invalid argument
3113 @retval -3 Call completed with error.
3114 @retval -4 Call completed with error; the requested
3115 error could not be injected due to failure in
3116 locating the target location in the specified
3118 @retval -5 Argument was valid, but requested error
3119 injection capability is not supported.
3120 @retval -9 Call requires PAL memory buffer.
3122 @return R9 64-bit vector specifying the supported error
3123 injection capabilities for the input argument
3124 combination of struct_hier, err_struct and
3125 err_sev fields in ErrorTypeInfo.
3126 @return R10 64-bit vector specifying the architectural
3127 resources that are used by the procedure.
3130 #define PAL_MC_ERROR_INJECT 276
3134 // Types of PAL_GET_PSTATE.Type
3136 #define PAL_GET_PSTATE_RECENT 0
3137 #define PAL_GET_PSTATE_AVERAGE_NEW_START 1
3138 #define PAL_GET_PSTATE_AVERAGE 2
3139 #define PAL_GET_PSTATE_NOW 3
3142 PAL Procedure - PAL_GET_PSTATE.
3144 Returns the performance index of the processor. It is optional
3145 by IPF. The PAL procedure supports the Stacked Registers
3146 calling convention. It could be called at physical and Virtual
3149 @param Index Index of PAL_GET_PSTATE within the list of PAL
3151 @param Type Type of performance_index value to be returned
3152 by this procedure.See PAL_GET_PSTATE.Type above.
3154 @retval 1 Call completed without error, but accuracy
3155 of performance index has been impacted by a
3156 thermal throttling event, or a
3157 hardware-initiated event.
3158 @retval 0 Call completed without error
3159 @retval -1 Unimplemented procedure
3160 @retval -2 Invalid argument
3161 @retval -3 Call completed with error.
3162 @retval -9 Call requires PAL memory buffer.
3164 @return R9 Unsigned integer denoting the processor
3165 performance for the time duration since the last
3166 PAL_GET_PSTATE procedure call was made. The
3167 value returned is between 0 and 100, and is
3168 relative to the performance index of the highest
3172 #define PAL_GET_PSTATE 262
3176 Layout of PAL_PSTATE_INFO.PStateBuffer
3180 UINT32 PerformanceIndex
:7;
3182 UINT32 TypicalPowerDissipation
:20;
3183 UINT32 TransitionLatency1
;
3184 UINT32 TransitionLatency2
;
3186 } PAL_PSTATE_INFO_BUFFER
;
3190 PAL Procedure - PAL_PSTATE_INFO.
3192 Returns information about the P-states supported by the
3193 processor. It is optional by IPF. The PAL procedure supports
3194 the Static Registers calling convention. It could be called
3195 at physical and Virtual mode.
3197 @param Index Index of PAL_PSTATE_INFO within the list of PAL
3199 @param PStateBuffer 64-bit pointer to a 256-byte buffer
3200 aligned on an 8-byte boundary. See
3201 PAL_PSTATE_INFO_BUFFER above.
3203 @retval 0 Call completed without error
3204 @retval -1 Unimplemented procedure
3205 @retval -2 Invalid argument
3206 @retval -3 Call completed with error.
3208 @return R9 Unsigned integer denoting the number of P-states
3209 supported. The maximum value of this field is 16.
3210 @return R10 Dependency domain information
3213 #define PAL_PSTATE_INFO 44
3217 PAL Procedure - PAL_SET_PSTATE.
3219 To request a processor transition to a given P-state. It is
3220 optional by IPF. The PAL procedure supports the Stacked
3221 Registers calling convention. It could be called at physical
3224 @param Index Index of PAL_SET_PSTATE within the list of PAL
3226 @param PState Unsigned integer denoting the processor
3227 P-state being requested.
3228 @param ForcePState Unsigned integer denoting whether the
3229 P-state change should be forced for the
3232 @retval 1 Call completed without error, but
3233 transition request was not accepted
3234 @retval 0 Call completed without error
3235 @retval -1 Unimplemented procedure
3236 @retval -2 Invalid argument
3237 @retval -3 Call completed with error.
3238 @retval -9 Call requires PAL memory buffer.
3241 #define PAL_SET_PSTATE 263
3244 PAL Procedure - PAL_SHUTDOWN.
3246 Put the logical processor into a low power state which can be
3247 exited only by a reset event. It is optional by IPF. The PAL
3248 procedure supports the Static Registers calling convention. It
3249 could be called at physical mode.
3251 @param Index Index of PAL_SHUTDOWN within the list of PAL
3253 @param NotifyPlatform 8-byte aligned physical address
3254 pointer providing details on how to
3255 optionally notify the platform that
3256 the processor is entering a shutdown
3259 @retval -1 Unimplemented procedure
3260 @retval -2 Invalid argument
3261 @retval -3 Call completed with error.
3262 @retval -9 Call requires PAL memory buffer.
3265 #define PAL_SHUTDOWN 45
3269 Layout of PAL_MEMORY_BUFFER.ControlWord
3273 UINT64 Registration
:1;
3274 UINT64 ProbeInterrupt
:1;
3276 } PAL_MEMORY_CONTROL_WORD
;
3279 PAL Procedure - PAL_MEMORY_BUFFER.
3281 Provides cacheable memory to PAL for exclusive use during
3282 runtime. It is optional by IPF. The PAL procedure supports the
3283 Static Registers calling convention. It could be called at
3286 @param Index Index of PAL_MEMORY_BUFFER within the list of PAL
3288 @param BaseAddress Physical address of the memory buffer
3289 allocated for PAL use.
3290 @param AllocSize Unsigned integer denoting the size of the
3292 @param ControlWord Formatted bit vector that provides control
3293 options for this procedure. See
3294 PAL_MEMORY_CONTROL_WORD above.
3296 @retval 1 Call has not completed a buffer relocation
3297 due to a pending interrupt
3298 @retval 0 Call completed without error
3299 @retval -1 Unimplemented procedure
3300 @retval -2 Invalid argument
3301 @retval -3 Call completed with error.
3302 @retval -9 Call requires PAL memory buffer.
3304 @return R9 Returns the minimum size of the memory buffer
3305 required if the alloc_size input argument was
3309 #define PAL_MEMORY_BUFFER 277
3313 PAL Procedure - PAL_VP_CREATE.
3315 Initializes a new vpd for the operation of a new virtual
3316 processor in the virtual environment. It is optional by IPF.
3317 The PAL procedure supports the Stacked Registers calling
3318 convention. It could be called at Virtual mode.
3320 @param Index Index of PAL_VP_CREATE within the list of PAL
3322 @param Vpd 64-bit host virtual pointer to the Virtual
3323 Processor Descriptor (VPD).
3324 @param HostIva 64-bit host virtual pointer to the host IVT
3325 for the virtual processor
3326 @param OptionalHandler 64-bit non-zero host-virtual pointer
3327 to an optional handler for
3328 virtualization intercepts.
3330 @retval 0 Call completed without error
3331 @retval -1 Unimplemented procedure
3332 @retval -2 Invalid argument
3333 @retval -3 Call completed with error.
3334 @retval -9 Call requires PAL memory buffer.
3337 #define PAL_VP_CREATE 265
3341 Virtual Environment Information Parameter
3348 } PAL_VP_ENV_INFO_RETURN
;
3351 PAL Procedure - PAL_VP_ENV_INFO.
3353 Returns the parameters needed to enter a virtual environment.
3354 It is optional by IPF. The PAL procedure supports the Stacked
3355 Registers calling convention. It could be called at Virtual
3358 @param Index Index of PAL_VP_ENV_INFO within the list of PAL
3360 @param Vpd 64-bit host virtual pointer to the Virtual
3361 Processor Descriptor (VPD).
3362 @param HostIva 64-bit host virtual pointer to the host IVT
3363 for the virtual processor
3364 @param OptionalHandler 64-bit non-zero host-virtual pointer
3365 to an optional handler for
3366 virtualization intercepts.
3368 @retval 0 Call completed without error
3369 @retval -1 Unimplemented procedure
3370 @retval -2 Invalid argument
3371 @retval -3 Call completed with error.
3372 @retval -9 Call requires PAL memory buffer.
3374 @return R9 Unsigned integer denoting the number of bytes
3375 required by the PAL virtual environment buffer
3376 during PAL_VP_INIT_ENV
3377 @return R10 64-bit vector of virtual environment
3378 information. See PAL_VP_ENV_INFO_RETURN.
3382 #define PAL_VP_ENV_INFO 266
3385 PAL Procedure - PAL_VP_EXIT_ENV.
3387 Allows a logical processor to exit a virtual environment.
3388 It is optional by IPF. The PAL procedure supports the Stacked
3389 Registers calling convention. It could be called at Virtual
3392 @param Index Index of PAL_VP_EXIT_ENV within the list of PAL
3394 @param Iva Optional 64-bit host virtual pointer to the IVT
3395 when this procedure is done
3397 @retval 0 Call completed without error
3398 @retval -1 Unimplemented procedure
3399 @retval -2 Invalid argument
3400 @retval -3 Call completed with error.
3401 @retval -9 Call requires PAL memory buffer.
3404 #define PAL_VP_EXIT_ENV 267
3409 PAL Procedure - PAL_VP_INIT_ENV.
3411 Allows a logical processor to enter a virtual environment. It
3412 is optional by IPF. The PAL procedure supports the Stacked
3413 Registers calling convention. It could be called at Virtual
3416 @param Index Index of PAL_VP_INIT_ENV within the list of PAL
3418 @param ConfigOptions 64-bit vector of global configuration
3420 @param PhysicalBase Host physical base address of a block of
3421 contiguous physical memory for the PAL
3422 virtual environment buffer 1) This
3423 memory area must be allocated by the VMM
3424 and be 4K aligned. The first logical
3425 processor to enter the environment will
3426 initialize the physical block for
3427 virtualization operations.
3428 @param VirtualBase Host virtual base address of the
3429 corresponding physical memory block for
3430 the PAL virtual environment buffer : The
3431 VMM must maintain the host virtual to host
3432 physical data and instruction translations
3433 in TRs for addresses within the allocated
3434 address space. Logical processors in this
3435 virtual environment will use this address
3436 when transitioning to virtual mode
3439 @retval 0 Call completed without error
3440 @retval -1 Unimplemented procedure
3441 @retval -2 Invalid argument
3442 @retval -3 Call completed with error.
3443 @retval -9 Call requires PAL memory buffer.
3445 @return R9 Virtualization Service Address - VSA specifies
3446 the virtual base address of the PAL
3447 virtualization services in this virtual
3452 #define PAL_VP_INIT_ENV 268
3456 PAL Procedure - PAL_VP_REGISTER.
3458 Register a different host IVT and/or a different optional
3459 virtualization intercept handler for the virtual processor
3460 specified by vpd. It is optional by IPF. The PAL procedure
3461 supports the Stacked Registers calling convention. It could be
3462 called at Virtual mode.
3464 @param Index Index of PAL_VP_REGISTER within the list of PAL
3466 @param Vpd 64-bit host virtual pointer to the Virtual
3467 Processor Descriptor (VPD) host_iva 64-bit host
3468 virtual pointer to the host IVT for the virtual
3470 @param OptionalHandler 64-bit non-zero host-virtual pointer
3471 to an optional handler for
3472 virtualization intercepts.
3474 @retval 0 Call completed without error
3475 @retval -1 Unimplemented procedure
3476 @retval -2 Invalid argument
3477 @retval -3 Call completed with error.
3478 @retval -9 Call requires PAL memory buffer.
3481 #define PAL_VP_REGISTER 269
3485 PAL Procedure - PAL_VP_RESTORE.
3487 Restores virtual processor state for the specified vpd on the
3488 logical processor. It is optional by IPF. The PAL procedure
3489 supports the Stacked Registers calling convention. It could be
3490 called at Virtual mode.
3492 @param Index Index of PAL_VP_RESTORE within the list of PAL
3494 @param Vpd 64-bit host virtual pointer to the Virtual
3495 Processor Descriptor (VPD) host_iva 64-bit host
3496 virtual pointer to the host IVT for the virtual
3498 @param PalVector Vector specifies PAL procedure
3499 implementation-specific state to be
3502 @retval 0 Call completed without error
3503 @retval -1 Unimplemented procedure
3504 @retval -2 Invalid argument
3505 @retval -3 Call completed with error.
3506 @retval -9 Call requires PAL memory buffer.
3509 #define PAL_VP_RESTORE 270
3512 PAL Procedure - PAL_VP_SAVE.
3514 Saves virtual processor state for the specified vpd on the
3515 logical processor. It is optional by IPF. The PAL procedure
3516 supports the Stacked Registers calling convention. It could be
3517 called at Virtual mode.
3519 @param Index Index of PAL_VP_SAVE within the list of PAL
3521 @param Vpd 64-bit host virtual pointer to the Virtual
3522 Processor Descriptor (VPD) host_iva 64-bit host
3523 virtual pointer to the host IVT for the virtual
3525 @param PalVector Vector specifies PAL procedure
3526 implementation-specific state to be
3529 @retval 0 Call completed without error
3530 @retval -1 Unimplemented procedure
3531 @retval -2 Invalid argument
3532 @retval -3 Call completed with error.
3533 @retval -9 Call requires PAL memory buffer.
3536 #define PAL_VP_SAVE 271
3540 PAL Procedure - PAL_VP_TERMINATE.
3542 Terminates operation for the specified virtual processor. It
3543 is optional by IPF. The PAL procedure supports the Stacked
3544 Registers calling convention. It could be called at Virtual
3547 @param Index Index of PAL_VP_TERMINATE within the list of PAL
3549 @param Vpd 64-bit host virtual pointer to the Virtual
3550 Processor Descriptor (VPD)
3551 @param Iva Optional 64-bit host virtual pointer to the IVT
3552 when this procedure is done.
3554 @retval 0 Call completed without error
3555 @retval -1 Unimplemented procedure
3556 @retval -2 Invalid argument
3557 @retval -3 Call completed with error.
3558 @retval -9 Call requires PAL memory buffer.
3561 #define PAL_VP_TERMINATE 272