2 Support for PCI 2.2 standard.
4 This file includes the definitions in the following specifications,
5 PCI Local Bus Specification, 2.2
6 PCI-to-PCI Bridge Architecture Specification, Revision 1.2
9 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
23 #define PCI_MAX_BUS 255
24 #define PCI_MAX_DEVICE 31
25 #define PCI_MAX_FUNC 7
30 /// Common header region in PCI Configuration Space
31 /// Section 6.1, PCI Local Bus Specification, 2.2
44 } PCI_DEVICE_INDEPENDENT_REGION
;
47 /// PCI Device header region in PCI Configuration Space
48 /// Section 6.1, PCI Local Bus Specification, 2.2
53 UINT16 SubsystemVendorID
;
55 UINT32 ExpansionRomBar
;
63 } PCI_DEVICE_HEADER_TYPE_REGION
;
66 /// PCI Device Configuration Space
67 /// Section 6.1, PCI Local Bus Specification, 2.2
70 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
71 PCI_DEVICE_HEADER_TYPE_REGION Device
;
75 /// PCI-PCI Bridge header region in PCI Configuration Space
76 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
83 UINT8 SecondaryLatencyTimer
;
86 UINT16 SecondaryStatus
;
89 UINT16 PrefetchableMemoryBase
;
90 UINT16 PrefetchableMemoryLimit
;
91 UINT32 PrefetchableBaseUpper32
;
92 UINT32 PrefetchableLimitUpper32
;
94 UINT16 IoLimitUpper16
;
97 UINT32 ExpansionRomBAR
;
100 UINT16 BridgeControl
;
101 } PCI_BRIDGE_CONTROL_REGISTER
;
104 /// PCI-to-PCI Bridge Configuration Space
105 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
108 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
109 PCI_BRIDGE_CONTROL_REGISTER Bridge
;
118 /// CardBus Conroller Configuration Space,
119 /// Section 4.5.1, PC Card Standard. 8.0
122 UINT32 CardBusSocketReg
; ///< Cardus Socket/ExCA Base
125 UINT16 SecondaryStatus
; ///< Secondary Status
126 UINT8 PciBusNumber
; ///< PCI Bus Number
127 UINT8 CardBusBusNumber
; ///< CardBus Bus Number
128 UINT8 SubordinateBusNumber
; ///< Subordinate Bus Number
129 UINT8 CardBusLatencyTimer
; ///< CardBus Latency Timer
130 UINT32 MemoryBase0
; ///< Memory Base Register 0
131 UINT32 MemoryLimit0
; ///< Memory Limit Register 0
135 UINT32 IoLimit0
; ///< I/O Base Register 0
136 UINT32 IoBase1
; ///< I/O Limit Register 0
138 UINT8 InterruptLine
; ///< Interrupt Line
139 UINT8 InterruptPin
; ///< Interrupt Pin
140 UINT16 BridgeControl
; ///< Bridge Control
141 } PCI_CARDBUS_CONTROL_REGISTER
;
144 // Definitions of PCI class bytes and manipulation macros.
146 #define PCI_CLASS_OLD 0x00
147 #define PCI_CLASS_OLD_OTHER 0x00
148 #define PCI_CLASS_OLD_VGA 0x01
150 #define PCI_CLASS_MASS_STORAGE 0x01
151 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
152 #define PCI_CLASS_MASS_STORAGE_IDE 0x01
153 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
154 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
155 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
156 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
158 #define PCI_CLASS_NETWORK 0x02
159 #define PCI_CLASS_NETWORK_ETHERNET 0x00
160 #define PCI_CLASS_NETWORK_TOKENRING 0x01
161 #define PCI_CLASS_NETWORK_FDDI 0x02
162 #define PCI_CLASS_NETWORK_ATM 0x03
163 #define PCI_CLASS_NETWORK_ISDN 0x04
164 #define PCI_CLASS_NETWORK_OTHER 0x80
166 #define PCI_CLASS_DISPLAY 0x03
167 #define PCI_CLASS_DISPLAY_VGA 0x00
168 #define PCI_IF_VGA_VGA 0x00
169 #define PCI_IF_VGA_8514 0x01
170 #define PCI_CLASS_DISPLAY_XGA 0x01
171 #define PCI_CLASS_DISPLAY_3D 0x02
172 #define PCI_CLASS_DISPLAY_OTHER 0x80
174 #define PCI_CLASS_MEDIA 0x04
175 #define PCI_CLASS_MEDIA_VIDEO 0x00
176 #define PCI_CLASS_MEDIA_AUDIO 0x01
177 #define PCI_CLASS_MEDIA_TELEPHONE 0x02
178 #define PCI_CLASS_MEDIA_OTHER 0x80
180 #define PCI_CLASS_MEMORY_CONTROLLER 0x05
181 #define PCI_CLASS_MEMORY_RAM 0x00
182 #define PCI_CLASS_MEMORY_FLASH 0x01
183 #define PCI_CLASS_MEMORY_OTHER 0x80
185 #define PCI_CLASS_BRIDGE 0x06
186 #define PCI_CLASS_BRIDGE_HOST 0x00
187 #define PCI_CLASS_BRIDGE_ISA 0x01
188 #define PCI_CLASS_BRIDGE_EISA 0x02
189 #define PCI_CLASS_BRIDGE_MCA 0x03
190 #define PCI_CLASS_BRIDGE_P2P 0x04
191 #define PCI_IF_BRIDGE_P2P 0x00
192 #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
193 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
194 #define PCI_CLASS_BRIDGE_NUBUS 0x06
195 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
196 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
197 #define PCI_CLASS_BRIDGE_OTHER 0x80
198 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
200 #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
201 #define PCI_SUBCLASS_SERIAL 0x00
202 #define PCI_IF_GENERIC_XT 0x00
203 #define PCI_IF_16450 0x01
204 #define PCI_IF_16550 0x02
205 #define PCI_IF_16650 0x03
206 #define PCI_IF_16750 0x04
207 #define PCI_IF_16850 0x05
208 #define PCI_IF_16950 0x06
209 #define PCI_SUBCLASS_PARALLEL 0x01
210 #define PCI_IF_PARALLEL_PORT 0x00
211 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
212 #define PCI_IF_ECP_PARALLEL_PORT 0x02
213 #define PCI_IF_1284_CONTROLLER 0x03
214 #define PCI_IF_1284_DEVICE 0xFE
215 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
216 #define PCI_SUBCLASS_MODEM 0x03
217 #define PCI_IF_GENERIC_MODEM 0x00
218 #define PCI_IF_16450_MODEM 0x01
219 #define PCI_IF_16550_MODEM 0x02
220 #define PCI_IF_16650_MODEM 0x03
221 #define PCI_IF_16750_MODEM 0x04
222 #define PCI_SUBCLASS_SCC_OTHER 0x80
224 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
225 #define PCI_SUBCLASS_PIC 0x00
226 #define PCI_IF_8259_PIC 0x00
227 #define PCI_IF_ISA_PIC 0x01
228 #define PCI_IF_EISA_PIC 0x02
229 #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
230 #define PCI_IF_APIC_CONTROLLER2 0x20
231 #define PCI_SUBCLASS_DMA 0x01
232 #define PCI_IF_8237_DMA 0x00
233 #define PCI_IF_ISA_DMA 0x01
234 #define PCI_IF_EISA_DMA 0x02
235 #define PCI_SUBCLASS_TIMER 0x02
236 #define PCI_IF_8254_TIMER 0x00
237 #define PCI_IF_ISA_TIMER 0x01
238 #define PCI_IF_EISA_TIMER 0x02
239 #define PCI_SUBCLASS_RTC 0x03
240 #define PCI_IF_GENERIC_RTC 0x00
241 #define PCI_IF_ISA_RTC 0x01
242 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
243 #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
245 #define PCI_CLASS_INPUT_DEVICE 0x09
246 #define PCI_SUBCLASS_KEYBOARD 0x00
247 #define PCI_SUBCLASS_PEN 0x01
248 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
249 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
250 #define PCI_SUBCLASS_GAMEPORT 0x04
251 #define PCI_IF_GAMEPORT 0x00
252 #define PCI_IF_GAMEPORT1 0x10
253 #define PCI_SUBCLASS_INPUT_OTHER 0x80
255 #define PCI_CLASS_DOCKING_STATION 0x0A
256 #define PCI_SUBCLASS_DOCKING_GENERIC 0x00
257 #define PCI_SUBCLASS_DOCKING_OTHER 0x80
259 #define PCI_CLASS_PROCESSOR 0x0B
260 #define PCI_SUBCLASS_PROC_386 0x00
261 #define PCI_SUBCLASS_PROC_486 0x01
262 #define PCI_SUBCLASS_PROC_PENTIUM 0x02
263 #define PCI_SUBCLASS_PROC_ALPHA 0x10
264 #define PCI_SUBCLASS_PROC_POWERPC 0x20
265 #define PCI_SUBCLASS_PROC_MIPS 0x30
266 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
268 #define PCI_CLASS_SERIAL 0x0C
269 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
270 #define PCI_IF_1394 0x00
271 #define PCI_IF_1394_OPEN_HCI 0x10
272 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
273 #define PCI_CLASS_SERIAL_SSA 0x02
274 #define PCI_CLASS_SERIAL_USB 0x03
275 #define PCI_IF_UHCI 0x00
276 #define PCI_IF_OHCI 0x10
277 #define PCI_IF_USB_OTHER 0x80
278 #define PCI_IF_USB_DEVICE 0xFE
279 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
280 #define PCI_CLASS_SERIAL_SMB 0x05
282 #define PCI_CLASS_WIRELESS 0x0D
283 #define PCI_SUBCLASS_IRDA 0x00
284 #define PCI_SUBCLASS_IR 0x01
285 #define PCI_SUBCLASS_RF 0x10
286 #define PCI_SUBCLASS_WIRELESS_OTHER 0x80
288 #define PCI_CLASS_INTELLIGENT_IO 0x0E
290 #define PCI_CLASS_SATELLITE 0x0F
291 #define PCI_SUBCLASS_TV 0x01
292 #define PCI_SUBCLASS_AUDIO 0x02
293 #define PCI_SUBCLASS_VOICE 0x03
294 #define PCI_SUBCLASS_DATA 0x04
296 #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
297 #define PCI_SUBCLASS_NET_COMPUT 0x00
298 #define PCI_SUBCLASS_ENTERTAINMENT 0x10
299 #define PCI_SUBCLASS_SECURITY_OTHER 0x80
301 #define PCI_CLASS_DPIO 0x11
302 #define PCI_SUBCLASS_DPIO 0x00
303 #define PCI_SUBCLASS_DPIO_OTHER 0x80
306 Macro that checks whether the Base Class code of device matched.
308 @param _p Specified device.
309 @param c Base Class code needs matching.
311 @retval TRUE Base Class code matches the specified device.
312 @retval FALSE Base Class code doesn't match the specified device.
315 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
317 Macro that checks whether the Base Class code and Sub-Class code of device matched.
319 @param _p Specified device.
320 @param c Base Class code needs matching.
321 @param s Sub-Class code needs matching.
323 @retval TRUE Base Class code and Sub-Class code match the specified device.
324 @retval FALSE Base Class code and Sub-Class code don't match the specified device.
327 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
329 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
331 @param _p Specified device.
332 @param c Base Class code needs matching.
333 @param s Sub-Class code needs matching.
334 @param p Interface code needs matching.
336 @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
337 @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
340 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
343 Macro that checks whether device is a display controller.
345 @param _p Specified device.
347 @retval TRUE Device is a display controller.
348 @retval FALSE Device is not a display controller.
351 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
353 Macro that checks whether device is a VGA-compatible controller.
355 @param _p Specified device.
357 @retval TRUE Device is a VGA-compatible controller.
358 @retval FALSE Device is not a VGA-compatible controller.
361 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
363 Macro that checks whether device is an 8514-compatible controller.
365 @param _p Specified device.
367 @retval TRUE Device is an 8514-compatible controller.
368 @retval FALSE Device is not an 8514-compatible controller.
371 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
373 Macro that checks whether device is built before the Class Code field was defined.
375 @param _p Specified device.
377 @retval TRUE Device is an old device.
378 @retval FALSE Device is not an old device.
381 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
383 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
385 @param _p Specified device.
387 @retval TRUE Device is an old VGA-compatible device.
388 @retval FALSE Device is not an old VGA-compatible device.
391 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
393 Macro that checks whether device is an IDE controller.
395 @param _p Specified device.
397 @retval TRUE Device is an IDE controller.
398 @retval FALSE Device is not an IDE controller.
401 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
403 Macro that checks whether device is a SCSI bus controller.
405 @param _p Specified device.
407 @retval TRUE Device is a SCSI bus controller.
408 @retval FALSE Device is not a SCSI bus controller.
411 #define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
413 Macro that checks whether device is a RAID controller.
415 @param _p Specified device.
417 @retval TRUE Device is a RAID controller.
418 @retval FALSE Device is not a RAID controller.
421 #define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
423 Macro that checks whether device is an ISA bridge.
425 @param _p Specified device.
427 @retval TRUE Device is an ISA bridge.
428 @retval FALSE Device is not an ISA bridge.
431 #define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
433 Macro that checks whether device is a PCI-to-PCI bridge.
435 @param _p Specified device.
437 @retval TRUE Device is a PCI-to-PCI bridge.
438 @retval FALSE Device is not a PCI-to-PCI bridge.
441 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
443 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
445 @param _p Specified device.
447 @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
448 @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
451 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
453 Macro that checks whether device is a 16550-compatible serial controller.
455 @param _p Specified device.
457 @retval TRUE Device is a 16550-compatible serial controller.
458 @retval FALSE Device is not a 16550-compatible serial controller.
461 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
463 Macro that checks whether device is a Universal Serial Bus controller.
465 @param _p Specified device.
467 @retval TRUE Device is a Universal Serial Bus controller.
468 @retval FALSE Device is not a Universal Serial Bus controller.
471 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
474 // the definition of Header Type
476 #define HEADER_TYPE_DEVICE 0x00
477 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
478 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
479 #define HEADER_TYPE_MULTI_FUNCTION 0x80
481 // Mask of Header type
483 #define HEADER_LAYOUT_CODE 0x7f
485 Macro that checks whether device is a PCI-PCI bridge.
487 @param _p Specified device.
489 @retval TRUE Device is a PCI-PCI bridge.
490 @retval FALSE Device is not a PCI-PCI bridge.
493 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
495 Macro that checks whether device is a CardBus bridge.
497 @param _p Specified device.
499 @retval TRUE Device is a CardBus bridge.
500 @retval FALSE Device is not a CardBus bridge.
503 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
505 Macro that checks whether device is a multiple functions device.
507 @param _p Specified device.
509 @retval TRUE Device is a multiple functions device.
510 @retval FALSE Device is not a multiple functions device.
513 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
516 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
518 #define PCI_BRIDGE_ROMBAR 0x38
520 #define PCI_MAX_BAR 0x0006
521 #define PCI_MAX_CONFIG_OFFSET 0x0100
523 #define PCI_VENDOR_ID_OFFSET 0x00
524 #define PCI_DEVICE_ID_OFFSET 0x02
525 #define PCI_COMMAND_OFFSET 0x04
526 #define PCI_PRIMARY_STATUS_OFFSET 0x06
527 #define PCI_REVISION_ID_OFFSET 0x08
528 #define PCI_CLASSCODE_OFFSET 0x09
529 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
530 #define PCI_LATENCY_TIMER_OFFSET 0x0D
531 #define PCI_HEADER_TYPE_OFFSET 0x0E
532 #define PCI_BIST_OFFSET 0x0F
533 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
534 #define PCI_CARDBUS_CIS_OFFSET 0x28
535 #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
536 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
537 #define PCI_SID_OFFSET 0x2E ///< SubSystem ID
538 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
539 #define PCI_EXPANSION_ROM_BASE 0x30
540 #define PCI_CAPBILITY_POINTER_OFFSET 0x34
541 #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
542 #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
543 #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
544 #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
547 // defined in PCI-to-PCI Bridge Architecture Specification
549 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
550 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
551 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
552 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
553 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
556 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
558 #define PCI_INT_LINE_UNKNOWN 0xFF
561 /// PCI Access Data Format
573 } PCI_CONFIG_ACCESS_CF8
;
577 #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
578 #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
579 #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
580 #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
581 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
582 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
583 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
584 #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
585 #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
586 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
589 // defined in PCI-to-PCI Bridge Architecture Specification
591 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
592 #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
593 #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
594 #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008
595 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010
596 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020
597 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040
598 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
599 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100
600 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
601 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
602 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
605 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
607 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
608 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
609 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
610 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
613 // Following are the PCI status control bit
615 #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
616 #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
617 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
618 #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
621 /// defined in PC Card Standard
623 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
627 // PCI Capability List IDs and records
629 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
630 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
631 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
632 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
633 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
634 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
637 /// Capabilities List Header
638 /// Section 6.7, PCI Local Bus Specification, 2.2
643 } EFI_PCI_CAPABILITY_HDR
;
646 /// Power Management Register Block Definition
647 /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
650 EFI_PCI_CAPABILITY_HDR Hdr
;
653 UINT8 BridgeExtention
;
655 } EFI_PCI_CAPABILITY_PMI
;
659 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
662 EFI_PCI_CAPABILITY_HDR Hdr
;
667 } EFI_PCI_CAPABILITY_AGP
;
670 /// VPD Capability Structure
671 /// Appendix I, PCI Local Bus Specification, 2.2
674 EFI_PCI_CAPABILITY_HDR Hdr
;
677 } EFI_PCI_CAPABILITY_VPD
;
680 /// Slot Numbering Capabilities Register
681 /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
684 EFI_PCI_CAPABILITY_HDR Hdr
;
687 } EFI_PCI_CAPABILITY_SLOTID
;
690 /// Message Capability Structure for 32-bit Message Address
691 /// Section 6.8.1, PCI Local Bus Specification, 2.2
694 EFI_PCI_CAPABILITY_HDR Hdr
;
698 } EFI_PCI_CAPABILITY_MSI32
;
701 /// Message Capability Structure for 64-bit Message Address
702 /// Section 6.8.1, PCI Local Bus Specification, 2.2
705 EFI_PCI_CAPABILITY_HDR Hdr
;
707 UINT32 MsgAddrRegLsdw
;
708 UINT32 MsgAddrRegMsdw
;
710 } EFI_PCI_CAPABILITY_MSI64
;
713 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
714 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
717 EFI_PCI_CAPABILITY_HDR Hdr
;
719 /// not finished - fields need to go here
721 } EFI_PCI_CAPABILITY_HOTPLUG
;
723 #define DEVICE_ID_NOCARE 0xFFFF
725 #define PCI_ACPI_UNUSED 0
726 #define PCI_BAR_NOCHANGE 0
727 #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
728 #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
729 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
730 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
732 #define PCI_BAR_IDX0 0x00
733 #define PCI_BAR_IDX1 0x01
734 #define PCI_BAR_IDX2 0x02
735 #define PCI_BAR_IDX3 0x03
736 #define PCI_BAR_IDX4 0x04
737 #define PCI_BAR_IDX5 0x05
738 #define PCI_BAR_ALL 0xFF
741 /// EFI PCI Option ROM definitions
743 #define EFI_ROOT_BRIDGE_LIST 'eprb'
744 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
746 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
747 #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
748 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
749 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
752 /// Standard PCI Expansion ROM Header
753 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
756 UINT16 Signature
; ///< 0xaa55
757 UINT8 Reserved
[0x16];
759 } PCI_EXPANSION_ROM_HEADER
;
762 /// Legacy ROM Header Extensions
763 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
766 UINT16 Signature
; ///< 0xaa55
768 UINT8 InitEntryPoint
[3];
769 UINT8 Reserved
[0x12];
771 } EFI_LEGACY_EXPANSION_ROM_HEADER
;
774 /// PCI Data Structure Format
775 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
778 UINT32 Signature
; ///< "PCIR"
790 } PCI_DATA_STRUCTURE
;
793 /// EFI PCI Expansion ROM Header
794 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
797 UINT16 Signature
; ///< 0xaa55
798 UINT16 InitializationSize
;
799 UINT32 EfiSignature
; ///< 0x0EF1
801 UINT16 EfiMachineType
;
802 UINT16 CompressionType
;
804 UINT16 EfiImageHeaderOffset
;
806 } EFI_PCI_EXPANSION_ROM_HEADER
;
810 PCI_EXPANSION_ROM_HEADER
*Generic
;
811 EFI_PCI_EXPANSION_ROM_HEADER
*Efi
;
812 EFI_LEGACY_EXPANSION_ROM_HEADER
*PcAt
;
813 } EFI_PCI_ROM_HEADER
;