2 Support for PCI 2.2 standard.
4 This file includes the definitions in the following specifications,
5 PCI Local Bus Specification, 2.2
6 PCI-to-PCI Bridge Architecture Specification, Revision 1.2
8 PCI Power Management Interface Specification, Revision 1.2
10 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
11 Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
12 SPDX-License-Identifier: BSD-2-Clause-Patent
19 #define PCI_MAX_BUS 255
20 #define PCI_MAX_DEVICE 31
21 #define PCI_MAX_FUNC 7
26 /// Common header region in PCI Configuration Space
27 /// Section 6.1, PCI Local Bus Specification, 2.2
40 } PCI_DEVICE_INDEPENDENT_REGION
;
43 /// PCI Device header region in PCI Configuration Space
44 /// Section 6.1, PCI Local Bus Specification, 2.2
49 UINT16 SubsystemVendorID
;
51 UINT32 ExpansionRomBar
;
59 } PCI_DEVICE_HEADER_TYPE_REGION
;
62 /// PCI Device Configuration Space
63 /// Section 6.1, PCI Local Bus Specification, 2.2
66 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
67 PCI_DEVICE_HEADER_TYPE_REGION Device
;
71 /// PCI-PCI Bridge header region in PCI Configuration Space
72 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
79 UINT8 SecondaryLatencyTimer
;
82 UINT16 SecondaryStatus
;
85 UINT16 PrefetchableMemoryBase
;
86 UINT16 PrefetchableMemoryLimit
;
87 UINT32 PrefetchableBaseUpper32
;
88 UINT32 PrefetchableLimitUpper32
;
90 UINT16 IoLimitUpper16
;
93 UINT32 ExpansionRomBAR
;
97 } PCI_BRIDGE_CONTROL_REGISTER
;
100 /// PCI-to-PCI Bridge Configuration Space
101 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
104 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
105 PCI_BRIDGE_CONTROL_REGISTER Bridge
;
114 /// CardBus Controller Configuration Space,
115 /// Section 4.5.1, PC Card Standard. 8.0
118 UINT32 CardBusSocketReg
; ///< Cardbus Socket/ExCA Base
121 UINT16 SecondaryStatus
; ///< Secondary Status
122 UINT8 PciBusNumber
; ///< PCI Bus Number
123 UINT8 CardBusBusNumber
; ///< CardBus Bus Number
124 UINT8 SubordinateBusNumber
; ///< Subordinate Bus Number
125 UINT8 CardBusLatencyTimer
; ///< CardBus Latency Timer
126 UINT32 MemoryBase0
; ///< Memory Base Register 0
127 UINT32 MemoryLimit0
; ///< Memory Limit Register 0
131 UINT32 IoLimit0
; ///< I/O Base Register 0
132 UINT32 IoBase1
; ///< I/O Limit Register 0
134 UINT8 InterruptLine
; ///< Interrupt Line
135 UINT8 InterruptPin
; ///< Interrupt Pin
136 UINT16 BridgeControl
; ///< Bridge Control
137 } PCI_CARDBUS_CONTROL_REGISTER
;
140 // Definitions of PCI class bytes and manipulation macros.
142 #define PCI_CLASS_OLD 0x00
143 #define PCI_CLASS_OLD_OTHER 0x00
144 #define PCI_CLASS_OLD_VGA 0x01
146 #define PCI_CLASS_MASS_STORAGE 0x01
147 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
148 #define PCI_CLASS_MASS_STORAGE_IDE 0x01
149 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
150 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
151 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
152 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
154 #define PCI_CLASS_NETWORK 0x02
155 #define PCI_CLASS_NETWORK_ETHERNET 0x00
156 #define PCI_CLASS_NETWORK_TOKENRING 0x01
157 #define PCI_CLASS_NETWORK_FDDI 0x02
158 #define PCI_CLASS_NETWORK_ATM 0x03
159 #define PCI_CLASS_NETWORK_ISDN 0x04
160 #define PCI_CLASS_NETWORK_OTHER 0x80
162 #define PCI_CLASS_DISPLAY 0x03
163 #define PCI_CLASS_DISPLAY_VGA 0x00
164 #define PCI_IF_VGA_VGA 0x00
165 #define PCI_IF_VGA_8514 0x01
166 #define PCI_CLASS_DISPLAY_XGA 0x01
167 #define PCI_CLASS_DISPLAY_3D 0x02
168 #define PCI_CLASS_DISPLAY_OTHER 0x80
170 #define PCI_CLASS_MEDIA 0x04
171 #define PCI_CLASS_MEDIA_VIDEO 0x00
172 #define PCI_CLASS_MEDIA_AUDIO 0x01
173 #define PCI_CLASS_MEDIA_TELEPHONE 0x02
174 #define PCI_CLASS_MEDIA_OTHER 0x80
176 #define PCI_CLASS_MEMORY_CONTROLLER 0x05
177 #define PCI_CLASS_MEMORY_RAM 0x00
178 #define PCI_CLASS_MEMORY_FLASH 0x01
179 #define PCI_CLASS_MEMORY_OTHER 0x80
181 #define PCI_CLASS_BRIDGE 0x06
182 #define PCI_CLASS_BRIDGE_HOST 0x00
183 #define PCI_CLASS_BRIDGE_ISA 0x01
184 #define PCI_CLASS_BRIDGE_EISA 0x02
185 #define PCI_CLASS_BRIDGE_MCA 0x03
186 #define PCI_CLASS_BRIDGE_P2P 0x04
187 #define PCI_IF_BRIDGE_P2P 0x00
188 #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
189 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
190 #define PCI_CLASS_BRIDGE_NUBUS 0x06
191 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
192 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
193 #define PCI_CLASS_BRIDGE_OTHER 0x80
194 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
196 #define PCI_CLASS_SCC 0x07///< Simple communications controllers
197 #define PCI_SUBCLASS_SERIAL 0x00
198 #define PCI_IF_GENERIC_XT 0x00
199 #define PCI_IF_16450 0x01
200 #define PCI_IF_16550 0x02
201 #define PCI_IF_16650 0x03
202 #define PCI_IF_16750 0x04
203 #define PCI_IF_16850 0x05
204 #define PCI_IF_16950 0x06
205 #define PCI_SUBCLASS_PARALLEL 0x01
206 #define PCI_IF_PARALLEL_PORT 0x00
207 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
208 #define PCI_IF_ECP_PARALLEL_PORT 0x02
209 #define PCI_IF_1284_CONTROLLER 0x03
210 #define PCI_IF_1284_DEVICE 0xFE
211 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
212 #define PCI_SUBCLASS_MODEM 0x03
213 #define PCI_IF_GENERIC_MODEM 0x00
214 #define PCI_IF_16450_MODEM 0x01
215 #define PCI_IF_16550_MODEM 0x02
216 #define PCI_IF_16650_MODEM 0x03
217 #define PCI_IF_16750_MODEM 0x04
218 #define PCI_SUBCLASS_SCC_OTHER 0x80
220 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
221 #define PCI_SUBCLASS_PIC 0x00
222 #define PCI_IF_8259_PIC 0x00
223 #define PCI_IF_ISA_PIC 0x01
224 #define PCI_IF_EISA_PIC 0x02
225 #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.
226 #define PCI_IF_APIC_CONTROLLER2 0x20
227 #define PCI_SUBCLASS_DMA 0x01
228 #define PCI_IF_8237_DMA 0x00
229 #define PCI_IF_ISA_DMA 0x01
230 #define PCI_IF_EISA_DMA 0x02
231 #define PCI_SUBCLASS_TIMER 0x02
232 #define PCI_IF_8254_TIMER 0x00
233 #define PCI_IF_ISA_TIMER 0x01
234 #define PCI_IF_EISA_TIMER 0x02
235 #define PCI_SUBCLASS_RTC 0x03
236 #define PCI_IF_GENERIC_RTC 0x00
237 #define PCI_IF_ISA_RTC 0x01
238 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
239 #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
241 #define PCI_CLASS_INPUT_DEVICE 0x09
242 #define PCI_SUBCLASS_KEYBOARD 0x00
243 #define PCI_SUBCLASS_PEN 0x01
244 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
245 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
246 #define PCI_SUBCLASS_GAMEPORT 0x04
247 #define PCI_IF_GAMEPORT 0x00
248 #define PCI_IF_GAMEPORT1 0x10
249 #define PCI_SUBCLASS_INPUT_OTHER 0x80
251 #define PCI_CLASS_DOCKING_STATION 0x0A
252 #define PCI_SUBCLASS_DOCKING_GENERIC 0x00
253 #define PCI_SUBCLASS_DOCKING_OTHER 0x80
255 #define PCI_CLASS_PROCESSOR 0x0B
256 #define PCI_SUBCLASS_PROC_386 0x00
257 #define PCI_SUBCLASS_PROC_486 0x01
258 #define PCI_SUBCLASS_PROC_PENTIUM 0x02
259 #define PCI_SUBCLASS_PROC_ALPHA 0x10
260 #define PCI_SUBCLASS_PROC_POWERPC 0x20
261 #define PCI_SUBCLASS_PROC_MIPS 0x30
262 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
264 #define PCI_CLASS_SERIAL 0x0C
265 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
266 #define PCI_IF_1394 0x00
267 #define PCI_IF_1394_OPEN_HCI 0x10
268 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
269 #define PCI_CLASS_SERIAL_SSA 0x02
270 #define PCI_CLASS_SERIAL_USB 0x03
271 #define PCI_IF_UHCI 0x00
272 #define PCI_IF_OHCI 0x10
273 #define PCI_IF_USB_OTHER 0x80
274 #define PCI_IF_USB_DEVICE 0xFE
275 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
276 #define PCI_CLASS_SERIAL_SMB 0x05
278 #define PCI_CLASS_WIRELESS 0x0D
279 #define PCI_SUBCLASS_IRDA 0x00
280 #define PCI_SUBCLASS_IR 0x01
281 #define PCI_SUBCLASS_RF 0x10
282 #define PCI_SUBCLASS_WIRELESS_OTHER 0x80
284 #define PCI_CLASS_INTELLIGENT_IO 0x0E
286 #define PCI_CLASS_SATELLITE 0x0F
287 #define PCI_SUBCLASS_TV 0x01
288 #define PCI_SUBCLASS_AUDIO 0x02
289 #define PCI_SUBCLASS_VOICE 0x03
290 #define PCI_SUBCLASS_DATA 0x04
292 #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
293 #define PCI_SUBCLASS_NET_COMPUT 0x00
294 #define PCI_SUBCLASS_ENTERTAINMENT 0x10
295 #define PCI_SUBCLASS_SECURITY_OTHER 0x80
297 #define PCI_CLASS_DPIO 0x11
298 #define PCI_SUBCLASS_DPIO 0x00
299 #define PCI_SUBCLASS_DPIO_OTHER 0x80
302 Macro that checks whether the Base Class code of device matched.
304 @param _p Specified device.
305 @param c Base Class code needs matching.
307 @retval TRUE Base Class code matches the specified device.
308 @retval FALSE Base Class code doesn't match the specified device.
311 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
314 Macro that checks whether the Base Class code and Sub-Class code of device matched.
316 @param _p Specified device.
317 @param c Base Class code needs matching.
318 @param s Sub-Class code needs matching.
320 @retval TRUE Base Class code and Sub-Class code match the specified device.
321 @retval FALSE Base Class code and Sub-Class code don't match the specified device.
324 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
327 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
329 @param _p Specified device.
330 @param c Base Class code needs matching.
331 @param s Sub-Class code needs matching.
332 @param p Interface code needs matching.
334 @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
335 @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
338 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
341 Macro that checks whether device is a display controller.
343 @param _p Specified device.
345 @retval TRUE Device is a display controller.
346 @retval FALSE Device is not a display controller.
349 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
352 Macro that checks whether device is a VGA-compatible controller.
354 @param _p Specified device.
356 @retval TRUE Device is a VGA-compatible controller.
357 @retval FALSE Device is not a VGA-compatible controller.
360 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
363 Macro that checks whether device is an 8514-compatible controller.
365 @param _p Specified device.
367 @retval TRUE Device is an 8514-compatible controller.
368 @retval FALSE Device is not an 8514-compatible controller.
371 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
374 Macro that checks whether device is built before the Class Code field was defined.
376 @param _p Specified device.
378 @retval TRUE Device is an old device.
379 @retval FALSE Device is not an old device.
382 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
385 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
387 @param _p Specified device.
389 @retval TRUE Device is an old VGA-compatible device.
390 @retval FALSE Device is not an old VGA-compatible device.
393 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
396 Macro that checks whether device is an IDE controller.
398 @param _p Specified device.
400 @retval TRUE Device is an IDE controller.
401 @retval FALSE Device is not an IDE controller.
404 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
407 Macro that checks whether device is a SCSI bus controller.
409 @param _p Specified device.
411 @retval TRUE Device is a SCSI bus controller.
412 @retval FALSE Device is not a SCSI bus controller.
415 #define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
418 Macro that checks whether device is a RAID controller.
420 @param _p Specified device.
422 @retval TRUE Device is a RAID controller.
423 @retval FALSE Device is not a RAID controller.
426 #define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
429 Macro that checks whether device is an ISA bridge.
431 @param _p Specified device.
433 @retval TRUE Device is an ISA bridge.
434 @retval FALSE Device is not an ISA bridge.
437 #define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
440 Macro that checks whether device is a PCI-to-PCI bridge.
442 @param _p Specified device.
444 @retval TRUE Device is a PCI-to-PCI bridge.
445 @retval FALSE Device is not a PCI-to-PCI bridge.
448 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
451 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
453 @param _p Specified device.
455 @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
456 @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
459 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
462 Macro that checks whether device is a 16550-compatible serial controller.
464 @param _p Specified device.
466 @retval TRUE Device is a 16550-compatible serial controller.
467 @retval FALSE Device is not a 16550-compatible serial controller.
470 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
473 Macro that checks whether device is a Universal Serial Bus controller.
475 @param _p Specified device.
477 @retval TRUE Device is a Universal Serial Bus controller.
478 @retval FALSE Device is not a Universal Serial Bus controller.
481 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
484 // the definition of Header Type
486 #define HEADER_TYPE_DEVICE 0x00
487 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
488 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
489 #define HEADER_TYPE_MULTI_FUNCTION 0x80
491 // Mask of Header type
493 #define HEADER_LAYOUT_CODE 0x7f
496 Macro that checks whether device is a PCI-PCI bridge.
498 @param _p Specified device.
500 @retval TRUE Device is a PCI-PCI bridge.
501 @retval FALSE Device is not a PCI-PCI bridge.
504 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
507 Macro that checks whether device is a CardBus bridge.
509 @param _p Specified device.
511 @retval TRUE Device is a CardBus bridge.
512 @retval FALSE Device is not a CardBus bridge.
515 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
518 Macro that checks whether device is a multiple functions device.
520 @param _p Specified device.
522 @retval TRUE Device is a multiple functions device.
523 @retval FALSE Device is not a multiple functions device.
526 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
529 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,
531 #define PCI_BRIDGE_ROMBAR 0x38
533 #define PCI_MAX_BAR 0x0006
534 #define PCI_MAX_CONFIG_OFFSET 0x0100
536 #define PCI_VENDOR_ID_OFFSET 0x00
537 #define PCI_DEVICE_ID_OFFSET 0x02
538 #define PCI_COMMAND_OFFSET 0x04
539 #define PCI_PRIMARY_STATUS_OFFSET 0x06
540 #define PCI_REVISION_ID_OFFSET 0x08
541 #define PCI_CLASSCODE_OFFSET 0x09
542 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
543 #define PCI_LATENCY_TIMER_OFFSET 0x0D
544 #define PCI_HEADER_TYPE_OFFSET 0x0E
545 #define PCI_BIST_OFFSET 0x0F
546 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
547 #define PCI_CARDBUS_CIS_OFFSET 0x28
548 #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
549 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
550 #define PCI_SID_OFFSET 0x2E ///< SubSystem ID
551 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
552 #define PCI_EXPANSION_ROM_BASE 0x30
553 #define PCI_CAPBILITY_POINTER_OFFSET 0x34
554 #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
555 #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
556 #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
557 #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
560 // defined in PCI-to-PCI Bridge Architecture Specification
562 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
563 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
564 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
565 #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
566 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
567 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
570 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
572 #define PCI_INT_LINE_UNKNOWN 0xFF
575 /// PCI Access Data Format
587 } PCI_CONFIG_ACCESS_CF8
;
591 #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
592 #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
593 #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
594 #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
595 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
596 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
597 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
598 #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
599 #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
600 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
603 // defined in PCI-to-PCI Bridge Architecture Specification
605 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
606 #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
607 #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
608 #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008
609 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010
610 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020
611 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040
612 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
613 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100
614 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
615 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
616 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
619 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
621 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
622 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
623 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
624 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
627 // Following are the PCI status control bit
629 #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
630 #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
631 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
632 #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
635 /// defined in PC Card Standard
637 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
641 // PCI Capability List IDs and records
643 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
644 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
645 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
646 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
647 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
648 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
649 #define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
652 /// Capabilities List Header
653 /// Section 6.7, PCI Local Bus Specification, 2.2
658 } EFI_PCI_CAPABILITY_HDR
;
661 /// PMC - Power Management Capabilities
662 /// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2
669 UINT16 DeviceSpecificInitialization
: 1;
670 UINT16 AuxCurrent
: 3;
671 UINT16 D1Support
: 1;
672 UINT16 D2Support
: 1;
673 UINT16 PmeSupport
: 5;
678 #define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
681 /// PMCSR - Power Management Control/Status
682 /// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2
686 UINT16 PowerState
: 2;
687 UINT16 ReservedForPciExpress
: 1;
688 UINT16 NoSoftReset
: 1;
690 UINT16 PmeEnable
: 1;
691 UINT16 DataSelect
: 4;
692 UINT16 DataScale
: 2;
693 UINT16 PmeStatus
: 1;
698 #define PCI_POWER_STATE_D0 0
699 #define PCI_POWER_STATE_D1 1
700 #define PCI_POWER_STATE_D2 2
701 #define PCI_POWER_STATE_D3_HOT 3
704 /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
705 /// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2
711 UINT8 BusPowerClockControl
: 1;
717 /// Power Management Register Block Definition
718 /// Section 3.2, PCI Power Management Interface Specification, Revision 1.2
721 EFI_PCI_CAPABILITY_HDR Hdr
;
724 EFI_PCI_PMCSR_BSE BridgeExtention
;
726 } EFI_PCI_CAPABILITY_PMI
;
730 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
733 EFI_PCI_CAPABILITY_HDR Hdr
;
738 } EFI_PCI_CAPABILITY_AGP
;
741 /// VPD Capability Structure
742 /// Appendix I, PCI Local Bus Specification, 2.2
745 EFI_PCI_CAPABILITY_HDR Hdr
;
748 } EFI_PCI_CAPABILITY_VPD
;
751 /// Slot Numbering Capabilities Register
752 /// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2
755 EFI_PCI_CAPABILITY_HDR Hdr
;
758 } EFI_PCI_CAPABILITY_SLOTID
;
761 /// Message Capability Structure for 32-bit Message Address
762 /// Section 6.8.1, PCI Local Bus Specification, 2.2
765 EFI_PCI_CAPABILITY_HDR Hdr
;
769 } EFI_PCI_CAPABILITY_MSI32
;
772 /// Message Capability Structure for 64-bit Message Address
773 /// Section 6.8.1, PCI Local Bus Specification, 2.2
776 EFI_PCI_CAPABILITY_HDR Hdr
;
778 UINT32 MsgAddrRegLsdw
;
779 UINT32 MsgAddrRegMsdw
;
781 } EFI_PCI_CAPABILITY_MSI64
;
784 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
785 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
788 EFI_PCI_CAPABILITY_HDR Hdr
;
790 /// not finished - fields need to go here
792 } EFI_PCI_CAPABILITY_HOTPLUG
;
794 #define PCI_BAR_IDX0 0x00
795 #define PCI_BAR_IDX1 0x01
796 #define PCI_BAR_IDX2 0x02
797 #define PCI_BAR_IDX3 0x03
798 #define PCI_BAR_IDX4 0x04
799 #define PCI_BAR_IDX5 0x05
802 /// EFI PCI Option ROM definitions
804 #define EFI_ROOT_BRIDGE_LIST 'eprb'
805 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
807 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
808 #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
809 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
810 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
813 /// Standard PCI Expansion ROM Header
814 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
817 UINT16 Signature
; ///< 0xaa55
818 UINT8 Reserved
[0x16];
820 } PCI_EXPANSION_ROM_HEADER
;
823 /// Legacy ROM Header Extensions
824 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
827 UINT16 Signature
; ///< 0xaa55
829 UINT8 InitEntryPoint
[3];
830 UINT8 Reserved
[0x12];
832 } EFI_LEGACY_EXPANSION_ROM_HEADER
;
835 /// PCI Data Structure Format
836 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
839 UINT32 Signature
; ///< "PCIR"
851 } PCI_DATA_STRUCTURE
;
854 /// EFI PCI Expansion ROM Header
855 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
858 UINT16 Signature
; ///< 0xaa55
859 UINT16 InitializationSize
;
860 UINT32 EfiSignature
; ///< 0x0EF1
862 UINT16 EfiMachineType
;
863 UINT16 CompressionType
;
865 UINT16 EfiImageHeaderOffset
;
867 } EFI_PCI_EXPANSION_ROM_HEADER
;
871 PCI_EXPANSION_ROM_HEADER
*Generic
;
872 EFI_PCI_EXPANSION_ROM_HEADER
*Efi
;
873 EFI_LEGACY_EXPANSION_ROM_HEADER
*PcAt
;
874 } EFI_PCI_ROM_HEADER
;