2 Main SAL API's defined in SAL 3.0 specification.
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 // Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003
22 #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
23 #define EFI_SAL_FIT_PAL_B_TYPE 0x01
25 // type from 0x02 to 0x0E is reserved.
27 #define EFI_SAL_FIT_PAL_A_TYPE 0x0F
29 // OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10
31 #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
32 #define EFI_SAL_FIT_UNUSED_TYPE 0x7F
37 typedef UINTN EFI_SAL_STATUS
;
39 #define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
40 #define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
41 #define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
42 #define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
43 #define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
44 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
45 #define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
46 #define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
49 // Return values from SAL
52 EFI_SAL_STATUS Status
; // register r8
59 // Delivery Mode of IPF CPU.
62 EFI_DELIVERY_MODE_INT
,
63 EFI_DELIVERY_MODE_MPreserved1
,
64 EFI_DELIVERY_MODE_PMI
,
65 EFI_DELIVERY_MODE_MPreserved2
,
66 EFI_DELIVERY_MODE_NMI
,
67 EFI_DELIVERY_MODE_INIT
,
68 EFI_DELIVERY_MODE_MPreserved3
,
69 EFI_DELIVERY_MODE_ExtINT
72 typedef SAL_RETURN_REGS (EFIAPI
*SAL_PROC
)
85 // SAL Procedure FunctionId definition
87 #define EFI_SAL_SET_VECTORS 0x01000000
88 #define EFI_SAL_GET_STATE_INFO 0x01000001
89 #define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
90 #define EFI_SAL_CLEAR_STATE_INFO 0x01000003
91 #define EFI_SAL_MC_RENDEZ 0x01000004
92 #define EFI_SAL_MC_SET_PARAMS 0x01000005
93 #define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
94 #define EFI_SAL_CACHE_FLUSH 0x01000008
95 #define EFI_SAL_CACHE_INIT 0x01000009
96 #define EFI_SAL_PCI_CONFIG_READ 0x01000010
97 #define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
98 #define EFI_SAL_FREQ_BASE 0x01000012
99 #define EFI_SAL_UPDATE_PAL 0x01000020
101 #define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
102 #define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
105 // SAL Procedure parameter definitions
106 // Not much point in using typedefs or enums because all params
107 // are UINT64 and the entry point is common
109 // EFI_SAL_SET_VECTORS
111 #define EFI_SAL_SET_MCA_VECTOR 0x0
112 #define EFI_SAL_SET_INIT_VECTOR 0x1
113 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
117 UINT64 ChecksumValid
: 1;
118 UINT64 Reserved1
: 7;
119 UINT64 ByteChecksum
: 8;
120 UINT64 Reserved2
: 16;
121 } SAL_SET_VECTORS_CS_N
;
124 // EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
125 // EFI_SAL_CLEAR_STATE_INFO
127 #define EFI_SAL_MCA_STATE_INFO 0x0
128 #define EFI_SAL_INIT_STATE_INFO 0x1
129 #define EFI_SAL_CMC_STATE_INFO 0x2
130 #define EFI_SAL_CP_STATE_INFO 0x3
133 // EFI_SAL_MC_SET_PARAMS
135 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
136 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
137 #define EFI_SAL_MC_SET_CPE_PARAM 0x3
139 #define EFI_SAL_MC_SET_INTR_PARAM 0x1
140 #define EFI_SAL_MC_SET_MEM_PARAM 0x2
143 // EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
145 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
148 // EFI_SAL_CACHE_FLUSH
150 #define EFI_SAL_FLUSH_I_CACHE 0x01
151 #define EFI_SAL_FLUSH_D_CACHE 0x02
152 #define EFI_SAL_FLUSH_BOTH_CACHE 0x03
153 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
156 // EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
158 #define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
159 #define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
160 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
168 UINT64 Reserved
: 32;
174 #define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
175 #define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
176 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
179 // EFI_SAL_UPDATE_PAL
181 #define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
182 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
183 #define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
184 #define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
185 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
186 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
187 #define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
188 #define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
197 } SAL_UPDATE_PAL_DATA_BLOCK
;
199 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK
{
200 struct _SAL_UPDATE_PAL_INFO_BLOCK
*Next
;
201 struct SAL_UPDATE_PAL_DATA_BLOCK
*DataBlock
;
204 } SAL_UPDATE_PAL_INFO_BLOCK
;
207 // SAL System Table Definitions
222 } SAL_SYSTEM_TABLE_HEADER
;
225 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
226 #define EFI_SAL_REVISION 0x0300
230 #define EFI_SAL_ST_ENTRY_POINT 0
231 #define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
232 #define EFI_SAL_ST_PLATFORM_FEATURES 2
233 #define EFI_SAL_ST_TR_USAGE 3
234 #define EFI_SAL_ST_PTC 4
235 #define EFI_SAL_ST_AP_WAKEUP 5
239 UINT8 Type
; // Type == 0
243 UINT64 SalGlobalDataPointer
;
245 } SAL_ST_ENTRY_POINT_DESCRIPTOR
;
248 // Not needed for Itanium-based OS boot
251 UINT8 Type
; // Type == 1
252 UINT8 NeedVirtualRegistration
;
253 UINT8 MemoryAttributes
;
254 UINT8 PageAccessRights
;
255 UINT8 SupportedAttributes
;
259 UINT64 PhysicalMemoryAddress
;
263 } SAL_ST_MEMORY_DESCRIPTOR_ENTRY
;
269 #define SAL_MDT_ATTRIB_WB 0x00
271 // #define SAL_MDT_ATTRIB_UC 0x02
273 #define SAL_MDT_ATTRIB_UC 0x04
274 #define SAL_MDT_ATTRIB_UCE 0x05
275 #define SAL_MDT_ATTRIB_WC 0x06
278 // Supported memory Attributes
280 #define SAL_MDT_SUPPORT_WB 0x1
281 #define SAL_MDT_SUPPORT_UC 0x2
282 #define SAL_MDT_SUPPORT_UCE 0x4
283 #define SAL_MDT_SUPPORT_WC 0x8
286 // Virtual address registration
288 #define SAL_MDT_NO_VA 0x00
289 #define SAL_MDT_NEED_VA 0x01
293 #define SAL_REGULAR_MEMORY 0x0000
294 #define SAL_MMIO_MAPPING 0x0001
295 #define SAL_SAPIC_IPI_BLOCK 0x0002
296 #define SAL_IO_PORT_MAPPING 0x0003
297 #define SAL_FIRMWARE_MEMORY 0x0004
298 #define SAL_BLACK_HOLE 0x000A
302 #define SAL_MDT_USAGE_UNSPECIFIED 0x00
303 #define SAL_PAL_CODE 0x01
304 #define SAL_BOOTSERVICE_CODE 0x02
305 #define SAL_BOOTSERVICE_DATA 0x03
306 #define SAL_RUNTIMESERVICE_CODE 0x04
307 #define SAL_RUNTIMESERVICE_DATA 0x05
308 #define SAL_IA32_OPTIONROM 0x06
309 #define SAL_IA32_SYSTEMROM 0x07
310 #define SAL_PMI_CODE 0x0a
311 #define SAL_PMI_DATA 0x0b
315 UINT8 Type
; // Type == 2
316 UINT8 PlatformFeatures
;
318 } SAL_ST_PLATFORM_FEATURES
;
321 #define SAL_PLAT_FEAT_BUS_LOCK 0x01
322 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
323 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
327 UINT8 Type
; // Type == 3
331 UINT64 VirtualAddress
;
332 UINT64 EncodedPageSize
;
334 } SAL_ST_TR_DECRIPTOR
;
337 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
338 #define EFI_SAL_ST_TR_USAGE_DATA 01
342 UINT64 NumberOfProcessors
;
343 UINT64 LocalIDRegister
;
344 } SAL_COHERENCE_DOMAIN_INFO
;
349 UINT8 Type
; // Type == 4
351 UINT32 NumberOfDomains
;
352 SAL_COHERENCE_DOMAIN_INFO
*DomainInformation
;
353 } SAL_ST_CACHE_COHERENCE_DECRIPTOR
;
358 UINT8 Type
; // Type == 5
361 UINT64 ExternalInterruptVector
;
362 } SAL_ST_AP_WAKEUP_DECRIPTOR
;
367 #define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
368 #define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
369 #define EFI_SAL_FIT_PALB_TYPE 01
377 UINT8 CheckSumValid
: 1;
382 // SAL Common Record Header
404 UINT8 ValidationBits
;
406 SAL_TIME_STAMP TimeStamp
;
407 UINT8 OemPlatformId
[16];
413 UINT8 ErrorRecoveryInfo
;
415 UINT32 SectionLength
;
419 // SAL Processor Record
421 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
423 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
426 #define CHECK_INFO_VALID_BIT_MASK 0x1
427 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
428 #define RESPONDER_ID_VALID_BIT_MASK 0x4
429 #define TARGER_ID_VALID_BIT_MASK 0x8
430 #define PRECISE_IP_VALID_BIT_MASK 0x10
433 UINT64 InfoValid
: 1;
435 UINT64 RespValid
: 1;
436 UINT64 TargetValid
: 1;
438 UINT64 Reserved
: 59;
456 #define MIN_STATE_VALID_BIT_MASK 0x1
457 #define BR_VALID_BIT_MASK 0x2
458 #define CR_VALID_BIT_MASK 0x4
459 #define AR_VALID_BIT_MASK 0x8
460 #define RR_VALID_BIT_MASK 0x10
461 #define FR_VALID_BIT_MASK 0x20
464 UINT64 ValidFieldBits
;
465 UINT8 MinStateInfo
[1024];
473 #define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
474 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
475 #define PROC_CR_LID_VALID_BIT_MASK 0x4
476 #define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
477 #define CPU_INFO_VALID_BIT_MASK 0x1000000
480 SAL_SEC_HEADER SectionHeader
;
481 UINT64 ValidationBits
;
483 UINT64 ProcStateParameter
;
485 MOD_ERROR_INFO CacheError
[15];
486 MOD_ERROR_INFO TlbError
[15];
487 MOD_ERROR_INFO BusError
[15];
488 MOD_ERROR_INFO RegFileCheck
[15];
489 MOD_ERROR_INFO MsCheck
[15];
491 PSI_STATIC_STRUCT PsiValidData
;
492 } SAL_PROCESSOR_ERROR_RECORD
;
495 // Sal Platform memory Error Record
497 #define SAL_MEMORY_ERROR_RECORD_INFO \
499 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
502 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
503 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
504 #define MEMORY_ADDR_BIT_MASK 0x4
505 #define MEMORY_NODE_VALID_BIT_MASK 0x8
506 #define MEMORY_CARD_VALID_BIT_MASK 0x10
507 #define MEMORY_MODULE_VALID_BIT_MASK 0x20
508 #define MEMORY_BANK_VALID_BIT_MASK 0x40
509 #define MEMORY_DEVICE_VALID_BIT_MASK 0x80
510 #define MEMORY_ROW_VALID_BIT_MASK 0x100
511 #define MEMORY_COLUMN_VALID_BIT_MASK 0x200
512 #define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
513 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
514 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
515 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
516 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
517 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
518 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
521 SAL_SEC_HEADER SectionHeader
;
522 UINT64 ValidationBits
;
523 UINT64 MemErrorStatus
;
524 UINT64 MemPhysicalAddress
;
525 UINT64 MemPhysicalAddressMask
;
533 UINT16 MemBitPosition
;
534 UINT64 ModRequestorId
;
535 UINT64 ModResponderId
;
537 UINT64 BusSpecificData
;
538 UINT8 MemPlatformOemId
[16];
539 } SAL_MEMORY_ERROR_RECORD
;
544 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
546 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
549 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
550 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
551 #define PCI_BUS_ID_VALID_BIT_MASK 0x4
552 #define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
553 #define PCI_BUS_DATA_VALID_BIT_MASK 0x10
554 #define PCI_BUS_CMD_VALID_BIT_MASK 0x20
555 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
556 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
557 #define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
558 #define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
559 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
567 SAL_SEC_HEADER SectionHeader
;
568 UINT64 ValidationBits
;
569 UINT64 PciBusErrorStatus
;
570 UINT16 PciBusErrorType
;
573 UINT64 PciBusAddress
;
575 UINT64 PciBusCommand
;
576 UINT64 PciBusRequestorId
;
577 UINT64 PciBusResponderId
;
578 UINT64 PciBusTargetId
;
579 UINT8 PciBusOemId
[16];
580 } SAL_PCI_BUS_ERROR_RECORD
;
583 // PCI Component Errors
585 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
587 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
590 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
591 #define PCI_COMP_INFO_VALID_BIT_MASK 0x2
592 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
593 #define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
594 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
595 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
601 UINT8 FunctionNumber
;
609 SAL_SEC_HEADER SectionHeader
;
610 UINT64 ValidationBits
;
611 UINT64 PciComponentErrorStatus
;
612 PCI_COMP_INFO PciComponentInfo
;
613 UINT32 PciComponentMemNum
;
614 UINT32 PciComponentIoNum
;
615 UINT8 PciBusOemId
[16];
616 } SAL_PCI_COMPONENT_ERROR_RECORD
;
619 // Sal Device Errors Info.
621 #define SAL_DEVICE_ERROR_RECORD_INFO \
623 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
626 #define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
627 #define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
628 #define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
629 #define SEL_EVM_REV_VALID_BIT_MASK 0x8;
630 #define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
631 #define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
632 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
633 #define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
634 #define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
635 #define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
638 SAL_SEC_HEADER SectionHeader
;
639 UINT64 ValidationBits
;
651 } SAL_DEVICE_ERROR_RECORD
;
654 // Sal SMBIOS Device Errors Info.
656 #define SAL_SMBIOS_ERROR_RECORD_INFO \
658 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
661 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
662 #define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
663 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
664 #define SMBIOS_DATA_VALID_BIT_MASK 0x8
667 SAL_SEC_HEADER SectionHeader
;
668 UINT64 ValidationBits
;
669 UINT8 SmbiosEventType
;
671 UINT8 SmbiosBcdTimeStamp
[6];
672 } SAL_SMBIOS_DEVICE_ERROR_RECORD
;
675 // Sal Platform Specific Errors Info.
677 #define SAL_PLATFORM_ERROR_RECORD_INFO \
679 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
682 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
683 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
684 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
685 #define PLATFORM_TARGET_VALID_BIT_MASK 0x8
686 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
687 #define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
688 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
689 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
692 SAL_SEC_HEADER SectionHeader
;
693 UINT64 ValidationBits
;
694 UINT64 PlatformErrorStatus
;
695 UINT64 PlatformRequestorId
;
696 UINT64 PlatformResponderId
;
697 UINT64 PlatformTargetId
;
698 UINT64 PlatformBusSpecificData
;
699 UINT8 OemComponentId
[16];
700 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD
;
703 // Union of all the possible Sal Record Types
706 SAL_RECORD_HEADER
*RecordHeader
;
707 SAL_PROCESSOR_ERROR_RECORD
*SalProcessorRecord
;
708 SAL_PCI_BUS_ERROR_RECORD
*SalPciBusRecord
;
709 SAL_PCI_COMPONENT_ERROR_RECORD
*SalPciComponentRecord
;
710 SAL_DEVICE_ERROR_RECORD
*ImpiRecord
;
711 SAL_SMBIOS_DEVICE_ERROR_RECORD
*SmbiosRecord
;
712 SAL_PLATFORM_SPECIFIC_ERROR_RECORD
*PlatformRecord
;
713 SAL_MEMORY_ERROR_RECORD
*MemoryRecord
;
715 } SAL_ERROR_RECORDS_POINTERS
;