2 Main SAL API's defined in Intel Itanium Processor Family System Abstraction
3 Layer Specification Revision 3.2 (December 2003)
5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
14 /// SAL return status type
16 typedef INTN EFI_SAL_STATUS
;
19 /// Call completed without error.
21 #define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
23 /// Call completed without error, but some information was lost due to overflow.
25 #define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)
27 /// Call completed without error; effect a warm boot of the system to complete the update.
29 #define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2)
31 /// More information is available for retrieval.
33 #define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
37 #define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
41 #define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
43 /// Call completed without error.
45 #define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
47 /// Virtual address not registered.
49 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
51 /// No information available.
53 #define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
55 /// Scratch buffer required.
57 #define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
60 /// Return registers from SAL.
64 /// SAL return status value in r8.
66 EFI_SAL_STATUS Status
;
68 /// SAL returned value in r9.
72 /// SAL returned value in r10.
76 /// SAL returned value in r11.
82 Prototype of SAL procedures.
84 @param FunctionId Functional identifier.
85 The upper 32 bits are ignored and only the lower 32 bits
86 are used. The following functional identifiers are defined:
87 0x01XXXXXX - Architected SAL functional group.
88 0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is
89 allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.
90 0x04XXXXXX to 0xFFFFFFFF - Reserved.
91 @param Arg1 The first parameter of the architected/OEM specific SAL functions.
92 @param Arg2 The second parameter of the architected/OEM specific SAL functions.
93 @param Arg3 The third parameter passed to the ESAL function based.
94 @param Arg4 The fourth parameter passed to the ESAL function based.
95 @param Arg5 The fifth parameter passed to the ESAL function based.
96 @param Arg6 The sixth parameter passed to the ESAL function.
97 @param Arg7 The seventh parameter passed to the ESAL function based.
99 @return r8 Return status: positive number indicates successful,
100 negative number indicates failure.
101 r9 Other return parameter in r9.
102 r10 Other return parameter in r10.
103 r11 Other return parameter in r11.
109 IN UINT64 FunctionId
,
120 // SAL Procedure FunctionId definition
124 /// Register software code locations with SAL.
126 #define EFI_SAL_SET_VECTORS 0x01000000
128 /// Return Machine State information obtained by SAL.
130 #define EFI_SAL_GET_STATE_INFO 0x01000001
132 /// Obtain size of Machine State information.
134 #define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
136 /// Clear Machine State information.
138 #define EFI_SAL_CLEAR_STATE_INFO 0x01000003
140 /// Cause the processor to go into a spin loop within SAL.
142 #define EFI_SAL_MC_RENDEZ 0x01000004
144 /// Register the machine check interface layer with SAL.
146 #define EFI_SAL_MC_SET_PARAMS 0x01000005
148 /// Register the physical addresses of locations needed by SAL.
150 #define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
152 /// Flush the instruction or data caches.
154 #define EFI_SAL_CACHE_FLUSH 0x01000008
156 /// Initialize the instruction and data caches.
158 #define EFI_SAL_CACHE_INIT 0x01000009
160 /// Read from the PCI configuration space.
162 #define EFI_SAL_PCI_CONFIG_READ 0x01000010
164 /// Write to the PCI configuration space.
166 #define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
168 /// Return the base frequency of the platform.
170 #define EFI_SAL_FREQ_BASE 0x01000012
172 /// Returns information on the physical processor mapping within the platform.
174 #define EFI_SAL_PHYSICAL_ID_INFO 0x01000013
176 /// Update the contents of firmware blocks.
178 #define EFI_SAL_UPDATE_PAL 0x01000020
180 #define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
181 #define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
184 // SAL Procedure parameter definitions
185 // Not much point in using typedefs or enums because all params
186 // are UINT64 and the entry point is common
190 // Parameter of EFI_SAL_SET_VECTORS
194 #define EFI_SAL_SET_MCA_VECTOR 0x0
195 #define EFI_SAL_SET_INIT_VECTOR 0x1
196 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
198 /// The format of a length_cs_n argument.
202 UINT64 ChecksumValid
: 1;
203 UINT64 Reserved1
: 7;
204 UINT64 ByteChecksum
: 8;
205 UINT64 Reserved2
: 16;
206 } SAL_SET_VECTORS_CS_N
;
209 // Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
211 // Type of information
213 #define EFI_SAL_MCA_STATE_INFO 0x0
214 #define EFI_SAL_INIT_STATE_INFO 0x1
215 #define EFI_SAL_CMC_STATE_INFO 0x2
216 #define EFI_SAL_CP_STATE_INFO 0x3
219 // Parameter of EFI_SAL_MC_SET_PARAMS
221 // Unsigned 64-bit integer value for the parameter type of the machine check interface
223 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
224 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
225 #define EFI_SAL_MC_SET_CPE_PARAM 0x3
227 // Unsigned 64-bit integer value indicating whether interrupt vector or
228 // memory address is specified
230 #define EFI_SAL_MC_SET_INTR_PARAM 0x1
231 #define EFI_SAL_MC_SET_MEM_PARAM 0x2
234 // Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
236 // The encoded value of the entity whose physical address is registered
238 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
241 // Parameter of EFI_SAL_CACHE_FLUSH
243 // Unsigned 64-bit integer denoting type of cache flush operation
245 #define EFI_SAL_FLUSH_I_CACHE 0x01
246 #define EFI_SAL_FLUSH_D_CACHE 0x02
247 #define EFI_SAL_FLUSH_BOTH_CACHE 0x03
248 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
251 // Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE
255 #define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
256 #define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
257 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
259 // The type of PCI configuration address
261 #define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0
262 #define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1
264 /// The format of PCI Compatible Address.
272 UINT64 Reserved
: 32;
275 /// The format of Extended Register Address.
279 UINT64 ExtendedRegister
: 4;
284 UINT64 Reserved
: 20;
285 } SAL_PCI_EXTENDED_REGISTER_ADDRESS
;
288 // Parameter of EFI_SAL_FREQ_BASE
290 // Unsigned 64-bit integer specifying the type of clock source
292 #define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
293 #define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
294 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
297 // Parameter and return value of EFI_SAL_UPDATE_PAL
299 // Return parameter provides additional information on the
300 // failure when the status field contains a value of -3,
303 #define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
304 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
305 #define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
306 #define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
307 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
308 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
309 #define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
310 #define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
312 /// 64-byte header of update data block.
322 } SAL_UPDATE_PAL_DATA_BLOCK
;
324 /// Data structure pointed by the parameter param_buf.
325 /// It is a 16-byte aligned data structure in memory with a length of 32 bytes
326 /// that describes the new firmware. This information is organized in the form
327 /// of a linked list with each element describing one firmware component.
329 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK
{
330 struct _SAL_UPDATE_PAL_INFO_BLOCK
*Next
;
331 struct SAL_UPDATE_PAL_DATA_BLOCK
*DataBlock
;
334 } SAL_UPDATE_PAL_INFO_BLOCK
;
337 /// SAL System Table Definitions.
342 /// The ASCII string representation of "SST_" that confirms the presence of the table.
346 /// The length of the entire table in bytes, starting from offset zero and including the
347 /// header and all entries indicated by the EntryCount field.
351 /// The revision number of the Itanium Processor Family System Abstraction Layer
352 /// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.
356 /// The number of entries in the variable portion of the table.
360 /// A modulo checksum of the entire table and the entries following this table.
364 /// Unused, must be zero.
368 /// Version Number of the SAL_A firmware implementation in BCD format.
372 /// Version Number of the SAL_B firmware implementation in BCD format.
376 /// An ASCII identification string which uniquely identifies the manufacturer
377 /// of the system hardware.
381 /// An ASCII identification string which uniquely identifies a family of
382 /// compatible products from the manufacturer.
386 /// Unused, must be zero.
389 } SAL_SYSTEM_TABLE_HEADER
;
391 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
392 #define EFI_SAL_REVISION 0x0320
396 #define EFI_SAL_ST_ENTRY_POINT 0
397 #define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
398 #define EFI_SAL_ST_PLATFORM_FEATURES 2
399 #define EFI_SAL_ST_TR_USAGE 3
400 #define EFI_SAL_ST_PTC 4
401 #define EFI_SAL_ST_AP_WAKEUP 5
404 // SAL System Type Sizes
406 #define EFI_SAL_ST_ENTRY_POINT_SIZE 48
407 #define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32
408 #define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16
409 #define EFI_SAL_ST_TR_USAGE_SIZE 32
410 #define EFI_SAL_ST_PTC_SIZE 16
411 #define EFI_SAL_ST_AP_WAKEUP_SIZE 16
414 /// Format of Entrypoint Descriptor Entry.
417 UINT8 Type
; ///< Type here should be 0.
421 UINT64 SalGlobalDataPointer
;
423 } SAL_ST_ENTRY_POINT_DESCRIPTOR
;
426 /// Format of Platform Features Descriptor Entry.
429 UINT8 Type
; ///< Type here should be 2.
430 UINT8 PlatformFeatures
;
432 } SAL_ST_PLATFORM_FEATURES
;
435 // Value of Platform Feature List
437 #define SAL_PLAT_FEAT_BUS_LOCK 0x01
438 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
439 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
442 /// Format of Translation Register Descriptor Entry.
445 UINT8 Type
; ///< Type here should be 3.
449 UINT64 VirtualAddress
;
450 UINT64 EncodedPageSize
;
452 } SAL_ST_TR_DECRIPTOR
;
455 // Type of Translation Register
457 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
458 #define EFI_SAL_ST_TR_USAGE_DATA 01
461 /// Definition of Coherence Domain Information.
464 UINT64 NumberOfProcessors
;
465 UINT64 LocalIDRegister
;
466 } SAL_COHERENCE_DOMAIN_INFO
;
469 /// Format of Purge Translation Cache Coherence Domain Entry.
472 UINT8 Type
; ///< Type here should be 4.
474 UINT32 NumberOfDomains
;
475 SAL_COHERENCE_DOMAIN_INFO
*DomainInformation
;
476 } SAL_ST_CACHE_COHERENCE_DECRIPTOR
;
479 /// Format of Application Processor Wake-Up Descriptor Entry.
482 UINT8 Type
; ///< Type here should be 5.
485 UINT64 ExternalInterruptVector
;
486 } SAL_ST_AP_WAKEUP_DECRIPTOR
;
489 /// Format of Firmware Interface Table (FIT) Entry.
497 UINT8 CheckSumValid
: 1;
503 #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
504 #define EFI_SAL_FIT_PAL_B_TYPE 0x01
506 // Type from 0x02 to 0x0D is reserved.
508 #define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E
509 #define EFI_SAL_FIT_PAL_A_TYPE 0x0F
511 // OEM-defined type range is from 0x10 to 0x7E.
512 // Here we defined the PEI_CORE type as 0x10
514 #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
515 #define EFI_SAL_FIT_UNUSED_TYPE 0x7F
520 #define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
521 #define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
522 #define EFI_SAL_FIT_PALB_TYPE 01
525 // Following definitions are for Error Record Structure
529 /// Format of TimeStamp field in Record Header.
542 /// Definition of Record Header.
548 UINT8 ValidationBits
;
550 SAL_TIME_STAMP TimeStamp
;
551 UINT8 OemPlatformId
[16];
554 /// Definition of Section Header.
559 UINT8 ErrorRecoveryInfo
;
561 UINT32 SectionLength
;
565 /// GUID of Processor Machine Check Errors.
567 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
569 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
572 // Bit masks for valid bits of MOD_ERROR_INFO
574 #define CHECK_INFO_VALID_BIT_MASK 0x1
575 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
576 #define RESPONDER_ID_VALID_BIT_MASK 0x4
577 #define TARGER_ID_VALID_BIT_MASK 0x8
578 #define PRECISE_IP_VALID_BIT_MASK 0x10
580 /// Definition of MOD_ERROR_INFO_STRUCT.
583 UINT64 InfoValid
: 1;
585 UINT64 RespValid
: 1;
586 UINT64 TargetValid
: 1;
588 UINT64 Reserved
: 59;
596 /// Definition of CPUID_INFO_STRUCT.
608 // Bit masks for PSI_STATIC_STRUCT.ValidFieldBits
610 #define MIN_STATE_VALID_BIT_MASK 0x1
611 #define BR_VALID_BIT_MASK 0x2
612 #define CR_VALID_BIT_MASK 0x4
613 #define AR_VALID_BIT_MASK 0x8
614 #define RR_VALID_BIT_MASK 0x10
615 #define FR_VALID_BIT_MASK 0x20
617 /// Definition of PSI_STATIC_STRUCT.
620 UINT64 ValidFieldBits
;
621 UINT8 MinStateInfo
[1024];
629 // Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits
631 #define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
632 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
633 #define PROC_CR_LID_VALID_BIT_MASK 0x4
634 #define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
635 #define CPU_INFO_VALID_BIT_MASK 0x1000000
637 /// Definition of Processor Machine Check Error Record.
640 SAL_SEC_HEADER SectionHeader
;
641 UINT64 ValidationBits
;
643 UINT64 ProcStateParameter
;
645 MOD_ERROR_INFO CacheError
[15];
646 MOD_ERROR_INFO TlbError
[15];
647 MOD_ERROR_INFO BusError
[15];
648 MOD_ERROR_INFO RegFileCheck
[15];
649 MOD_ERROR_INFO MsCheck
[15];
651 PSI_STATIC_STRUCT PsiValidData
;
652 } SAL_PROCESSOR_ERROR_RECORD
;
655 /// GUID of Platform Memory Device Error Info.
657 #define SAL_MEMORY_ERROR_RECORD_INFO \
659 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
662 // Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits
664 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
665 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
666 #define MEMORY_ADDR_BIT_MASK 0x4
667 #define MEMORY_NODE_VALID_BIT_MASK 0x8
668 #define MEMORY_CARD_VALID_BIT_MASK 0x10
669 #define MEMORY_MODULE_VALID_BIT_MASK 0x20
670 #define MEMORY_BANK_VALID_BIT_MASK 0x40
671 #define MEMORY_DEVICE_VALID_BIT_MASK 0x80
672 #define MEMORY_ROW_VALID_BIT_MASK 0x100
673 #define MEMORY_COLUMN_VALID_BIT_MASK 0x200
674 #define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
675 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
676 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
677 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
678 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
679 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
680 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
682 /// Definition of Platform Memory Device Error Info Record.
685 SAL_SEC_HEADER SectionHeader
;
686 UINT64 ValidationBits
;
687 UINT64 MemErrorStatus
;
688 UINT64 MemPhysicalAddress
;
689 UINT64 MemPhysicalAddressMask
;
697 UINT16 MemBitPosition
;
698 UINT64 ModRequestorId
;
699 UINT64 ModResponderId
;
701 UINT64 BusSpecificData
;
702 UINT8 MemPlatformOemId
[16];
703 } SAL_MEMORY_ERROR_RECORD
;
706 /// GUID of Platform PCI Bus Error Info.
708 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
710 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
713 // Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits
715 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
716 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
717 #define PCI_BUS_ID_VALID_BIT_MASK 0x4
718 #define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
719 #define PCI_BUS_DATA_VALID_BIT_MASK 0x10
720 #define PCI_BUS_CMD_VALID_BIT_MASK 0x20
721 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
722 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
723 #define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
724 #define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
725 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
728 /// Designated PCI Bus identifier.
736 /// Definition of Platform PCI Bus Error Info Record.
739 SAL_SEC_HEADER SectionHeader
;
740 UINT64 ValidationBits
;
741 UINT64 PciBusErrorStatus
;
742 UINT16 PciBusErrorType
;
745 UINT64 PciBusAddress
;
747 UINT64 PciBusCommand
;
748 UINT64 PciBusRequestorId
;
749 UINT64 PciBusResponderId
;
750 UINT64 PciBusTargetId
;
751 UINT8 PciBusOemId
[16];
752 } SAL_PCI_BUS_ERROR_RECORD
;
755 /// GUID of Platform PCI Component Error Info.
757 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
759 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
762 // Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits
764 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
765 #define PCI_COMP_INFO_VALID_BIT_MASK 0x2
766 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
767 #define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
768 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
769 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
771 /// Format of PCI Component Information to identify the device.
777 UINT8 FunctionNumber
;
784 /// Definition of Platform PCI Component Error Info.
787 SAL_SEC_HEADER SectionHeader
;
788 UINT64 ValidationBits
;
789 UINT64 PciComponentErrorStatus
;
790 PCI_COMP_INFO PciComponentInfo
;
791 UINT32 PciComponentMemNum
;
792 UINT32 PciComponentIoNum
;
793 UINT8 PciBusOemId
[16];
794 } SAL_PCI_COMPONENT_ERROR_RECORD
;
797 /// Platform SEL Device Error Info.
799 #define SAL_SEL_DEVICE_ERROR_RECORD_INFO \
801 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
804 // Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits
806 #define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
807 #define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
808 #define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
809 #define SEL_EVM_REV_VALID_BIT_MASK 0x8;
810 #define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
811 #define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
812 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
813 #define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
814 #define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
815 #define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
817 /// Definition of Platform SEL Device Error Info Record.
820 SAL_SEC_HEADER SectionHeader
;
821 UINT64 ValidationBits
;
833 } SAL_SEL_DEVICE_ERROR_RECORD
;
836 /// GUID of Platform SMBIOS Device Error Info.
838 #define SAL_SMBIOS_ERROR_RECORD_INFO \
840 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
843 // Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits
845 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
846 #define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
847 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
848 #define SMBIOS_DATA_VALID_BIT_MASK 0x8
850 /// Definition of Platform SMBIOS Device Error Info Record.
853 SAL_SEC_HEADER SectionHeader
;
854 UINT64 ValidationBits
;
855 UINT8 SmbiosEventType
;
857 UINT8 SmbiosBcdTimeStamp
[6];
858 } SAL_SMBIOS_DEVICE_ERROR_RECORD
;
861 /// GUID of Platform Specific Error Info.
863 #define SAL_PLATFORM_ERROR_RECORD_INFO \
865 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
868 // Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits
870 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
871 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
872 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
873 #define PLATFORM_TARGET_VALID_BIT_MASK 0x8
874 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
875 #define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
876 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
877 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
879 /// Definition of Platform Specific Error Info Record.
882 SAL_SEC_HEADER SectionHeader
;
883 UINT64 ValidationBits
;
884 UINT64 PlatformErrorStatus
;
885 UINT64 PlatformRequestorId
;
886 UINT64 PlatformResponderId
;
887 UINT64 PlatformTargetId
;
888 UINT64 PlatformBusSpecificData
;
889 UINT8 OemComponentId
[16];
890 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD
;
893 /// Union of all the possible SAL Error Record Types.
896 SAL_RECORD_HEADER
*RecordHeader
;
897 SAL_PROCESSOR_ERROR_RECORD
*SalProcessorRecord
;
898 SAL_PCI_BUS_ERROR_RECORD
*SalPciBusRecord
;
899 SAL_PCI_COMPONENT_ERROR_RECORD
*SalPciComponentRecord
;
900 SAL_SEL_DEVICE_ERROR_RECORD
*ImpiRecord
;
901 SAL_SMBIOS_DEVICE_ERROR_RECORD
*SmbiosRecord
;
902 SAL_PLATFORM_SPECIFIC_ERROR_RECORD
*PlatformRecord
;
903 SAL_MEMORY_ERROR_RECORD
*MemoryRecord
;
905 } SAL_ERROR_RECORDS_POINTERS
;