2 Main SAL API's defined in SAL 3.0 specification.
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 // Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003
22 #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
23 #define EFI_SAL_FIT_PAL_B_TYPE 0x01
25 // type from 0x02 to 0x0E is reserved.
27 #define EFI_SAL_FIT_PAL_A_TYPE 0x0F
29 // OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10
31 #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
32 #define EFI_SAL_FIT_UNUSED_TYPE 0x7F
37 typedef UINTN EFI_SAL_STATUS
;
39 #define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
40 #define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
41 #define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
42 #define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
43 #define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
44 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
45 #define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
46 #define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
49 // Return values from SAL
52 EFI_SAL_STATUS Status
; // register r8
59 // Delivery Mode of IPF CPU.
62 EFI_DELIVERY_MODE_INT
,
63 EFI_DELIVERY_MODE_MPreserved1
,
64 EFI_DELIVERY_MODE_PMI
,
65 EFI_DELIVERY_MODE_MPreserved2
,
66 EFI_DELIVERY_MODE_NMI
,
67 EFI_DELIVERY_MODE_INIT
,
68 EFI_DELIVERY_MODE_MPreserved3
,
69 EFI_DELIVERY_MODE_ExtINT
72 typedef SAL_RETURN_REGS (EFIAPI
*SAL_PROC
)
85 // SAL Procedure FunctionId definition
87 #define EFI_SAL_SET_VECTORS 0x01000000
88 #define EFI_SAL_GET_STATE_INFO 0x01000001
89 #define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
90 #define EFI_SAL_CLEAR_STATE_INFO 0x01000003
91 #define EFI_SAL_MC_RENDEZ 0x01000004
92 #define EFI_SAL_MC_SET_PARAMS 0x01000005
93 #define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
94 #define EFI_SAL_CACHE_FLUSH 0x01000008
95 #define EFI_SAL_CACHE_INIT 0x01000009
96 #define EFI_SAL_PCI_CONFIG_READ 0x01000010
97 #define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
98 #define EFI_SAL_FREQ_BASE 0x01000012
99 #define EFI_SAL_PHYSICAL_ID_INFO 0x01000013
100 #define EFI_SAL_UPDATE_PAL 0x01000020
102 #define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
103 #define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
106 // SAL Procedure parameter definitions
107 // Not much point in using typedefs or enums because all params
108 // are UINT64 and the entry point is common
110 // EFI_SAL_SET_VECTORS
112 #define EFI_SAL_SET_MCA_VECTOR 0x0
113 #define EFI_SAL_SET_INIT_VECTOR 0x1
114 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
118 UINT64 ChecksumValid
: 1;
119 UINT64 Reserved1
: 7;
120 UINT64 ByteChecksum
: 8;
121 UINT64 Reserved2
: 16;
122 } SAL_SET_VECTORS_CS_N
;
125 // EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
126 // EFI_SAL_CLEAR_STATE_INFO
128 #define EFI_SAL_MCA_STATE_INFO 0x0
129 #define EFI_SAL_INIT_STATE_INFO 0x1
130 #define EFI_SAL_CMC_STATE_INFO 0x2
131 #define EFI_SAL_CP_STATE_INFO 0x3
134 // EFI_SAL_MC_SET_PARAMS
136 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
137 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
138 #define EFI_SAL_MC_SET_CPE_PARAM 0x3
140 #define EFI_SAL_MC_SET_INTR_PARAM 0x1
141 #define EFI_SAL_MC_SET_MEM_PARAM 0x2
144 // EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
146 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
149 // EFI_SAL_CACHE_FLUSH
151 #define EFI_SAL_FLUSH_I_CACHE 0x01
152 #define EFI_SAL_FLUSH_D_CACHE 0x02
153 #define EFI_SAL_FLUSH_BOTH_CACHE 0x03
154 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
157 // EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
159 #define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
160 #define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
161 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
169 UINT64 Reserved
: 32;
175 #define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
176 #define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
177 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
180 // EFI_SAL_UPDATE_PAL
182 #define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
183 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
184 #define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
185 #define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
186 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
187 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
188 #define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
189 #define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
198 } SAL_UPDATE_PAL_DATA_BLOCK
;
200 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK
{
201 struct _SAL_UPDATE_PAL_INFO_BLOCK
*Next
;
202 struct SAL_UPDATE_PAL_DATA_BLOCK
*DataBlock
;
205 } SAL_UPDATE_PAL_INFO_BLOCK
;
208 // SAL System Table Definitions
223 } SAL_SYSTEM_TABLE_HEADER
;
226 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
227 #define EFI_SAL_REVISION 0x0300
231 #define EFI_SAL_ST_ENTRY_POINT 0
232 #define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
233 #define EFI_SAL_ST_PLATFORM_FEATURES 2
234 #define EFI_SAL_ST_TR_USAGE 3
235 #define EFI_SAL_ST_PTC 4
236 #define EFI_SAL_ST_AP_WAKEUP 5
240 UINT8 Type
; // Type == 0
244 UINT64 SalGlobalDataPointer
;
246 } SAL_ST_ENTRY_POINT_DESCRIPTOR
;
250 UINT8 Type
; // Type == 2
251 UINT8 PlatformFeatures
;
253 } SAL_ST_PLATFORM_FEATURES
;
256 #define SAL_PLAT_FEAT_BUS_LOCK 0x01
257 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
258 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
262 UINT8 Type
; // Type == 3
266 UINT64 VirtualAddress
;
267 UINT64 EncodedPageSize
;
269 } SAL_ST_TR_DECRIPTOR
;
272 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
273 #define EFI_SAL_ST_TR_USAGE_DATA 01
277 UINT64 NumberOfProcessors
;
278 UINT64 LocalIDRegister
;
279 } SAL_COHERENCE_DOMAIN_INFO
;
284 UINT8 Type
; // Type == 4
286 UINT32 NumberOfDomains
;
287 SAL_COHERENCE_DOMAIN_INFO
*DomainInformation
;
288 } SAL_ST_CACHE_COHERENCE_DECRIPTOR
;
293 UINT8 Type
; // Type == 5
296 UINT64 ExternalInterruptVector
;
297 } SAL_ST_AP_WAKEUP_DECRIPTOR
;
302 #define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
303 #define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
304 #define EFI_SAL_FIT_PALB_TYPE 01
312 UINT8 CheckSumValid
: 1;
317 // SAL Common Record Header
339 UINT8 ValidationBits
;
341 SAL_TIME_STAMP TimeStamp
;
342 UINT8 OemPlatformId
[16];
348 UINT8 ErrorRecoveryInfo
;
350 UINT32 SectionLength
;
354 // SAL Processor Record
356 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
358 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
361 #define CHECK_INFO_VALID_BIT_MASK 0x1
362 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
363 #define RESPONDER_ID_VALID_BIT_MASK 0x4
364 #define TARGER_ID_VALID_BIT_MASK 0x8
365 #define PRECISE_IP_VALID_BIT_MASK 0x10
368 UINT64 InfoValid
: 1;
370 UINT64 RespValid
: 1;
371 UINT64 TargetValid
: 1;
373 UINT64 Reserved
: 59;
391 #define MIN_STATE_VALID_BIT_MASK 0x1
392 #define BR_VALID_BIT_MASK 0x2
393 #define CR_VALID_BIT_MASK 0x4
394 #define AR_VALID_BIT_MASK 0x8
395 #define RR_VALID_BIT_MASK 0x10
396 #define FR_VALID_BIT_MASK 0x20
399 UINT64 ValidFieldBits
;
400 UINT8 MinStateInfo
[1024];
408 #define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
409 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
410 #define PROC_CR_LID_VALID_BIT_MASK 0x4
411 #define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
412 #define CPU_INFO_VALID_BIT_MASK 0x1000000
415 SAL_SEC_HEADER SectionHeader
;
416 UINT64 ValidationBits
;
418 UINT64 ProcStateParameter
;
420 MOD_ERROR_INFO CacheError
[15];
421 MOD_ERROR_INFO TlbError
[15];
422 MOD_ERROR_INFO BusError
[15];
423 MOD_ERROR_INFO RegFileCheck
[15];
424 MOD_ERROR_INFO MsCheck
[15];
426 PSI_STATIC_STRUCT PsiValidData
;
427 } SAL_PROCESSOR_ERROR_RECORD
;
430 // Sal Platform memory Error Record
432 #define SAL_MEMORY_ERROR_RECORD_INFO \
434 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
437 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
438 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
439 #define MEMORY_ADDR_BIT_MASK 0x4
440 #define MEMORY_NODE_VALID_BIT_MASK 0x8
441 #define MEMORY_CARD_VALID_BIT_MASK 0x10
442 #define MEMORY_MODULE_VALID_BIT_MASK 0x20
443 #define MEMORY_BANK_VALID_BIT_MASK 0x40
444 #define MEMORY_DEVICE_VALID_BIT_MASK 0x80
445 #define MEMORY_ROW_VALID_BIT_MASK 0x100
446 #define MEMORY_COLUMN_VALID_BIT_MASK 0x200
447 #define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
448 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
449 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
450 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
451 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
452 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
453 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
456 SAL_SEC_HEADER SectionHeader
;
457 UINT64 ValidationBits
;
458 UINT64 MemErrorStatus
;
459 UINT64 MemPhysicalAddress
;
460 UINT64 MemPhysicalAddressMask
;
468 UINT16 MemBitPosition
;
469 UINT64 ModRequestorId
;
470 UINT64 ModResponderId
;
472 UINT64 BusSpecificData
;
473 UINT8 MemPlatformOemId
[16];
474 } SAL_MEMORY_ERROR_RECORD
;
479 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
481 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
484 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
485 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
486 #define PCI_BUS_ID_VALID_BIT_MASK 0x4
487 #define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
488 #define PCI_BUS_DATA_VALID_BIT_MASK 0x10
489 #define PCI_BUS_CMD_VALID_BIT_MASK 0x20
490 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
491 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
492 #define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
493 #define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
494 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
502 SAL_SEC_HEADER SectionHeader
;
503 UINT64 ValidationBits
;
504 UINT64 PciBusErrorStatus
;
505 UINT16 PciBusErrorType
;
508 UINT64 PciBusAddress
;
510 UINT64 PciBusCommand
;
511 UINT64 PciBusRequestorId
;
512 UINT64 PciBusResponderId
;
513 UINT64 PciBusTargetId
;
514 UINT8 PciBusOemId
[16];
515 } SAL_PCI_BUS_ERROR_RECORD
;
518 // PCI Component Errors
520 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
522 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
525 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
526 #define PCI_COMP_INFO_VALID_BIT_MASK 0x2
527 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
528 #define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
529 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
530 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
536 UINT8 FunctionNumber
;
544 SAL_SEC_HEADER SectionHeader
;
545 UINT64 ValidationBits
;
546 UINT64 PciComponentErrorStatus
;
547 PCI_COMP_INFO PciComponentInfo
;
548 UINT32 PciComponentMemNum
;
549 UINT32 PciComponentIoNum
;
550 UINT8 PciBusOemId
[16];
551 } SAL_PCI_COMPONENT_ERROR_RECORD
;
554 // Sal Device Errors Info.
556 #define SAL_DEVICE_ERROR_RECORD_INFO \
558 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
561 #define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
562 #define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
563 #define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
564 #define SEL_EVM_REV_VALID_BIT_MASK 0x8;
565 #define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
566 #define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
567 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
568 #define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
569 #define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
570 #define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
573 SAL_SEC_HEADER SectionHeader
;
574 UINT64 ValidationBits
;
586 } SAL_DEVICE_ERROR_RECORD
;
589 // Sal SMBIOS Device Errors Info.
591 #define SAL_SMBIOS_ERROR_RECORD_INFO \
593 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
596 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
597 #define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
598 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
599 #define SMBIOS_DATA_VALID_BIT_MASK 0x8
602 SAL_SEC_HEADER SectionHeader
;
603 UINT64 ValidationBits
;
604 UINT8 SmbiosEventType
;
606 UINT8 SmbiosBcdTimeStamp
[6];
607 } SAL_SMBIOS_DEVICE_ERROR_RECORD
;
610 // Sal Platform Specific Errors Info.
612 #define SAL_PLATFORM_ERROR_RECORD_INFO \
614 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
617 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
618 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
619 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
620 #define PLATFORM_TARGET_VALID_BIT_MASK 0x8
621 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
622 #define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
623 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
624 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
627 SAL_SEC_HEADER SectionHeader
;
628 UINT64 ValidationBits
;
629 UINT64 PlatformErrorStatus
;
630 UINT64 PlatformRequestorId
;
631 UINT64 PlatformResponderId
;
632 UINT64 PlatformTargetId
;
633 UINT64 PlatformBusSpecificData
;
634 UINT8 OemComponentId
[16];
635 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD
;
638 // Union of all the possible Sal Record Types
641 SAL_RECORD_HEADER
*RecordHeader
;
642 SAL_PROCESSOR_ERROR_RECORD
*SalProcessorRecord
;
643 SAL_PCI_BUS_ERROR_RECORD
*SalPciBusRecord
;
644 SAL_PCI_COMPONENT_ERROR_RECORD
*SalPciComponentRecord
;
645 SAL_DEVICE_ERROR_RECORD
*ImpiRecord
;
646 SAL_SMBIOS_DEVICE_ERROR_RECORD
*SmbiosRecord
;
647 SAL_PLATFORM_SPECIFIC_ERROR_RECORD
*PlatformRecord
;
648 SAL_MEMORY_ERROR_RECORD
*MemoryRecord
;
650 } SAL_ERROR_RECORDS_POINTERS
;