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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/IndustryStandard/TpmTis.h
2 TPM Interface Specification definition.
3 It covers both TPM1.2 and TPM2.0.
5 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 // Set structure alignment to 1-byte
25 // Register set map as specified in TIS specification Chapter 10
29 /// Used to gain ownership for this particular port.
32 UINT8 Reserved1
[7]; // 1
34 /// Controls interrupts.
36 UINT32 IntEnable
; // 8
38 /// SIRQ vector to be used by the TPM.
40 UINT8 IntVector
; // 0ch
41 UINT8 Reserved2
[3]; // 0dh
43 /// What caused interrupt.
47 /// Shows which interrupts are supported by that particular TPM.
49 UINT32 IntfCapability
; // 14h
51 /// Status Register. Provides status of the TPM.
55 /// Number of consecutive writes that can be done to the TPM.
57 UINT16 BurstCount
; // 19h
60 /// Read or write FIFO, depending on transaction.
62 UINT32 DataFifo
; // 24h
63 UINT8 Reserved4
[0xed8]; // 28h
76 UINT8 Reserved
[0x7b]; // 0f05h
78 /// Alias to I/O legacy space.
80 UINT32 LegacyAddress1
; // 0f80h
82 /// Additional 8 bits for I/O legacy space extension.
84 UINT32 LegacyAddress1Ex
; // 0f84h
86 /// Alias to second I/O legacy space.
88 UINT32 LegacyAddress2
; // 0f88h
90 /// Additional 8 bits for second I/O legacy space extension.
92 UINT32 LegacyAddress2Ex
; // 0f8ch
94 /// Vendor-defined configuration registers.
96 UINT8 VendorDefined
[0x70];// 0f90h
100 // Restore original structure alignment
105 // Define pointer types used to access TIS registers on PC
107 typedef TIS_PC_REGISTERS
*TIS_PC_REGISTERS_PTR
;
110 // Define bits of ACCESS and STATUS registers
114 /// This bit is a 1 to indicate that the other bits in this register are valid.
116 #define TIS_PC_VALID BIT7
118 /// Indicate that this locality is active.
120 #define TIS_PC_ACC_ACTIVE BIT5
122 /// Set to 1 to indicate that this locality had the TPM taken away while
123 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
125 #define TIS_PC_ACC_SEIZED BIT4
127 /// Set to 1 to indicate that TPM MUST reset the
128 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
129 /// locality that is writing this bit.
131 #define TIS_PC_ACC_SEIZE BIT3
133 /// When this bit is 1, another locality is requesting usage of the TPM.
135 #define TIS_PC_ACC_PENDIND BIT2
137 /// Set to 1 to indicate that this locality is requesting to use TPM.
139 #define TIS_PC_ACC_RQUUSE BIT1
141 /// A value of 1 indicates that a T/OS has not been established on the platform
143 #define TIS_PC_ACC_ESTABLISH BIT0
146 /// This field indicates that STS_DATA and STS_EXPECT are valid
148 #define TIS_PC_STS_VALID BIT7
150 /// When this bit is 1, TPM is in the Ready state,
151 /// indicating it is ready to receive a new command.
153 #define TIS_PC_STS_READY BIT6
155 /// Write a 1 to this bit to cause the TPM to execute that command.
157 #define TIS_PC_STS_GO BIT5
159 /// This bit indicates that the TPM has data available as a response.
161 #define TIS_PC_STS_DATA BIT4
163 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
165 #define TIS_PC_STS_EXPECT BIT3
167 /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
169 #define TIS_PC_STS_SELFTEST_DONE BIT2
171 /// Writes a 1 to this bit to force the TPM to re-send the response.
173 #define TIS_PC_STS_RETRY BIT1
176 // Default TimeOut value
178 #define TIS_TIMEOUT_A (750 * 1000) // 750ms
179 #define TIS_TIMEOUT_B (2000 * 1000) // 2s
180 #define TIS_TIMEOUT_C (750 * 1000) // 750ms
181 #define TIS_TIMEOUT_D (750 * 1000) // 750ms