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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/IndustryStandard/TpmTis.h
2 TPM Interface Specification definition.
3 It covers both TPM1.2 and TPM2.0.
5 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // Set structure alignment to 1-byte
19 // Register set map as specified in TIS specification Chapter 10
23 /// Used to gain ownership for this particular port.
26 UINT8 Reserved1
[7]; // 1
28 /// Controls interrupts.
30 UINT32 IntEnable
; // 8
32 /// SIRQ vector to be used by the TPM.
34 UINT8 IntVector
; // 0ch
35 UINT8 Reserved2
[3]; // 0dh
37 /// What caused interrupt.
41 /// Shows which interrupts are supported by that particular TPM.
43 UINT32 IntfCapability
; // 14h
45 /// Status Register. Provides status of the TPM.
49 /// Number of consecutive writes that can be done to the TPM.
51 UINT16 BurstCount
; // 19h
54 /// Read or write FIFO, depending on transaction.
56 UINT32 DataFifo
; // 24h
57 UINT8 Reserved4
[0xed8]; // 28h
70 UINT8 Reserved
[0x7b]; // 0f05h
72 /// Alias to I/O legacy space.
74 UINT32 LegacyAddress1
; // 0f80h
76 /// Additional 8 bits for I/O legacy space extension.
78 UINT32 LegacyAddress1Ex
; // 0f84h
80 /// Alias to second I/O legacy space.
82 UINT32 LegacyAddress2
; // 0f88h
84 /// Additional 8 bits for second I/O legacy space extension.
86 UINT32 LegacyAddress2Ex
; // 0f8ch
88 /// Vendor-defined configuration registers.
90 UINT8 VendorDefined
[0x70]; // 0f90h
94 // Restore original structure alignment
99 // Define pointer types used to access TIS registers on PC
101 typedef TIS_PC_REGISTERS
*TIS_PC_REGISTERS_PTR
;
104 // Define bits of ACCESS and STATUS registers
108 /// This bit is a 1 to indicate that the other bits in this register are valid.
110 #define TIS_PC_VALID BIT7
112 /// Indicate that this locality is active.
114 #define TIS_PC_ACC_ACTIVE BIT5
116 /// Set to 1 to indicate that this locality had the TPM taken away while
117 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
119 #define TIS_PC_ACC_SEIZED BIT4
121 /// Set to 1 to indicate that TPM MUST reset the
122 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
123 /// locality that is writing this bit.
125 #define TIS_PC_ACC_SEIZE BIT3
127 /// When this bit is 1, another locality is requesting usage of the TPM.
129 #define TIS_PC_ACC_PENDIND BIT2
131 /// Set to 1 to indicate that this locality is requesting to use TPM.
133 #define TIS_PC_ACC_RQUUSE BIT1
135 /// A value of 1 indicates that a T/OS has not been established on the platform
137 #define TIS_PC_ACC_ESTABLISH BIT0
140 /// Write a 1 to this bit to notify TPM to cancel currently executing command
142 #define TIS_PC_STS_CANCEL BIT24
144 /// This field indicates that STS_DATA and STS_EXPECT are valid
146 #define TIS_PC_STS_VALID BIT7
148 /// When this bit is 1, TPM is in the Ready state,
149 /// indicating it is ready to receive a new command.
151 #define TIS_PC_STS_READY BIT6
153 /// Write a 1 to this bit to cause the TPM to execute that command.
155 #define TIS_PC_STS_GO BIT5
157 /// This bit indicates that the TPM has data available as a response.
159 #define TIS_PC_STS_DATA BIT4
161 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
163 #define TIS_PC_STS_EXPECT BIT3
165 /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
167 #define TIS_PC_STS_SELFTEST_DONE BIT2
169 /// Writes a 1 to this bit to force the TPM to re-send the response.
171 #define TIS_PC_STS_RETRY BIT1
174 // Default TimeOut value
176 #define TIS_TIMEOUT_A (750 * 1000) // 750ms
177 #define TIS_TIMEOUT_B (2000 * 1000) // 2s
178 #define TIS_TIMEOUT_C (750 * 1000) // 750ms
179 #define TIS_TIMEOUT_D (750 * 1000) // 750ms