2 Support for PCI 2.2 standard.
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 #define PCI_MAX_SEGMENT 0
22 #define PCI_MAX_BUS 255
24 #define PCI_MAX_DEVICE 31
25 #define PCI_MAX_FUNC 7
30 #define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
44 } PCI_DEVICE_INDEPENDENT_REGION
;
49 UINT16 SubsystemVendorID
;
51 UINT32 ExpansionRomBar
;
59 } PCI_DEVICE_HEADER_TYPE_REGION
;
62 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
63 PCI_DEVICE_HEADER_TYPE_REGION Device
;
71 UINT8 SecondaryLatencyTimer
;
74 UINT16 SecondaryStatus
;
77 UINT16 PrefetchableMemoryBase
;
78 UINT16 PrefetchableMemoryLimit
;
79 UINT32 PrefetchableBaseUpper32
;
80 UINT32 PrefetchableLimitUpper32
;
82 UINT16 IoLimitUpper16
;
85 UINT32 ExpansionRomBAR
;
89 } PCI_BRIDGE_CONTROL_REGISTER
;
92 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
93 PCI_BRIDGE_CONTROL_REGISTER Bridge
;
102 UINT32 CardBusSocketReg
; // Cardus Socket/ExCA Base
106 UINT16 SecondaryStatus
; // Secondary Status
107 UINT8 PciBusNumber
; // PCI Bus Number
108 UINT8 CardBusBusNumber
; // CardBus Bus Number
109 UINT8 SubordinateBusNumber
; // Subordinate Bus Number
110 UINT8 CardBusLatencyTimer
; // CardBus Latency Timer
111 UINT32 MemoryBase0
; // Memory Base Register 0
112 UINT32 MemoryLimit0
; // Memory Limit Register 0
116 UINT32 IoLimit0
; // I/O Base Register 0
117 UINT32 IoBase1
; // I/O Limit Register 0
119 UINT8 InterruptLine
; // Interrupt Line
120 UINT8 InterruptPin
; // Interrupt Pin
121 UINT16 BridgeControl
; // Bridge Control
122 } PCI_CARDBUS_CONTROL_REGISTER
;
125 // Definitions of PCI class bytes and manipulation macros.
127 #define PCI_CLASS_OLD 0x00
128 #define PCI_CLASS_OLD_OTHER 0x00
129 #define PCI_CLASS_OLD_VGA 0x01
131 #define PCI_CLASS_MASS_STORAGE 0x01
132 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
133 #define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
134 #define PCI_CLASS_IDE 0x01
135 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
136 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
137 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
138 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
140 #define PCI_CLASS_NETWORK 0x02
141 #define PCI_CLASS_NETWORK_ETHERNET 0x00
142 #define PCI_CLASS_ETHERNET 0x00 // obsolete
143 #define PCI_CLASS_NETWORK_TOKENRING 0x01
144 #define PCI_CLASS_NETWORK_FDDI 0x02
145 #define PCI_CLASS_NETWORK_ATM 0x03
146 #define PCI_CLASS_NETWORK_ISDN 0x04
147 #define PCI_CLASS_NETWORK_OTHER 0x80
149 #define PCI_CLASS_DISPLAY 0x03
150 #define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
151 #define PCI_CLASS_DISPLAY_VGA 0x00
152 #define PCI_CLASS_VGA 0x00 // obsolete
153 #define PCI_CLASS_DISPLAY_XGA 0x01
154 #define PCI_CLASS_DISPLAY_3D 0x02
155 #define PCI_CLASS_DISPLAY_OTHER 0x80
156 #define PCI_CLASS_DISPLAY_GFX 0x80
157 #define PCI_CLASS_GFX 0x80 // obsolete
158 #define PCI_CLASS_BRIDGE 0x06
159 #define PCI_CLASS_BRIDGE_HOST 0x00
160 #define PCI_CLASS_BRIDGE_ISA 0x01
161 #define PCI_CLASS_ISA 0x01 // obsolete
162 #define PCI_CLASS_BRIDGE_EISA 0x02
163 #define PCI_CLASS_BRIDGE_MCA 0x03
164 #define PCI_CLASS_BRIDGE_P2P 0x04
165 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
166 #define PCI_CLASS_BRIDGE_NUBUS 0x06
167 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
168 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
169 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
170 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
171 #define PCI_CLASS_SERIAL 0x0C
172 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
173 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
174 #define PCI_CLASS_SERIAL_SSA 0x02
175 #define PCI_CLASS_SERIAL_USB 0x03
176 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
177 #define PCI_CLASS_SERIAL_SMB 0x05
179 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
180 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
181 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
183 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
184 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
185 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
186 #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
187 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
188 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
189 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
190 #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
191 #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
192 #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
193 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
194 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
195 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
197 #define HEADER_TYPE_DEVICE 0x00
198 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
199 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
201 #define HEADER_TYPE_MULTI_FUNCTION 0x80
202 #define HEADER_LAYOUT_CODE 0x7f
204 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
205 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
206 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
208 #define PCI_DEVICE_ROMBAR 0x30
209 #define PCI_BRIDGE_ROMBAR 0x38
211 #define PCI_MAX_BAR 6
212 #define PCI_MAX_CONFIG_OFFSET 0x100
214 // bugbug: this is supported in PCI spec v2.3
216 #define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
218 #define PCI_VENDOR_ID_OFFSET 0x00
219 #define PCI_DEVICE_ID_OFFSET 0x02
220 #define PCI_COMMAND_OFFSET 0x04
221 #define PCI_PRIMARY_STATUS_OFFSET 0x06
222 #define PCI_REVISION_ID_OFFSET 0x08
223 #define PCI_CLASSCODE_OFFSET 0x09
224 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
225 #define PCI_LATENCY_TIMER_OFFSET 0x0D
226 #define PCI_HEADER_TYPE_OFFSET 0x0E
227 #define PCI_BIST_OFFSET 0x0F
229 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
230 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
232 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
233 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
234 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
254 } PCI_CONFIG_ACCESS_CF8
;
258 #define EFI_ROOT_BRIDGE_LIST 'eprb'
259 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
260 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
261 #define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
262 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
263 #define PCI_CODE_TYPE_EFI_IMAGE 0x03
264 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
266 #define EFI_PCI_COMMAND_IO_SPACE 0x0001
267 #define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
268 #define EFI_PCI_COMMAND_BUS_MASTER 0x0004
269 #define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
270 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
271 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
272 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
273 #define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
274 #define EFI_PCI_COMMAND_SERR 0x0100
275 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
277 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
278 #define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
279 #define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
280 #define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
281 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
282 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
283 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
284 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
285 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
286 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
287 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
288 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
291 // Following are the PCI-CARDBUS bridge control bit
293 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
294 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
295 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
296 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
299 // Following are the PCI status control bit
301 #define EFI_PCI_STATUS_CAPABILITY 0x0010
302 #define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
303 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
304 #define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
306 #define EFI_PCI_CAPABILITY_PTR 0x34
307 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
311 UINT16 Signature
; // 0xaa55
312 UINT8 Reserved
[0x16];
314 } PCI_EXPANSION_ROM_HEADER
;
317 UINT16 Signature
; // 0xaa55
318 UINT16 InitializationSize
;
319 UINT32 EfiSignature
; // 0x0EF1
321 UINT16 EfiMachineType
;
322 UINT16 CompressionType
;
324 UINT16 EfiImageHeaderOffset
;
326 } EFI_PCI_EXPANSION_ROM_HEADER
;
329 UINT16 Signature
; // 0xaa55
333 } EFI_LEGACY_EXPANSION_ROM_HEADER
;
337 PCI_EXPANSION_ROM_HEADER
*Generic
;
338 EFI_PCI_EXPANSION_ROM_HEADER
*Efi
;
339 EFI_LEGACY_EXPANSION_ROM_HEADER
*PcAt
;
340 } EFI_PCI_ROM_HEADER
;
343 UINT32 Signature
; // "PCIR"
355 } PCI_DATA_STRUCTURE
;
358 // PCI Capability List IDs and records
360 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
361 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
362 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
363 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
364 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
365 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
366 #define EFI_PCI_CAPABILITY_ID_PCIX 0x07
368 // bugbug: this ID is defined in PCI spec v2.3
370 #define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
375 } EFI_PCI_CAPABILITY_HDR
;
378 // Capability EFI_PCI_CAPABILITY_ID_PMI
381 EFI_PCI_CAPABILITY_HDR Hdr
;
384 UINT8 BridgeExtention
;
386 } EFI_PCI_CAPABILITY_PMI
;
389 // Capability EFI_PCI_CAPABILITY_ID_AGP
392 EFI_PCI_CAPABILITY_HDR Hdr
;
397 } EFI_PCI_CAPABILITY_AGP
;
400 // Capability EFI_PCI_CAPABILITY_ID_VPD
403 EFI_PCI_CAPABILITY_HDR Hdr
;
406 } EFI_PCI_CAPABILITY_VPD
;
409 // Capability EFI_PCI_CAPABILITY_ID_SLOTID
412 EFI_PCI_CAPABILITY_HDR Hdr
;
415 } EFI_PCI_CAPABILITY_SLOTID
;
418 // Capability EFI_PCI_CAPABILITY_ID_MSI
421 EFI_PCI_CAPABILITY_HDR Hdr
;
425 } EFI_PCI_CAPABILITY_MSI32
;
428 EFI_PCI_CAPABILITY_HDR Hdr
;
430 UINT32 MsgAddrRegLsdw
;
431 UINT32 MsgAddrRegMsdw
;
433 } EFI_PCI_CAPABILITY_MSI64
;
436 // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
439 EFI_PCI_CAPABILITY_HDR Hdr
;
441 // not finished - fields need to go here
443 } EFI_PCI_CAPABILITY_HOTPLUG
;
446 // Capability EFI_PCI_CAPABILITY_ID_PCIX
449 EFI_PCI_CAPABILITY_HDR Hdr
;
452 } EFI_PCI_CAPABILITY_PCIX
;
455 EFI_PCI_CAPABILITY_HDR Hdr
;
458 UINT32 SplitTransCtrlRegUp
;
459 UINT32 SplitTransCtrlRegDn
;
460 } EFI_PCI_CAPABILITY_PCIX_BRDG
;
462 #define DEVICE_ID_NOCARE 0xFFFF
464 #define PCI_ACPI_UNUSED 0
465 #define PCI_BAR_NOCHANGE 0
466 #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
467 #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
468 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
469 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
471 #define PCI_BAR_IDX0 0x00
472 #define PCI_BAR_IDX1 0x01
473 #define PCI_BAR_IDX2 0x02
474 #define PCI_BAR_IDX3 0x03
475 #define PCI_BAR_IDX4 0x04
476 #define PCI_BAR_IDX5 0x05
477 #define PCI_BAR_ALL 0xFF