2 Support for PCI 2.2 standard.
4 Copyright (c) 2006 - 2007, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 #define PCI_MAX_SEGMENT 0
22 #define PCI_MAX_BUS 255
24 #define PCI_MAX_DEVICE 31
25 #define PCI_MAX_FUNC 7
30 #define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
44 } PCI_DEVICE_INDEPENDENT_REGION
;
49 UINT16 SubsystemVendorID
;
51 UINT32 ExpansionRomBar
;
59 } PCI_DEVICE_HEADER_TYPE_REGION
;
62 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
63 PCI_DEVICE_HEADER_TYPE_REGION Device
;
71 UINT8 SecondaryLatencyTimer
;
74 UINT16 SecondaryStatus
;
77 UINT16 PrefetchableMemoryBase
;
78 UINT16 PrefetchableMemoryLimit
;
79 UINT32 PrefetchableBaseUpper32
;
80 UINT32 PrefetchableLimitUpper32
;
82 UINT16 IoLimitUpper16
;
85 UINT32 ExpansionRomBAR
;
89 } PCI_BRIDGE_CONTROL_REGISTER
;
92 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
93 PCI_BRIDGE_CONTROL_REGISTER Bridge
;
102 UINT32 CardBusSocketReg
; // Cardus Socket/ExCA Base
106 UINT16 SecondaryStatus
; // Secondary Status
107 UINT8 PciBusNumber
; // PCI Bus Number
108 UINT8 CardBusBusNumber
; // CardBus Bus Number
109 UINT8 SubordinateBusNumber
; // Subordinate Bus Number
110 UINT8 CardBusLatencyTimer
; // CardBus Latency Timer
111 UINT32 MemoryBase0
; // Memory Base Register 0
112 UINT32 MemoryLimit0
; // Memory Limit Register 0
116 UINT32 IoLimit0
; // I/O Base Register 0
117 UINT32 IoBase1
; // I/O Limit Register 0
119 UINT8 InterruptLine
; // Interrupt Line
120 UINT8 InterruptPin
; // Interrupt Pin
121 UINT16 BridgeControl
; // Bridge Control
122 } PCI_CARDBUS_CONTROL_REGISTER
;
125 // Definitions of PCI class bytes and manipulation macros.
127 #define PCI_CLASS_OLD 0x00
128 #define PCI_CLASS_OLD_OTHER 0x00
129 #define PCI_CLASS_OLD_VGA 0x01
131 #define PCI_CLASS_MASS_STORAGE 0x01
132 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
133 #define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
134 #define PCI_CLASS_IDE 0x01
135 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
136 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
137 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
138 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
140 #define PCI_CLASS_NETWORK 0x02
141 #define PCI_CLASS_NETWORK_ETHERNET 0x00
142 #define PCI_CLASS_ETHERNET 0x00 // obsolete
143 #define PCI_CLASS_NETWORK_TOKENRING 0x01
144 #define PCI_CLASS_NETWORK_FDDI 0x02
145 #define PCI_CLASS_NETWORK_ATM 0x03
146 #define PCI_CLASS_NETWORK_ISDN 0x04
147 #define PCI_CLASS_NETWORK_OTHER 0x80
149 #define PCI_CLASS_DISPLAY 0x03
150 #define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
151 #define PCI_CLASS_DISPLAY_VGA 0x00
152 #define PCI_CLASS_VGA 0x00 // obsolete
153 #define PCI_CLASS_DISPLAY_XGA 0x01
154 #define PCI_CLASS_DISPLAY_3D 0x02
155 #define PCI_CLASS_DISPLAY_OTHER 0x80
156 #define PCI_CLASS_DISPLAY_GFX 0x80
157 #define PCI_CLASS_GFX 0x80 // obsolete
158 #define PCI_CLASS_BRIDGE 0x06
159 #define PCI_CLASS_BRIDGE_HOST 0x00
160 #define PCI_CLASS_BRIDGE_ISA 0x01
161 #define PCI_CLASS_ISA 0x01 // obsolete
162 #define PCI_CLASS_BRIDGE_EISA 0x02
163 #define PCI_CLASS_BRIDGE_MCA 0x03
164 #define PCI_CLASS_BRIDGE_P2P 0x04
165 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
166 #define PCI_CLASS_BRIDGE_NUBUS 0x06
167 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
168 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
169 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
170 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
172 #define PCI_CLASS_SCC 0x07 // Simple communications controllers
173 #define PCI_SUBCLASS_SERIAL 0x00
174 #define PCI_IF_GENERIC_XT 0x00
175 #define PCI_IF_16450 0x01
176 #define PCI_IF_16550 0x02
177 #define PCI_IF_16650 0x03
178 #define PCI_IF_16750 0x04
179 #define PCI_IF_16850 0x05
180 #define PCI_IF_16950 0x06
181 #define PCI_SUBCLASS_PARALLEL 0x01
182 #define PCI_IF_PARALLEL_PORT 0x00
183 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
184 #define PCI_IF_ECP_PARALLEL_PORT 0x02
185 #define PCI_IF_1284_CONTROLLER 0x03
186 #define PCI_IF_1284_DEVICE 0xFE
187 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
188 #define PCI_SUBCLASS_MODEM 0x03
189 #define PCI_IF_GENERIC_MODEM 0x00
190 #define PCI_IF_16450_MODEM 0x01
191 #define PCI_IF_16550_MODEM 0x02
192 #define PCI_IF_16650_MODEM 0x03
193 #define PCI_IF_16750_MODEM 0x04
194 #define PCI_SUBCLASS_OTHER 0x80
196 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
197 #define PCI_SUBCLASS_PIC 0x00
198 #define PCI_IF_8259_PIC 0x00
199 #define PCI_IF_ISA_PIC 0x01
200 #define PCI_IF_EISA_PIC 0x02
201 #define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
202 #define PCI_IF_APIC_CONTROLLER2 0x20
203 #define PCI_SUBCLASS_TIMER 0x02
204 #define PCI_IF_8254_TIMER 0x00
205 #define PCI_IF_ISA_TIMER 0x01
206 #define PCI_EISA_TIMER 0x02
207 #define PCI_SUBCLASS_RTC 0x03
208 #define PCI_IF_GENERIC_RTC 0x00
209 #define PCI_IF_ISA_RTC 0x00
210 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
212 #define PCI_CLASS_INPUT_DEVICE 0x09
213 #define PCI_SUBCLASS_KEYBOARD 0x00
214 #define PCI_SUBCLASS_PEN 0x01
215 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
216 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
217 #define PCI_SUBCLASS_GAMEPORT 0x04
219 #define PCI_CLASS_DOCKING_STATION 0x0A
221 #define PCI_CLASS_PROCESSOR 0x0B
222 #define PCI_SUBCLASS_PROC_386 0x00
223 #define PCI_SUBCLASS_PROC_486 0x01
224 #define PCI_SUBCLASS_PROC_PENTIUM 0x02
225 #define PCI_SUBCLASS_PROC_ALPHA 0x10
226 #define PCI_SUBCLASS_PROC_POWERPC 0x20
227 #define PCI_SUBCLASS_PROC_MIPS 0x30
228 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
230 #define PCI_CLASS_SERIAL 0x0C
231 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
232 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
233 #define PCI_CLASS_SERIAL_SSA 0x02
234 #define PCI_CLASS_SERIAL_USB 0x03
235 #define PCI_IF_EHCI 0x20
236 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
237 #define PCI_CLASS_SERIAL_SMB 0x05
239 #define PCI_CLASS_WIRELESS 0x0D
240 #define PCI_SUBCLASS_IRDA 0x00
241 #define PCI_SUBCLASS_IR 0x01
242 #define PCI_SUBCLASS_RF 0x02
244 #define PCI_CLASS_INTELLIGENT_IO 0x0E
246 #define PCI_CLASS_SATELLITE 0x0F
247 #define PCI_SUBCLASS_TV 0x01
248 #define PCI_SUBCLASS_AUDIO 0x02
249 #define PCI_SUBCLASS_VOICE 0x03
250 #define PCI_SUBCLASS_DATA 0x04
252 #define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
253 #define PCI_SUBCLASS_NET_COMPUT 0x00
254 #define PCI_SUBCLASS_ENTERTAINMENT 0x10
256 #define PCI_CLASS_DPIO 0x11
258 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
259 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
260 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
262 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
263 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
264 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
265 #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
266 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
267 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
268 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
269 #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
270 #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
271 #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
272 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
273 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
274 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
275 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
277 #define HEADER_TYPE_DEVICE 0x00
278 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
279 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
281 #define HEADER_TYPE_MULTI_FUNCTION 0x80
282 #define HEADER_LAYOUT_CODE 0x7f
284 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
285 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
286 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
288 #define PCI_DEVICE_ROMBAR 0x30
289 #define PCI_BRIDGE_ROMBAR 0x38
291 #define PCI_MAX_BAR 0x0006
292 #define PCI_MAX_CONFIG_OFFSET 0x0100
294 #define PCI_VENDOR_ID_OFFSET 0x00
295 #define PCI_DEVICE_ID_OFFSET 0x02
296 #define PCI_COMMAND_OFFSET 0x04
297 #define PCI_PRIMARY_STATUS_OFFSET 0x06
298 #define PCI_REVISION_ID_OFFSET 0x08
299 #define PCI_CLASSCODE_OFFSET 0x09
300 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
301 #define PCI_LATENCY_TIMER_OFFSET 0x0D
302 #define PCI_HEADER_TYPE_OFFSET 0x0E
303 #define PCI_BIST_OFFSET 0x0F
304 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
305 #define PCI_CARDBUS_CIS_OFFSET 0x28
306 #define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
307 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
308 #define PCI_SID_OFFSET 0x2E // SubSystem ID
309 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
310 #define PCI_EXPANSION_ROM_BASE 0x30
311 #define PCI_CAPBILITY_POINTER_OFFSET 0x34
312 #define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
313 #define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
314 #define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
315 #define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
317 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
318 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
320 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
321 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
322 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
325 // Interrupt Line "Unknown" or "No connection" value defined for x86 based system
327 #define PCI_INT_LINE_UNKNOWN 0xFF
339 } PCI_CONFIG_ACCESS_CF8
;
343 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
344 #define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
345 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
346 #define PCI_CODE_TYPE_EFI_IMAGE 0x03
347 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
349 #define EFI_PCI_COMMAND_IO_SPACE 0x0001
350 #define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
351 #define EFI_PCI_COMMAND_BUS_MASTER 0x0004
352 #define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
353 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
354 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
355 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
356 #define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
357 #define EFI_PCI_COMMAND_SERR 0x0100
358 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
360 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
361 #define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
362 #define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
363 #define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
364 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
365 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
366 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
367 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
368 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
369 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
370 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
371 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
374 // Following are the PCI-CARDBUS bridge control bit
376 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
377 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
378 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
379 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
382 // Following are the PCI status control bit
384 #define EFI_PCI_STATUS_CAPABILITY 0x0010
385 #define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
386 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
387 #define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
389 #define EFI_PCI_CAPABILITY_PTR 0x34
390 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
394 UINT16 Signature
; // 0xaa55
395 UINT8 Reserved
[0x16];
397 } PCI_EXPANSION_ROM_HEADER
;
400 UINT16 Signature
; // 0xaa55
402 UINT8 InitEntryPoint
[3];
403 UINT8 Reserved
[0x12];
405 } EFI_LEGACY_EXPANSION_ROM_HEADER
;
408 UINT32 Signature
; // "PCIR"
420 } PCI_DATA_STRUCTURE
;
423 // PCI Capability List IDs and records
425 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
426 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
427 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
428 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
429 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
430 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
431 #define EFI_PCI_CAPABILITY_ID_PCIX 0x07
436 } EFI_PCI_CAPABILITY_HDR
;
439 // Capability EFI_PCI_CAPABILITY_ID_PMI
442 EFI_PCI_CAPABILITY_HDR Hdr
;
445 UINT8 BridgeExtention
;
447 } EFI_PCI_CAPABILITY_PMI
;
450 // Capability EFI_PCI_CAPABILITY_ID_AGP
453 EFI_PCI_CAPABILITY_HDR Hdr
;
458 } EFI_PCI_CAPABILITY_AGP
;
461 // Capability EFI_PCI_CAPABILITY_ID_VPD
464 EFI_PCI_CAPABILITY_HDR Hdr
;
467 } EFI_PCI_CAPABILITY_VPD
;
470 // Capability EFI_PCI_CAPABILITY_ID_SLOTID
473 EFI_PCI_CAPABILITY_HDR Hdr
;
476 } EFI_PCI_CAPABILITY_SLOTID
;
479 // Capability EFI_PCI_CAPABILITY_ID_MSI
482 EFI_PCI_CAPABILITY_HDR Hdr
;
486 } EFI_PCI_CAPABILITY_MSI32
;
489 EFI_PCI_CAPABILITY_HDR Hdr
;
491 UINT32 MsgAddrRegLsdw
;
492 UINT32 MsgAddrRegMsdw
;
494 } EFI_PCI_CAPABILITY_MSI64
;
497 // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
500 EFI_PCI_CAPABILITY_HDR Hdr
;
502 // not finished - fields need to go here
504 } EFI_PCI_CAPABILITY_HOTPLUG
;
507 // Capability EFI_PCI_CAPABILITY_ID_PCIX
510 EFI_PCI_CAPABILITY_HDR Hdr
;
513 } EFI_PCI_CAPABILITY_PCIX
;
516 EFI_PCI_CAPABILITY_HDR Hdr
;
519 UINT32 SplitTransCtrlRegUp
;
520 UINT32 SplitTransCtrlRegDn
;
521 } EFI_PCI_CAPABILITY_PCIX_BRDG
;
523 #define DEVICE_ID_NOCARE 0xFFFF
525 #define PCI_ACPI_UNUSED 0
526 #define PCI_BAR_NOCHANGE 0
527 #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
528 #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
529 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
530 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
532 #define PCI_BAR_IDX0 0x00
533 #define PCI_BAR_IDX1 0x01
534 #define PCI_BAR_IDX2 0x02
535 #define PCI_BAR_IDX3 0x03
536 #define PCI_BAR_IDX4 0x04
537 #define PCI_BAR_IDX5 0x05
538 #define PCI_BAR_ALL 0xFF
543 // NOTE: The following header files are included here for
544 // compatibility consideration.