4 Copyright (c) 2006 -2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef __PAL_CALL_LIB_H__
17 #define __PAL_CALL_LIB_H__
19 #define PAL_SUCCESS 0x0
22 // CacheType of PAL_CACHE_FLUSH.
24 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
25 #define PAL_CACHE_FLUSH_DATA_ALL 2
26 #define PAL_CACHE_FLUSH_ALL 3
27 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
31 // Bitmask of Opearation of PAL_CACHE_FLUSH.
33 #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0
34 #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0
35 #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1
36 #define PAL_CACHE_FLUSH_NO_INTERRUPT 0
39 PAL Procedure - PAL_CACHE_FLUSH.
41 Flush the instruction or data caches. It is required by IPF.
42 The PAL procedure supports the Static Registers calling
43 convention. It could be called at virtual mode and physical
46 @param Index Index of PAL_CACHE_FLUSH within the
47 list of PAL procedures.
48 @param CacheType Unsigned 64-bit integer indicating
50 @param Operation Formatted bit vector indicating the
51 operation of this call.
52 @param ProgressIndicator Unsigned 64-bit integer specifying
53 the starting position of the flush
56 @retval 2 Call completed without error, but a PMI
57 was taken during the execution of this
59 @retval 1 Call has not completed flushing due to
61 @retval 0 Call completed without error
62 @retval -2 Invalid argument
63 @retval -3 Call completed with error
65 @return R9 Unsigned 64-bit integer specifying the vector
66 number of the pending interrupt.
67 @return R10 Unsigned 64-bit integer specifying the
68 starting position of the flush operation.
69 @return R11 Unsigned 64-bit integer specifying the vector
70 number of the pending interrupt.
73 #define PAL_CACHE_FLUSH 1
77 // Attributes of PAL_CACHE_CONFIG_INFO1
79 #define PAL_CACHE_ATTR_WT 0
80 #define PAL_CACHE_ATTR_WB 1
83 // PAL_CACHE_CONFIG_INFO1.StoreHint
85 #define PAL_CACHE_STORE_TEMPORAL 0
86 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
89 // PAL_CACHE_CONFIG_INFO1.StoreHint
91 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
92 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
95 // PAL_CACHE_CONFIG_INFO1.StoreHint
97 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
98 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
99 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
102 // Detail the characteristics of a given processor controlled
103 // cache in the cache hierarchy.
106 UINT64 IsUnified
: 1;
107 UINT64 Attributes
: 2;
108 UINT64 Associativity
:8;
111 UINT64 StoreLatency
:8;
114 } PAL_CACHE_INFO_RETURN1
;
117 // Detail the characteristics of a given processor controlled
118 // cache in the cache hierarchy.
122 UINT64 AliasBoundary
:8;
125 } PAL_CACHE_INFO_RETURN2
;
128 PAL Procedure - PAL_CACHE_INFO.
130 Return detailed instruction or data cache information. It is
131 required by IPF. The PAL procedure supports the Static
132 Registers calling convention. It could be called at virtual
133 mode and physical mode.
135 @param Index Index of PAL_CACHE_INFO within the list of
137 @param CacheLevel Unsigned 64-bit integer specifying the
138 level in the cache hierarchy for which
139 information is requested. This value must
140 be between 0 and one less than the value
141 returned in the cache_levels return value
142 from PAL_CACHE_SUMMARY.
143 @param CacheType Unsigned 64-bit integer with a value of 1
144 for instruction cache and 2 for data or
145 unified cache. All other values are
147 @param Reserved Should be 0.
149 @retval 0 Call completed without error
150 @retval -2 Invalid argument
151 @retval -3 Call completed with error
153 @return R9 Detail the characteristics of a given
154 processor controlled cache in the cache
155 hierarchy. See PAL_CACHE_INFO_RETURN1.
156 @return R10 Detail the characteristics of a given
157 processor controlled cache in the cache
158 hierarchy. See PAL_CACHE_INFO_RETURN2.
159 @return R11 Reserved with 0.
162 #define PAL_CACHE_INFO 2
167 // Level of PAL_CACHE_INIT.
169 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
174 #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1
175 #define PAL_CACHE_INIT_TYPE_DATA 0x2
176 #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3
179 // Restrict of PAL_CACHE_INIT.
181 #define PAL_CACHE_INIT_NO_RESTRICT 0
182 #define PAL_CACHE_INIT_RESTRICTED 1
185 PAL Procedure - PAL_CACHE_INIT.
187 Initialize the instruction or data caches. It is required by
188 IPF. The PAL procedure supports the Static Registers calling
189 convention. It could be called at physical mode.
191 @param Index Index of PAL_CACHE_INIT within the list of PAL
193 @param Level Unsigned 64-bit integer containing the level of
194 cache to initialize. If the cache level can be
195 initialized independently, only that level will
196 be initialized. Otherwise
197 implementation-dependent side-effects will
199 @param CacheType Unsigned 64-bit integer with a value of 1 to
200 initialize the instruction cache, 2 to
201 initialize the data cache, or 3 to
202 initialize both. All other values are
204 @param Restrict Unsigned 64-bit integer with a value of 0 or
205 1. All other values are reserved. If
206 restrict is 1 and initializing the specified
207 level and cache_type of the cache would
208 cause side-effects, PAL_CACHE_INIT will
209 return -4 instead of initializing the cache.
211 @retval 0 Call completed without error
212 @retval -2 Invalid argument
213 @retval -3 Call completed with error.
214 @retval -4 Call could not initialize the specified
215 level and cache_type of the cache without
216 side-effects and restrict was 1.
219 #define PAL_CACHE_INIT 3
223 // PAL_CACHE_PROTECTION.Method.
225 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
226 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
227 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
228 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
233 // PAL_CACHE_PROTECTION.TagOrData.
235 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
236 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
237 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
238 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
241 // 32-bit protection information structures.
250 } PAL_CACHE_PROTECTION
;
253 PAL Procedure - PAL_CACHE_PROT_INFO.
255 Return instruction or data cache protection information. It is
256 required by IPF. The PAL procedure supports the Static
257 Registers calling convention. It could be called at physical
258 mode and Virtual mode.
260 @param Index Index of PAL_CACHE_PROT_INFO within the list of
262 @param CacheLevel Unsigned 64-bit integer specifying the level
263 in the cache hierarchy for which information
264 is requested. This value must be between 0
265 and one less than the value returned in the
266 cache_levels return value from
268 @param CacheType Unsigned 64-bit integer with a value of 1
269 for instruction cache and 2 for data or
270 unified cache. All other values are
273 @retval 0 Call completed without error
274 @retval -2 Invalid argument
275 @retval -3 Call completed with error.
277 @return R9 Detail the characteristics of a given
278 processor controlled cache in the cache
279 hierarchy. See PAL_CACHE_PROTECTION[0..1].
280 @return R10 Detail the characteristics of a given
281 processor controlled cache in the cache
282 hierarchy. See PAL_CACHE_PROTECTION[2..3].
283 @return R11 Detail the characteristics of a given
284 processor controlled cache in the cache
285 hierarchy. See PAL_CACHE_PROTECTION[4..5].
288 #define PAL_CACHE_PROT_INFO 38
292 @param ThreadId The thread identifier of the logical
293 processor for which information is being
294 returned. This value will be unique on a per
297 @param CoreId The core identifier of the logical processor
298 for which information is being returned.
299 This value will be unique on a per physical
300 processor package basis.
304 UINT64 ThreadId
: 16;
305 UINT64 Reserved1
: 16;
307 UINT64 Reserved2
: 16;
308 } PAL_PCOC_N_CACHE_INFO1
;
312 @param LogicalAddress Logical address: geographical address
313 of the logical processor for which
314 information is being returned. This is
315 the same value that is returned by the
316 PAL_FIXED_ADDR procedure when it is
317 called on the logical processor.
321 UINT64 LogicalAddress
: 16;
322 UINT64 Reserved1
: 16;
323 UINT64 Reserved2
: 32;
324 } PAL_PCOC_N_CACHE_INFO2
;
327 PAL Procedure - PAL_CACHE_SHARED_INFO.
329 Returns information on which logical processors share caches.
330 It is optional. The PAL procedure supports the Static
331 Registers calling convention. It could be called at physical
332 mode and Virtual mode.
334 @param Index Index of PAL_CACHE_SHARED_INFO within the list
336 @param CacheLevel Unsigned 64-bit integer specifying the
337 level in the cache hierarchy for which
338 information is requested. This value must
339 be between 0 and one less than the value
340 returned in the cache_levels return value
341 from PAL_CACHE_SUMMARY.
342 @param CacheType Unsigned 64-bit integer with a value of 1
343 for instruction cache and 2 for data or
344 unified cache. All other values are
346 @param ProcNumber Unsigned 64-bit integer that specifies for
347 which logical processor information is
348 being requested. This input argument must
349 be zero for the first call to this
350 procedure and can be a maximum value of
351 one less than the number of logical
352 processors sharing this cache, which is
353 returned by the num_shared return value.
355 @retval 0 Call completed without error
356 @retval -1 Unimplemented procedure
357 @retval -2 Invalid argument
358 @retval -3 Call completed with error.
360 @return R9 Unsigned integer that returns the number of
361 logical processors that share the processor
362 cache level and type, for which information was
364 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
365 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
368 #define PAL_CACHE_SHARED_INFO 43
372 PAL Procedure - PAL_CACHE_SUMMARY.
374 Return a summary of the cache hierarchy. It is required by
375 IPF. The PAL procedure supports the Static Registers calling
376 convention. It could be called at physical mode and Virtual
379 @param Index Index of PAL_CACHE_SUMMARY within the list of
382 @retval 0 Call completed without error
383 @retval -2 Invalid argument
384 @retval -3 Call completed with error.
386 @return R9 CacheLevels Unsigned 64-bit integer denoting the
387 number of levels of cache
388 implemented by the processor.
389 Strictly, this is the number of
390 levels for which the cache
391 controller is integrated into the
392 processor (the cache SRAMs may be
393 external to the processor).
394 @return R10 UniqueCaches Unsigned 64-bit integer denoting the
395 number of unique caches implemented
396 by the processor. This has a maximum
397 of 2*cache_levels, but may be less
398 if any of the levels in the cache
399 hierarchy are unified caches or do
400 not have both instruction and data
404 #define PAL_CACHE_SUMMARY 4
408 // Virtual Memory Attributes implemented by processor.
410 #define PAL_MEMORY_ATTR_WB 0
411 #define PAL_MEMORY_ATTR_WC 6
412 #define PAL_MEMORY_ATTR_UC 4
413 #define PAL_MEMORY_ATTR_UCE 5
414 #define PAL_MEMORY_ATTR_NATPAGE 7
417 PAL Procedure - PAL_MEM_ATTRIB.
419 Return a list of supported memory attributes.. It is required
420 by IPF. The PAL procedure supports the Static Registers calling
421 convention. It could be called at physical mode and Virtual
424 @param Index Index of PAL_MEM_ATTRIB within the list of PAL
427 @retval 0 Call completed without error
428 @retval -2 Invalid argument
429 @retval -3 Call completed with error.
431 @return R9 Attributes 8-bit vector of memory attributes
432 implemented by processor. See Virtual
433 Memory Attributes above.
437 #define PAL_MEM_ATTRIB 5
440 PAL Procedure - PAL_PREFETCH_VISIBILITY.
442 Used in architected sequence to transition pages from a
443 cacheable, speculative attribute to an uncacheable attribute.
444 It is required by IPF. The PAL procedure supports the Static
445 Registers calling convention. It could be called at physical
446 mode and Virtual mode.
448 @param Index Index of PAL_PREFETCH_VISIBILITY within the list
450 @param TransitionType Unsigned integer specifying the type
451 of memory attribute transition that is
454 @retval 1 Call completed without error; this
455 call is not necessary on remote
457 @retval 0 Call completed without error
458 @retval -2 Invalid argument
459 @retval -3 Call completed with error.
462 #define PAL_PREFETCH_VISIBILITY 41
465 PAL Procedure - PAL_PTCE_INFO.
467 Return information needed for ptc.e instruction to purge
468 entire TC. It is required by IPF. The PAL procedure supports
469 the Static Registers calling convention. It could be called at
470 physical mode and Virtual mode.
472 @param Index Index of PAL_PTCE_INFO within the list
475 @retval 0 Call completed without error
476 @retval -2 Invalid argument
477 @retval -3 Call completed with error.
479 @return R9 Unsigned 64-bit integer denoting the beginning
480 address to be used by the first PTCE instruction
482 @return R10 Two unsigned 32-bit integers denoting the loop
483 counts of the outer (loop 1) and inner (loop 2)
484 purge loops. count1 (loop 1) is contained in bits
485 63:32 of the parameter, and count2 (loop 2) is
486 contained in bits 31:0 of the parameter.
487 @return R11 Two unsigned 32-bit integers denoting the loop
488 strides of the outer (loop 1) and inner (loop 2)
489 purge loops. stride1 (loop 1) is contained in bits
490 63:32 of the parameter, and stride2 (loop 2) is
491 contained in bits 31:0 of the parameter.
494 #define PAL_PTCE_INFO 6
500 @param NumberSets Unsigned 8-bit integer denoting the number
501 of hash sets for the specified level
502 (1=fully associative)
504 @param NumberWays Unsigned 8-bit integer denoting the
505 associativity of the specified level
508 @param NumberEntries Unsigned 16-bit integer denoting the
509 number of entries in the specified TC.
512 @param PageSizeIsOptimized Flag denoting whether the
513 specified level is optimized for
514 the region's preferred page size
515 (1=optimized) tc_pages indicates
516 which page sizes are usable by
517 this translation cache.
519 @param TcIsUnified Flag denoting whether the specified TC is
522 @param EntriesReduction Flag denoting whether installed
523 translation registers will reduce
524 the number of entries within the
531 UINT64 NumberEntries
:16;
532 UINT64 PageSizeIsOptimized
:1;
533 UINT64 TcIsUnified
:1;
534 UINT64 EntriesReduction
:1;
538 PAL Procedure - PAL_VM_INFO.
540 Return detailed information about virtual memory features
541 supported in the processor. It is required by IPF. The PAL
542 procedure supports the Static Registers calling convention. It
543 could be called at physical mode and Virtual mode.
545 @param Index Index of PAL_VM_INFO within the list
547 @param TcLevel Unsigned 64-bit integer specifying the level
548 in the TLB hierarchy for which information is
549 required. This value must be between 0 and one
550 less than the value returned in the
551 vm_info_1.num_tc_levels return value from
553 @param TcType Unsigned 64-bit integer with a value of 1 for
554 instruction translation cache and 2 for data
555 or unified translation cache. All other values
558 @retval 0 Call completed without error
559 @retval -2 Invalid argument
560 @retval -3 Call completed with error.
562 @return R9 8-byte formatted value returning information
563 about the specified TC. See PAL_TC_INFO above.
564 @return R10 64-bit vector containing a bit for each page
565 size supported in the specified TC, where bit
566 position n indicates a page size of 2**n.
569 #define PAL_VM_INFO 7
573 PAL Procedure - PAL_VM_PAGE_SIZE.
575 Return virtual memory TC and hardware walker page sizes
576 supported in the processor. It is required by IPF. The PAL
577 procedure supports the Static Registers calling convention. It
578 could be called at physical mode and Virtual mode.
580 @param Index Index of PAL_VM_PAGE_SIZE within the list
583 @retval 0 Call completed without error
584 @retval -2 Invalid argument
585 @retval -3 Call completed with error.
587 @return R9 64-bit vector containing a bit for each
588 architected page size that is supported for
589 TLB insertions and region registers.
590 @return R10 64-bit vector containing a bit for each
591 architected page size supported for TLB purge
595 #define PAL_VM_PAGE_SIZE 34
599 @param WalkerPresent 1-bit flag indicating whether a hardware
600 TLB walker is implemented (1 = walker
603 @param WidthOfPhysicalAddress Unsigned 7-bit integer
604 denoting the number of bits of
605 physical address implemented.
607 @param WidthOfKey Unsigned 8-bit integer denoting the number
608 of bits mplemented in the PKR.key field.
610 @param MaxPkrIndex Unsigned 8-bit integer denoting the
611 maximum PKR index (number of PKRs-1).
613 @param HashTagId Unsigned 8-bit integer which uniquely
614 identifies the processor hash and tag
617 @param MaxDtrIndex Unsigned 8 bit integer denoting the
618 maximum data translation register index
619 (number of dtr entries - 1).
621 @param MaxItrIndex Unsigned 8 bit integer denoting the
622 maximum instruction translation register
623 index (number of itr entries - 1).
625 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the
626 number of unique TCs implemented.
630 @param NumberOfTcLevels Unsigned 8-bit integer denoting the
635 UINT64 WalkerPresent
:1;
636 UINT64 WidthOfPhysicalAddress
: 7;
638 UINT64 MaxPkrIndex
:8;
640 UINT64 MaxDtrIndex
:8;
641 UINT64 MaxItrIndex
:8;
642 UINT64 NumberOfUniqueTc
:8;
643 UINT64 NumberOfTcLevels
:8;
648 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting
649 is the total number of virtual
652 @param WidthOfRid Unsigned 8-bit integer denoting the number
653 of bits implemented in the RR.rid field.
655 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the
656 maximum number of concurrent outstanding
657 TLB purges allowed by the processor. A
658 value of 0 indicates one outstanding
659 purge allowed. A value of 216-1
660 indicates no limit on outstanding
661 purges. All other values indicate the
662 actual number of concurrent outstanding
667 UINT64 WidthOfVirtualAddress
:8;
669 UINT64 MaxPurgedTlbs
:16;
674 PAL Procedure - PAL_VM_SUMMARY.
676 Return summary information about virtual memory features
677 supported in the processor. It is required by IPF. The PAL
678 procedure supports the Static Registers calling convention. It
679 could be called at physical mode and Virtual mode.
681 @param Index Index of PAL_VM_SUMMARY within the list
684 @retval 0 Call completed without error
685 @retval -2 Invalid argument
686 @retval -3 Call completed with error.
688 @return R9 8-byte formatted value returning global virtual
689 memory information. See PAL_VM_INFO1 above.
690 @return R10 8-byte formatted value returning global virtual
691 memory information. See PAL_VM_INFO2 above.
694 #define PAL_VM_SUMMARY 8
698 // Bit mask of TR_valid flag.
700 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
701 #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
702 #define PAL_TR_DIRTY_IS_VALID BIT2
703 #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
707 PAL Procedure - PAL_VM_TR_READ.
709 Read contents of a translation register. It is required by
710 IPF. The PAL procedure supports the Stacked Register calling
711 convention. It could be called at physical mode.
713 @param Index Index of PAL_VM_TR_READ within the list
715 @param RegNumber Unsigned 64-bit number denoting which TR to
717 @param TrType Unsigned 64-bit number denoting whether to
718 read an ITR (0) or DTR (1). All other values
720 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
721 which translation data is returned.
723 @retval 0 Call completed without error
724 @retval -2 Invalid argument
725 @retval -3 Call completed with error.
727 @return R9 Formatted bit vector denoting which fields are
728 valid. See TR_valid above.
731 #define PAL_VM_TR_READ 261
737 // Bit Mask of Processor Bus Fesatures .
742 When 0, bus data errors are detected and single bit errors are
743 corrected. When 1, no error detection or correction is done.
746 #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
751 When 0, bus address errors are signalled on the bus. When 1,
752 no bus errors are signalled on the bus. If Disable Bus Address
753 Error Checking is 1, this bit is ignored.
756 #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
763 When 0, bus errors are detected, single bit errors are
764 corrected., and a CMCI or MCA is generated internally to the
765 processor. When 1, no bus address errors are detected or
769 #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
774 When 0, bus protocol errors (BINIT#) are signaled by the
775 processor on the bus. When 1, bus protocol errors (BINIT#) are
776 not signaled on the bus. If Disable Bus Initialization Event
777 Checking is 1, this bit is ignored.
780 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
785 When 0, bus protocol errors (BINIT#) are detected and sampled
786 and an MCA is generated internally to the processor. When 1,
787 the processor will ignore bus protocol error conditions
791 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
797 When 0, BERR# is signalled if a bus error is detected. When 1,
798 bus errors are not signalled on the bus.
801 #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
808 When 0, BERR# is signalled when internal processor requestor
809 initiated bus errors are detected. When 1, internal requester
810 bus errors are not signalled on the bus.
813 #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
818 When 0, the processor takes an MCA if BERR# is asserted. When
819 1, the processor ignores the BERR# signal.
822 #define PAL_BUS_DISABLE_ERROR_CHECK BIT56
827 When 0, the processor asserts BINIT# if it detects a parity
828 error on the signals which identify the transactions to which
829 this is a response. When 1, the processor ignores parity on
833 #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
838 When 0, the in-order transaction queue is limited only by the
839 number of hardware entries. When 1, the processor's in-order
840 transactions queue is limited to one entry.
843 #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
847 Enable a bus cache line replacement transaction when a cache
848 line in the exclusive state is replaced from the highest level
849 processor cache and is not present in the lower level processor
850 caches. When 0, no bus cache line replacement transaction will
851 be seen on the bus. When 1, bus cache line replacement
852 transactions will be seen on the bus when the above condition is
856 #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
861 Enable a bus cache line replacement transaction when a cache
862 line in the shared or exclusive state is replaced from the
863 highest level processor cache and is not present in the lower
864 level processor caches.
865 When 0, no bus cache line replacement transaction will be seen
866 on the bus. When 1, bus cache line replacement transactions
867 will be seen on the bus when the above condition is detected.
870 #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
876 When 0, the data bus is configured at the 2x data transfer
877 rate.When 1, the data bus is configured at the 1x data
878 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
879 processor executes locked transactions atomically. When 1, the
880 processor masks the bus lock signal and executes locked
881 transactions as a non-atomic series of transactions.
884 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
888 When 0, the processor will deassert bus request when finished
889 with each transaction. When 1, the processor will continue to
890 assert bus request after it has finished, if it was the last
891 agent to own the bus and if there are no other pending
895 #define PAL_BUS_REQUEST_BUS_PARKING BIT29
899 PAL Procedure - PAL_BUS_GET_FEATURES.
901 Return configurable processor bus interface features and their
902 current settings. It is required by IPF. The PAL procedure
903 supports the Stacked Register calling convention. It could be
904 called at physical mode.
906 @param Index Index of PAL_BUS_GET_FEATURES within the list
909 @retval 0 Call completed without error
910 @retval -2 Invalid argument
911 @retval -3 Call completed with error.
913 @return R9 64-bit vector of features implemented.
914 (1=implemented, 0=not implemented)
915 @return R10 64-bit vector of current feature settings.
916 @return R11 64-bit vector of features controllable by
917 software. (1=controllable, 0= not controllable)
920 #define PAL_BUS_GET_FEATURES 9
923 PAL Procedure - PAL_BUS_SET_FEATURES.
925 Enable or disable configurable features in processor bus
926 interface. It is required by IPF. It is required by IPF. The PAL procedure
927 supports the Static Registers calling convention. It could be
928 called at physical mode.
930 @param Index Index of PAL_BUS_SET_FEATURES within the list
932 @param FeatureSelect 64-bit vector denoting desired state of
933 each feature (1=select, 0=non-select).
935 @retval 0 Call completed without error
936 @retval -2 Invalid argument
937 @retval -3 Call completed with error.
940 #define PAL_BUS_SET_FEATURES 10
944 PAL Procedure - PAL_DEBUG_INFO.
946 Return the number of instruction and data breakpoint
947 registers. It is required by IPF. It is required by IPF. The
948 PAL procedure supports the Static Registers calling
949 convention. It could be called at physical mode and virtual
952 @param Index Index of PAL_DEBUG_INFO within the list of PAL
955 @retval 0 Call completed without error
956 @retval -2 Invalid argument
957 @retval -3 Call completed with error.
959 @return R9 Unsigned 64-bit integer denoting the number of
960 pairs of instruction debug registers implemented
962 @return R10 Unsigned 64-bit integer denoting the number of
963 pairs of data debug registers implemented by the
967 #define PAL_DEBUG_INFO 11
970 PAL Procedure - PAL_FIXED_ADDR.
972 Return the fixed component of a processor's directed address.
973 It is required by IPF. It is required by IPF. The PAL
974 procedure supports the Static Registers calling convention. It
975 could be called at physical mode and virtual mode.
977 @param Index Index of PAL_FIXED_ADDR within the list of PAL
980 @retval 0 Call completed without error
981 @retval -2 Invalid argument
982 @retval -3 Call completed with error.
984 @return R9 Fixed geographical address of this processor.
987 #define PAL_FIXED_ADDR 12
990 PAL Procedure - PAL_FREQ_BASE.
992 Return the frequency of the output clock for use by the
993 platform, if generated by the processor. It is optinal. The
994 PAL procedure supports the Static Registers calling
995 convention. It could be called at physical mode and virtual
998 @param Index Index of PAL_FREQ_BASE within the list of PAL
1001 @retval 0 Call completed without error
1002 @retval -1 Unimplemented procedure
1003 @retval -2 Invalid argument
1004 @retval -3 Call completed with error.
1006 @return R9 Base frequency of the platform if generated by the
1010 #define PAL_FREQ_BASE 13
1014 PAL Procedure - PAL_FREQ_RATIOS.
1016 Return ratio of processor, bus, and interval time counter to
1017 processor input clock or output clock for platform use, if
1018 generated by the processor. It is required by IPF. The PAL
1019 procedure supports the Static Registers calling convention. It
1020 could be called at physical mode and virtual mode.
1022 @param Index Index of PAL_FREQ_RATIOS within the list of PAL
1025 @retval 0 Call completed without error
1026 @retval -2 Invalid argument
1027 @retval -3 Call completed with error.
1029 @return R9 Ratio of the processor frequency to the input
1030 clock of the processor, if the platform clock is
1031 generated externally or to the output clock to the
1032 platform, if the platform clock is generated by
1034 @return R10 Ratio of the bus frequency to the input clock of
1035 the processor, if the platform clock is generated
1036 externally or to the output clock to the platform,
1037 if the platform clock is generated by the
1039 @return R11 Ratio of the interval timer counter rate to input
1040 clock of the processor, if the platform clock is
1041 generated externally or to the output clock to the
1042 platform, if the platform clock is generated by
1046 #define PAL_FREQ_RATIOS 14
1050 @param NumberOfLogicalProcessors Total number of logical
1051 processors on this physical
1052 processor package that are
1055 @param ThreadsPerCore Number of threads per core.
1057 @param CoresPerProcessor Total number of cores on this
1058 physical processor package.
1060 @param PhysicalProcessorPackageId Physical processor package
1061 identifier which was
1062 assigned at reset by the
1064 controller. This value may
1065 or may not be unique
1066 across the entire platform
1067 since it depends on the
1068 platform vendor's policy.
1071 UINT64 NumberOfLogicalProcessors
:16;
1072 UINT64 ThreadsPerCore
:8;
1074 UINT64 CoresPerProcessor
;
1076 UINT64 PhysicalProcessorPackageId
:8;
1078 } PAL_LOGICAL_PROCESSPR_OVERVIEW
;
1082 @param ThreadId The thread identifier of the logical
1083 processor for which information is being
1084 returned. This value will be unique on a per
1087 @param CoreId The core identifier of the logical processor
1088 for which information is being returned.
1089 This value will be unique on a per physical
1090 processor package basis.
1095 UINT64 Reserved1
:16;
1097 UINT64 Reserved2
:16;
1098 } PAL_LOGICAL_PROCESSORN_INFO1
;
1103 @param LogicalAddress Geographical address of the logical
1104 processor for which information is being
1105 returned. This is the same value that is
1106 returned by the PAL_FIXED_ADDR procedure
1107 when it is called on the logical
1113 UINT64 LogicalAddress
:16;
1115 } PAL_LOGICAL_PROCESSORN_INFO2
;
1118 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
1120 Return information on which logical processors map to a
1121 physical processor die. It is optinal. The PAL procedure
1122 supports the Static Registers calling convention. It could be
1123 called at physical mode and virtual mode.
1125 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
1127 @param ProcessorNumber Signed 64-bit integer that specifies
1128 for which logical processor
1129 information is being requested. When
1130 this input argument is -1, information
1131 is returned about the logical
1132 processor on which the procedure call
1133 is made. This input argument must be
1134 in the range of 1 up to one less than
1135 the number of logical processors
1136 returned by num_log in the
1137 log_overview return value.
1139 @retval 0 Call completed without error
1140 @retval -1 Unimplemented procedure
1141 @retval -2 Invalid argument
1142 @retval -3 Call completed with error.
1144 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
1145 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
1146 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
1149 #define PAL_LOGICAL_TO_PHYSICAL 42
1154 @param NumberOfPmcPairs Unsigned 8-bit number defining the
1155 number of generic PMC/PMD pairs.
1157 @param WidthOfCounter Unsigned 8-bit number in the range
1158 0:60 defining the number of
1159 implemented counter bits.
1161 @param TypeOfCycleCounting Unsigned 8-bit number defining the
1162 event type for counting processor
1166 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
1168 event type for retired
1169 instruction bundles.
1173 UINT64 NumberOfPmcPairs
:8;
1174 UINT64 WidthOfCounter
:8;
1175 UINT64 TypeOfCycleCounting
:8;
1176 UINT64 TypeOfRetiredInstructionBundle
:8;
1178 } PAL_PERFORMANCE_INFO
;
1181 PAL Procedure - PAL_PERF_MON_INFO.
1183 Return the number and type of performance monitors. It is
1184 required by IPF. The PAL procedure supports the Static
1185 Registers calling convention. It could be called at physical
1186 mode and virtual mode.
1188 @param Index Index of PAL_PERF_MON_INFO within the list of
1190 @param PerformanceBuffer An address to an 8-byte aligned
1191 128-byte memory buffer.
1193 @retval 0 Call completed without error
1194 @retval -2 Invalid argument
1195 @retval -3 Call completed with error.
1197 @return R9 Information about the performance monitors
1198 implemented. See PAL_PERFORMANCE_INFO;
1201 #define PAL_PERF_MON_INFO 15
1203 #define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0
1204 #define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1
1207 PAL Procedure - PAL_PLATFORM_ADDR.
1209 Specify processor interrupt block address and I/O port space
1210 address. It is required by IPF. The PAL procedure supports the
1211 Static Registers calling convention. It could be called at
1212 physical mode and virtual mode.
1214 @param Index Index of PAL_PLATFORM_ADDR within the list of
1216 @param Type Unsigned 64-bit integer specifying the type of
1217 block. 0 indicates that the processor interrupt
1218 block pointer should be initialized. 1 indicates
1219 that the processor I/O block pointer should be
1221 @param Address Unsigned 64-bit integer specifying the address
1222 to which the processor I/O block or interrupt
1223 block shall be set. The address must specify
1224 an implemented physical address on the
1225 processor model, bit 63 is ignored.
1227 @retval 0 Call completed without error
1228 @retval -1 Unimplemented procedure.
1229 @retval -2 Invalid argument
1230 @retval -3 Call completed with error.
1233 #define PAL_PLATFORM_ADDR 16
1238 @param EnableBerrPromotion Bit63. Enable BERR promotion. When
1239 1, the Bus Error (BERR) signal is
1240 promoted to the Bus Initialization
1241 (BINIT) signal, and the BINIT pin
1242 is asserted on the occurrence of
1243 each Bus Error. Setting this bit
1244 has no effect if BINIT signalling
1246 PAL_BUS_GET/SET_FEATURES)
1248 @param EnableMcaPromotion Bit62, Enable MCA promotion. When
1249 1, machine check aborts (MCAs) are
1250 promoted to the Bus Error signal,
1251 and the BERR pin is assert on each
1252 occurrence of an MCA. Setting this
1253 bit has no effect if BERR
1254 signalling is disabled. (See
1255 PAL_BUS_GET/SET_FEATURES)
1257 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
1258 promotion. When 1, machine
1259 check aborts (MCAs) are
1261 Initialization signal, and
1262 the BINIT pin is assert on
1263 each occurrence of an MCA.
1264 Setting this bit has no
1265 effect if BINIT signalling
1267 PAL_BUS_GET/SET_FEATURES)
1269 @param EnableCmciPromotion Bit60, Enable CMCI promotion When
1270 1, Corrected Machine Check
1271 Interrupts (CMCI) are promoted to
1272 MCAs. They are also further
1273 promoted to BERR if bit 39, Enable
1274 MCA promotion, is also set and
1275 they are promoted to BINIT if bit
1276 38, Enable MCA to BINIT promotion,
1277 is also set. This bit has no
1278 effect if MCA signalling is
1280 PAL_BUS_GET/SET_FEATURES)
1282 @param DisableCache Bit59, Disable Cache. When 0, the
1283 processor performs cast outs on
1284 cacheable pages and issues and responds
1285 to coherency requests normally. When 1,
1286 the processor performs a memory access
1287 for each reference regardless of cache
1288 contents and issues no coherence
1289 requests and responds as if the line
1290 were not present. Cache contents cannot
1291 be relied upon when the cache is
1292 disabled. WARNING: Semaphore
1293 instructions may not be atomic or may
1294 cause Unsupported Data Reference faults
1295 if caches are disabled.
1297 @param DisableCoherency Bit58, Disable Coherency. When 0,
1298 the processor uses normal coherency
1299 requests and responses. When 1, the
1300 processor answers all requests as if
1301 the line were not present.
1303 @param DisableDPM Bit57, Disable Dynamic Power Management
1304 (DPM). When 0, the hardware may reduce
1305 power consumption by removing the clock
1306 input from idle functional units. When 1,
1307 all functional units will receive clock
1308 input, even when idle.
1310 @param DisableBinitWithTimeout Bit56, Disable a BINIT on
1311 internal processor time-out.
1312 When 0, the processor may
1313 generate a BINIT on an
1314 internal processor time-out.
1315 When 1, the processor will not
1316 generate a BINIT on an
1317 internal processor time-out.
1318 The event is silently ignored.
1321 @param EnableEnvNotification Bit55, Enable external
1322 notification when the processor
1323 detects hardware errors caused
1324 by environmental factors that
1326 deterministic behavior of the
1327 processor. When 1, this bit will
1328 enable external notification,
1329 when 0 external notification is
1330 not provided. The type of
1331 external notification of these
1332 errors is processor-dependent. A
1333 loss of processor deterministic
1334 behavior is considered to have
1336 environmentally induced errors
1337 cause the processor to deviate
1338 from its normal execution and
1339 eventually causes different
1340 behavior which can be observed
1341 at the processor bus pins.
1342 Processor errors that do not
1343 have this effects (i.e.,
1344 software induced machine checks)
1345 may or may not be promoted
1346 depending on the processor
1349 @param EnableVmsw Bit54, Enable the use of the vmsw
1350 instruction. When 0, the vmsw instruction
1351 causes a Virtualization fault when
1352 executed at the most privileged level.
1353 When 1, this bit will enable normal
1354 operation of the vmsw instruction.
1356 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
1357 on data-poisoning event
1358 detection. When 0, a CMCI
1359 will be signaled on error
1360 detection. When 1, an MCA
1361 will be signaled on error
1362 detection. If this feature
1363 is not supported, then the
1364 corresponding argument is
1365 ignored when calling
1366 PAL_PROC_SET_FEATURES. Note
1367 that the functionality of
1368 this bit is independent of
1369 the setting in bit 60
1370 (Enable CMCI promotion), and
1371 that the bit 60 setting does
1372 not affect CMCI signaling
1373 for data-poisoning related
1374 events. Volume 2: Processor
1375 Abstraction Layer 2:431
1376 PAL_PROC_GET_FEATURES
1378 @param DisablePState Bit52, Disable P-states. When 1, the PAL
1379 P-state procedures (PAL_PSTATE_INFO,
1380 PAL_SET_PSTATE, PAL_GET_PSTATE) will
1381 return with a status of -1
1382 (Unimplemented procedure).
1384 @param DisableBranchPrediction Bit47, Disable Dynamic branch
1385 prediction. When 0, the
1386 processor may predict branch
1387 targets and speculatively
1388 execute, but may not commit
1389 results. When 1, the processor
1390 must wait until branch targets
1391 are known to execute.
1393 @param DisableDynamicInsCachePrefetch Bit46, Disable
1394 DynamicInstruction Cache
1395 Prefetch. When 0, the
1396 processor may prefetch
1398 instruction which has
1399 not been executed, but
1402 instructions may not be
1403 fetched until needed or
1404 hinted for execution.
1405 (Prefetch for a hinted
1406 branch is allowed even
1407 when dynamic instruction
1411 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
1412 Data Cache Prefetch.
1413 When 0, the processor
1414 may prefetch into the
1415 caches any data which
1416 has not been accessed
1418 execution, but which
1420 accessed. When 1, no
1422 until it is needed for
1423 instruction execution
1427 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous
1428 Deferral. When 1, the
1429 processor may optionally
1430 defer speculative loads
1431 that do not encounter any
1432 exception conditions, but
1434 implementation-dependent
1435 conditions (e.g., cache
1436 miss). When 0, spontaneous
1437 deferral is disabled.
1439 @param DisableDynamicPrediction Bit43, Disable Dynamic
1440 Predicate Prediction. When
1441 0, the processor may predict
1442 predicate results and
1443 execute speculatively, but
1444 may not commit results until
1445 the actual predicates are
1446 known. When 1, the processor
1447 shall not execute predicated
1448 instructions until the
1449 actual predicates are known.
1451 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
1452 Denotes whether XR1 XR3 are
1453 implemented for machine check
1454 recovery. This feature may only be
1455 interrogated by PAL_PROC_GET_FEATURES.
1456 It may not be enabled or disabled by
1457 PAL_PROC_SET_FEATURES. The
1458 corresponding argument is ignored.
1460 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
1461 implemented. Denotes whether XIP, XPSR,
1462 and XFS are implemented for machine
1463 check recovery. This feature may only be
1464 interrogated by PAL_PROC_GET_FEATURES.
1465 It may not be enabled or disabled by
1466 PAL_PROC_SET_FEATURES. The corresponding
1467 argument is ignored.
1469 @param NoVM Bit40, No Virtual Machine features implemented.
1470 Denotes whether PSR.vm is implemented. This
1471 feature may only be interrogated by
1472 PAL_PROC_GET_FEATURES. It may not be enabled or
1473 disabled by PAL_PROC_SET_FEATURES. The
1474 corresponding argument is ignored.
1476 @param NoVariablePState Bit39, No Variable P-state
1477 performance: A value of 1, indicates
1478 that a processor implements
1479 techniques to optimize performance
1480 for the given P-state power budget
1481 by dynamically varying the
1482 frequency, such that maximum
1483 performance is achieved for the
1484 power budget. A value of 0,
1485 indicates that P-states have no
1486 frequency variation or very small
1487 frequency variations for their given
1488 power budget. This feature may only
1490 PAL_PROC_GET_FEATURES. it may not be
1491 enabled or disabled by
1492 PAL_PROC_SET_FEATURES. The
1493 corresponding argument is ignored.
1496 @param NoSimpleImpInUndefinedIns Bit38, No Simple
1498 unimplemented instruction
1499 addresses. Denotes how an
1500 unimplemented instruction
1501 address is recorded in IIP
1503 Instruction Address trap or
1504 fault. When 1, the full
1505 unimplemented address is
1506 recorded in IIP; when 0, the
1507 address is sign extended
1508 (virtual addresses) or zero
1510 addresses). This feature may
1511 only be interrogated by
1512 PAL_PROC_GET_FEATURES. It
1513 may not be enabled or
1515 PAL_PROC_SET_FEATURES. The
1516 corresponding argument is
1519 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
1520 present. Denotes the absence of INIT,
1521 PMI, LINT0 and LINT1 pins on the
1522 processor. When 1, the pins are absent.
1523 When 0, the pins are present. This
1524 feature may only be interrogated by
1525 PAL_PROC_GET_FEATURES. It may not be
1526 enabled or disabled by
1527 PAL_PROC_SET_FEATURES. The corresponding
1528 argument is ignored.
1530 @param FaultInUndefinedIns Bit36, No Unimplemented
1531 instruction address reported as
1532 fault. Denotes how the processor
1533 reports the detection of
1534 unimplemented instruction
1535 addresses. When 1, the processor
1536 reports an Unimplemented
1537 Instruction Address fault on the
1538 unimplemented address; when 0, it
1539 reports an Unimplemented
1540 Instruction Address trap on the
1541 previous instruction in program
1542 order. This feature may only be
1544 PAL_PROC_GET_FEATURES. It may not
1545 be enabled or disabled by
1546 PAL_PROC_SET_FEATURES. The
1547 corresponding argument is
1552 UINT64 Reserved1
:36;
1553 UINT64 FaultInUndefinedIns
:1;
1554 UINT64 NoPresentPmi
:1;
1555 UINT64 NoSimpleImpInUndefinedIns
:1;
1556 UINT64 NoVariablePState
:1;
1558 UINT64 NoXipXpsrXfs
:1;
1559 UINT64 NoXr1ThroughXr3
:1;
1560 UINT64 DisableDynamicPrediction
:1;
1561 UINT64 DisableSpontaneousDeferral
:1;
1562 UINT64 DisableDynamicDataCachePrefetch
:1;
1563 UINT64 DisableDynamicInsCachePrefetch
:1;
1564 UINT64 DisableBranchPrediction
:1;
1566 UINT64 DisablePState
:1;
1567 UINT64 EnableMcaOnDataPoisoning
:1;
1568 UINT64 EnableVmsw
:1;
1569 UINT64 EnableEnvNotification
:1;
1570 UINT64 DisableBinitWithTimeout
:1;
1571 UINT64 DisableDPM
:1;
1572 UINT64 DisableCoherency
:1;
1573 UINT64 DisableCache
:1;
1574 UINT64 EnableCmciPromotion
:1;
1575 UINT64 EnableMcaToBinitPromotion
:1;
1576 UINT64 EnableMcaPromotion
:1;
1577 UINT64 EnableBerrPromotion
:1;
1578 } PAL_PROCESSOR_FEATURES
;
1581 PAL Procedure - PAL_PROC_GET_FEATURES.
1583 Return configurable processor features and their current
1584 setting. It is required by IPF. The PAL procedure supports the
1585 Static Registers calling convention. It could be called at
1586 physical mode and virtual mode.
1588 @param Index Index of PAL_PROC_GET_FEATURES within the list of
1590 @param Reserved Reserved parameter.
1591 @param FeatureSet Feature set information is being requested
1594 @retval 1 Call completed without error; The
1595 feature_set passed is not supported but a
1596 feature_set of a larger value is supported.
1597 @retval 0 Call completed without error
1598 @retval -2 Invalid argument
1599 @retval -3 Call completed with error.
1600 @retval -8 feature_set passed is beyond the maximum
1601 feature_set supported
1603 @return R9 64-bit vector of features implemented. See
1604 PAL_PROCESSOR_FEATURES.
1605 @return R10 64-bit vector of current feature settings. See
1606 PAL_PROCESSOR_FEATURES.
1607 @return R11 64-bit vector of features controllable by
1611 #define PAL_PROC_GET_FEATURES 17
1615 PAL Procedure - PAL_PROC_SET_FEATURES.
1617 Enable or disable configurable processor features. It is
1618 required by IPF. The PAL procedure supports the Static
1619 Registers calling convention. It could be called at physical
1622 @param Index Index of PAL_PROC_SET_FEATURES within the list of
1624 @param FeatureSelect 64-bit vector denoting desired state of
1625 each feature (1=select, 0=non-select).
1626 @param FeatureSet Feature set to apply changes to. See
1627 PAL_PROC_GET_FEATURES for more information
1630 @retval 1 Call completed without error; The
1631 feature_set passed is not supported but a
1632 feature_set of a larger value is supported
1633 @retval 0 Call completed without error
1634 @retval -2 Invalid argument
1635 @retval -3 Call completed with error.
1636 @retval -8 feature_set passed is beyond the maximum
1637 feature_set supported
1640 #define PAL_PROC_SET_FEATURES 18
1644 // Value of PAL_REGISTER_INFO.InfoRequest.
1646 #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
1647 #define PAL_APPLICATION_REGISTER_READABLE 1
1648 #define PAL_CONTROL_REGISTER_IMPLEMENTED 2
1649 #define PAL_CONTROL_REGISTER_READABLE 3
1653 PAL Procedure - PAL_REGISTER_INFO.
1655 Return AR and CR register information. It is required by IPF.
1656 The PAL procedure supports the Static Registers calling
1657 convention. It could be called at physical mode and virtual
1660 @param Index Index of PAL_REGISTER_INFO within the list of
1662 @param InfoRequest Unsigned 64-bit integer denoting what
1663 register information is requested. See
1664 PAL_REGISTER_INFO.InfoRequest above.
1666 @retval 0 Call completed without error
1667 @retval -2 Invalid argument
1668 @retval -3 Call completed with error.
1670 @return R9 64-bit vector denoting information for registers
1671 0-63. Bit 0 is register 0, bit 63 is register 63.
1672 @return R10 64-bit vector denoting information for registers
1673 64-127. Bit 0 is register 64, bit 63 is register
1677 #define PAL_REGISTER_INFO 39
1680 PAL Procedure - PAL_RSE_INFO.
1682 Return RSE information. It is required by IPF. The PAL
1683 procedure supports the Static Registers calling convention. It
1684 could be called at physical mode and virtual mode.
1686 @param Index Index of PAL_RSE_INFO within the list of
1688 @param InfoRequest Unsigned 64-bit integer denoting what
1689 register information is requested. See
1690 PAL_REGISTER_INFO.InfoRequest above.
1692 @retval 0 Call completed without error
1693 @retval -2 Invalid argument
1694 @retval -3 Call completed with error.
1696 @return R9 Number of physical stacked general registers.
1697 @return R10 RSE hints supported by processor.
1700 #define PAL_RSE_INFO 19
1704 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1705 number that provides identification
1706 information about the PAL_B firmware.
1708 @param PalVendor Is an unsigned 8-bit integer indicating the
1709 vendor of the PAL code.
1711 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1712 number that provides identification
1713 information about the PAL_A firmware. In
1714 the split PAL_A model, this return value
1715 is the version number of the
1716 processor-specific PAL_A. The generic
1717 PAL_A version is not returned by this
1718 procedure in the split PAL_A model.
1722 UINT64 VersionOfPalB
:16;
1725 UINT64 VersionOfPalA
:16;
1726 UINT64 Reserved2
:16;
1730 PAL Procedure - PAL_VERSION.
1732 Return version of PAL code. It is required by IPF. The PAL
1733 procedure supports the Static Registers calling convention. It
1734 could be called at physical mode and virtual mode.
1736 @param Index Index of PAL_VERSION within the list of
1738 @param InfoRequest Unsigned 64-bit integer denoting what
1739 register information is requested. See
1740 PAL_REGISTER_INFO.InfoRequest above.
1742 @retval 0 Call completed without error
1743 @retval -2 Invalid argument
1744 @retval -3 Call completed with error.
1746 @return R9 8-byte formatted value returning the minimum PAL
1747 version needed for proper operation of the
1748 processor. See PAL_VERSION_INFO above.
1749 @return R10 8-byte formatted value returning the current PAL
1750 version running on the processor. See
1751 PAL_VERSION_INFO above.
1754 #define PAL_VERSION 20
1759 // Vectors of PAL_MC_CLEAR_LOG.pending
1761 #define PAL_MC_PENDING BIT0
1762 #define PAL_INIT_PENDING BIT1
1765 PAL Procedure - PAL_MC_CLEAR_LOG.
1767 Clear all error information from processor error logging
1768 registers. It is required by IPF. The PAL procedure supports
1769 the Static Registers calling convention. It could be called at
1770 physical mode and virtual mode.
1772 @param Index Index of PAL_MC_CLEAR_LOG within the list of
1775 @retval 0 Call completed without error
1776 @retval -2 Invalid argument
1777 @retval -3 Call completed with error.
1779 @return R9 64-bit vector denoting whether an event is
1780 pending. See PAL_MC_CLEAR_LOG.pending above.
1783 #define PAL_MC_CLEAR_LOG 21
1786 PAL Procedure - PAL_MC_DRAIN.
1788 Ensure that all operations that could cause an MCA have
1789 completed. It is required by IPF. The PAL procedure supports
1790 the Static Registers calling convention. It could be called at
1791 physical mode and virtual mode.
1793 @param Index Index of PAL_MC_DRAIN within the list of PAL
1796 @retval 0 Call completed without error
1797 @retval -2 Invalid argument
1798 @retval -3 Call completed with error.
1801 #define PAL_MC_DRAIN 22
1805 PAL Procedure - PAL_MC_DYNAMIC_STATE.
1807 Return Processor Dynamic State for logging by SAL. It is
1808 optional. The PAL procedure supports the Static Registers
1809 calling convention. It could be called at physical mode.
1811 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
1813 @param Offset Offset of the next 8 bytes of Dynamic Processor
1814 State to return. (multiple of 8).
1816 @retval 0 Call completed without error
1817 @retval -1 Unimplemented procedure.
1818 @retval -2 Invalid argument
1819 @retval -3 Call completed with error.
1821 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
1822 Processor State returned.
1823 @return R10 Next 8 bytes of Dynamic Processor State.
1826 #define PAL_MC_DYNAMIC_STATE 24
1831 // Values of PAL_MC_ERROR_INFO.InfoIndex.
1833 #define PAL_PROCESSOR_ERROR_MAP 0
1834 #define PAL_PROCESSOR_STATE_PARAM 1
1835 #define PAL_STRUCTURE_SPECIFIC_ERROR 2
1839 @param CoreId Bit3:0, Processor core ID (default is 0 for
1840 processors with a single core)
1842 @param ThreadId Bit7:4, Logical thread ID (default is 0 for
1843 processors that execute a single thread)
1845 @param InfoOfInsCache Bit11:8, Error information is
1846 available for 1st, 2nd, 3rd, and 4th
1847 level instruction caches.
1849 @param InfoOfDataCache Bit15:12, Error information is
1850 available for 1st, 2nd, 3rd, and 4th
1851 level data/unified caches.
1853 @param InfoOfInsTlb Bit19:16 Error information is available
1854 for 1st, 2nd, 3rd, and 4th level
1857 @param InfoOfDataTlb Bit23:20, Error information is available
1858 for 1st, 2nd, 3rd, and 4th level
1861 @param InfoOfProcessorBus Bit27:24 Error information is
1862 available for the 1st, 2nd, 3rd,
1863 and 4th level processor bus
1866 @param InfoOfRegisterFile Bit31:28 Error information is
1867 available on register file
1870 @param InfoOfMicroArch Bit47:32, Error information is
1871 available on micro-architectural
1878 UINT64 InfoOfInsCache
:4;
1879 UINT64 InfoOfDataCache
:4;
1880 UINT64 InfoOfInsTlb
:4;
1881 UINT64 InfoOfDataTlb
:4;
1882 UINT64 InfoOfProcessorBus
:4;
1883 UINT64 InfoOfRegisterFile
:4;
1884 UINT64 InfoOfMicroArch
:4;
1886 } PAL_MC_ERROR_INFO_LEVEL_INDEX
;
1889 // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
1891 #define PAL_ERR_INFO_BY_LEVEL_INDEX 0
1892 #define PAL_ERR_INFO_TARGET_ADDRESS 1
1893 #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
1894 #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
1895 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
1899 @param Operation Bit3:0, Type of cache operation that caused
1900 the machine check: 0 - unknown or internal
1901 error 1 - load 2 - store 3 - instruction
1902 fetch or instruction prefetch 4 - data
1903 prefetch (both hardware and software) 5 -
1904 snoop (coherency check) 6 - cast out
1905 (explicit or implicit write-back of a cache
1906 line) 7 - move in (cache line fill)
1908 @param FailedCacheLevel Bit5:4 Level of cache where the
1909 error occurred. A value of 0
1910 indicates the first level of cache.
1912 @param FailedInDataPart Bit8, Failure located in the data
1913 part of the cache line.
1915 @param FailedInTagPart Bit9, Failure located in the tag part
1918 @param FailedInDataCache Bit10, Failure located in the data
1921 @param FailedInInsCache Bit11, Failure located in the
1925 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
1926 line is held shared. 2 - cache line is held
1927 exclusive. 3 - cache line is modified. All other
1928 values are reserved.
1930 @param MesiIsValid Bit15, The mesi field in the cache_check
1933 @param FailedWay Bit20:16, Failure located in the way of
1934 the cache indicated by this value.
1936 @param WayIndexIsValid Bit21, The way and index field in the
1937 cache_check parameter is valid.
1939 @param MultipleBitsError Bit23, A multiple-bit error was
1940 detected, and data was poisoned for
1941 the corresponding cache line during
1944 @param IndexOfCacheLineError Bit51:32, Index of the cache
1945 line where the error occurred.
1947 @param InstructionSet Bit54, Instruction set. If this value
1948 is set to zero, the instruction that
1949 generated the machine check was an
1950 Intel Itanium instruction. If this bit
1951 is set to one, the instruction that
1952 generated the machine check was IA-32
1955 @param InstructionSetIsValid Bit55, The is field in the
1956 cache_check parameter is valid.
1958 @param PrivilegeLevel Bit57:56, Privilege level. The
1959 privilege level of the instruction
1960 bundle responsible for generating the
1963 @param PrivilegeLevelIsValide Bit58, The pl field of the
1964 cache_check parameter is
1967 @param McCorrected Bit59, Machine check corrected: This bit
1968 is set to one to indicate that the machine
1969 check has been corrected.
1971 @param TargetAddressIsValid Bit60, Target address is valid:
1972 This bit is set to one to
1973 indicate that a valid target
1974 address has been logged.
1976 @param RequesterIdentifier Bit61, Requester identifier: This
1977 bit is set to one to indicate that
1978 a valid requester identifier has
1981 @param ResponserIdentifier Bit62, Responder identifier: This
1982 bit is set to one to indicate that
1983 a valid responder identifier has
1986 @param PreciseInsPointer Bit63, Precise instruction pointer.
1987 This bit is set to one to indicate
1988 that a valid precise instruction
1989 pointer has been logged.
1994 UINT64 FailedCacheLevel
:2;
1996 UINT64 FailedInDataPart
:1;
1997 UINT64 FailedInTagPart
:1;
1998 UINT64 FailedInDataCache
:1;
1999 UINT64 FailedInInsCache
:1;
2001 UINT64 MesiIsValid
:1;
2003 UINT64 WayIndexIsValid
:1;
2006 UINT64 MultipleBitsError
:1;
2008 UINT64 IndexOfCacheLineError
:20;
2010 UINT64 InstructionSet
:1;
2011 UINT64 InstructionSetIsValid
:1;
2013 UINT64 PrivilegeLevel
:2;
2014 UINT64 PrivilegeLevelIsValide
:1;
2016 UINT64 McCorrected
:1;
2018 UINT64 TargetAddressIsValid
:1;
2019 UINT64 RequesterIdentifier
:1;
2020 UINT64 ResponserIdentifier
:1;
2021 UINT64 PreciseInsPointer
:1;
2023 } PAL_CACHE_CHECK_INFO
;
2027 @param FailedSlot Bit7:0, Slot number of the translation
2028 register where the failure occurred.
2030 @param FailedSlotIsValid Bit8, The tr_slot field in the
2031 TLB_check parameter is valid.
2033 @param TlbLevel Bit11:10, The level of the TLB where the
2034 error occurred. A value of 0 indicates the
2037 @param FailedInDataTr Bit16, Error occurred in the data
2038 translation registers.
2040 @param FailedInInsTr Bit17, Error occurred in the instruction
2041 translation registers
2043 @param FailedInDataTc Bit18, Error occurred in data
2046 @param FailedInInsTc Bit19, Error occurred in the instruction
2049 @param FailedOperation Bit23:20, Type of cache operation that
2050 caused the machine check: 0 - unknown
2051 1 - TLB access due to load instruction
2052 2 - TLB access due to store
2053 instruction 3 - TLB access due to
2054 instruction fetch or instruction
2055 prefetch 4 - TLB access due to data
2056 prefetch (both hardware and software)
2057 5 - TLB shoot down access 6 - TLB
2058 probe instruction (probe, tpa) 7 -
2059 move in (VHPT fill) 8 - purge (insert
2060 operation that purges entries or a TLB
2061 purge instruction) All other values
2064 @param InstructionSet Bit54, Instruction set. If this value
2065 is set to zero, the instruction that
2066 generated the machine check was an
2067 Intel Itanium instruction. If this bit
2068 is set to one, the instruction that
2069 generated the machine check was IA-32
2072 @param InstructionSetIsValid Bit55, The is field in the
2073 TLB_check parameter is valid.
2075 @param PrivelegeLevel Bit57:56, Privilege level. The
2076 privilege level of the instruction
2077 bundle responsible for generating the
2080 @param PrivelegeLevelIsValid Bit58, The pl field of the
2081 TLB_check parameter is valid.
2083 @param McCorrected Bit59, Machine check corrected: This bit
2084 is set to one to indicate that the machine
2085 check has been corrected.
2087 @param TargetAddressIsValid Bit60, Target address is valid:
2088 This bit is set to one to
2089 indicate that a valid target
2090 address has been logged.
2092 @param RequesterIdentifier Bit61 Requester identifier: This
2093 bit is set to one to indicate that
2094 a valid requester identifier has
2097 @param ResponserIdentifier Bit62, Responder identifier: This
2098 bit is set to one to indicate that
2099 a valid responder identifier has
2102 @param PreciseInsPointer Bit63 Precise instruction pointer.
2103 This bit is set to one to indicate
2104 that a valid precise instruction
2105 pointer has been logged.
2108 UINT64 FailedSlot
:8;
2109 UINT64 FailedSlotIsValid
:1;
2110 UINT64 Reserved1
:1;
2112 UINT64 Reserved2
:4;
2113 UINT64 FailedInDataTr
:1;
2114 UINT64 FailedInInsTr
:1;
2115 UINT64 FailedInDataTc
:1;
2116 UINT64 FailedInInsTc
:1;
2117 UINT64 FailedOperation
:4;
2118 UINT64 Reserved3
:30;
2119 UINT64 InstructionSet
:1;
2120 UINT64 InstructionSetIsValid
:1;
2121 UINT64 PrivelegeLevel
:2;
2122 UINT64 PrivelegeLevelIsValid
:1;
2123 UINT64 McCorrected
:1;
2124 UINT64 TargetAddressIsValid
:1;
2125 UINT64 RequesterIdentifier
:1;
2126 UINT64 ResponserIdentifier
:1;
2127 UINT64 PreciseInsPointer
:1;
2128 } PAL_TLB_CHECK_INFO
;
2131 PAL Procedure - PAL_MC_ERROR_INFO.
2133 Return Processor Machine Check Information and Processor
2134 Static State for logging by SAL. It is required by IPF. The
2135 PAL procedure supports the Static Registers calling
2136 convention. It could be called at physical and virtual mode.
2138 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
2140 @param InfoIndex Unsigned 64-bit integer identifying the
2141 error information that is being requested.
2142 See PAL_MC_ERROR_INFO.InfoIndex.
2143 @param LevelIndex 8-byte formatted value identifying the
2144 structure to return error information
2145 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
2146 @param ErrorTypeIndex Unsigned 64-bit integer denoting the
2147 type of error information that is
2148 being requested for the structure
2149 identified in LevelIndex.
2151 @retval 0 Call completed without error
2152 @retval -2 Invalid argument
2153 @retval -3 Call completed with error.
2154 @retval -6 Argument was valid, but no error
2155 information was available
2157 @return R9 Error information returned. The format of this
2158 value is dependant on the input values passed.
2159 @return R10 If this value is zero, all the error information
2160 specified by err_type_index has been returned. If
2161 this value is one, more structure-specific error
2162 information is available and the caller needs to
2163 make this procedure call again with level_index
2164 unchanged and err_type_index, incremented.
2167 #define PAL_MC_ERROR_INFO 25
2170 PAL Procedure - PAL_MC_EXPECTED.
2172 Set/Reset Expected Machine Check Indicator. It is required by
2173 IPF. The PAL procedure supports the Static Registers calling
2174 convention. It could be called at physical mode.
2176 @param Index Index of PAL_MC_EXPECTED within the list of PAL
2178 @param Expected Unsigned integer with a value of 0 or 1 to
2179 set or reset the hardware resource
2180 PALE_CHECK examines for expected machine
2183 @retval 0 Call completed without error
2184 @retval -2 Invalid argument
2185 @retval -3 Call completed with error.
2187 @return R9 Unsigned integer denoting whether a machine check
2188 was previously expected.
2191 #define PAL_MC_EXPECTED 23
2194 PAL Procedure - PAL_MC_REGISTER_MEM.
2196 Register min-state save area with PAL for machine checks and
2197 inits. It is required by IPF. The PAL procedure supports the
2198 Static Registers calling convention. It could be called at
2201 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
2203 @param Address Physical address of the buffer to be
2204 registered with PAL.
2206 @retval 0 Call completed without error
2207 @retval -2 Invalid argument
2208 @retval -3 Call completed with error.
2211 #define PAL_MC_REGISTER_MEM 27
2214 PAL Procedure - PAL_MC_RESUME.
2216 Restore minimal architected state and return to interrupted
2217 process. It is required by IPF. The PAL procedure supports the
2218 Static Registers calling convention. It could be called at
2221 @param Index Index of PAL_MC_RESUME within the list of PAL
2223 @param SetCmci Unsigned 64 bit integer denoting whether to
2224 set the CMC interrupt. A value of 0 indicates
2225 not to set the interrupt, a value of 1
2226 indicated to set the interrupt, and all other
2227 values are reserved.
2228 @param SavePtr Physical address of min-state save area used
2229 to used to restore processor state.
2230 @param NewContext Unsigned 64-bit integer denoting whether
2231 the caller is returning to a new context.
2232 A value of 0 indicates the caller is
2233 returning to the interrupted context, a
2234 value of 1 indicates that the caller is
2235 returning to a new context.
2237 @retval -2 Invalid argument
2238 @retval -3 Call completed with error.
2241 #define PAL_MC_RESUME 26
2244 PAL Procedure - PAL_HALT.
2246 Enter the low-power HALT state or an implementation-dependent
2247 low-power state. It is optinal. The PAL procedure supports the
2248 Static Registers calling convention. It could be called at
2251 @param Index Index of PAL_HALT within the list of PAL
2253 @param HaltState Unsigned 64-bit integer denoting low power
2255 @param IoDetailPtr 8-byte aligned physical address pointer to
2256 information on the type of I/O
2257 (load/store) requested.
2259 @retval 0 Call completed without error
2260 @retval -1 Unimplemented procedure
2261 @retval -2 Invalid argument
2262 @retval -3 Call completed with error.
2264 @return R9 Value returned if a load instruction is requested
2265 in the io_detail_ptr
2272 PAL Procedure - PAL_HALT_INFO.
2274 Return the low power capabilities of the processor. It is
2275 required by IPF. The PAL procedure supports the
2276 Stacked Registers calling convention. It could be called at
2277 physical and virtual mode.
2279 @param Index Index of PAL_HALT_INFO within the list of PAL
2281 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
2282 on an 8-byte boundary.
2284 @retval 0 Call completed without error
2285 @retval -2 Invalid argument
2286 @retval -3 Call completed with error.
2289 #define PAL_HALT_INFO 257
2293 PAL Procedure - PAL_HALT_LIGHT.
2295 Enter the low power LIGHT HALT state. It is required by
2296 IPF. The PAL procedure supports the Static Registers calling
2297 convention. It could be called at physical and virtual mode.
2299 @param Index Index of PAL_HALT_LIGHT within the list of PAL
2302 @retval 0 Call completed without error
2303 @retval -2 Invalid argument
2304 @retval -3 Call completed with error.
2307 #define PAL_HALT_LIGHT 29
2310 PAL Procedure - PAL_CACHE_LINE_INIT.
2312 Initialize tags and data of a cache line for processor
2313 testing. It is required by IPF. The PAL procedure supports the
2314 Static Registers calling convention. It could be called at
2315 physical and virtual mode.
2317 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
2319 @param Address Unsigned 64-bit integer value denoting the
2320 physical address from which the physical page
2321 number is to be generated. The address must be
2322 an implemented physical address, bit 63 must
2324 @param DataValue 64-bit data value which is used to
2325 initialize the cache line.
2327 @retval 0 Call completed without error
2328 @retval -2 Invalid argument
2329 @retval -3 Call completed with error.
2332 #define PAL_CACHE_LINE_INIT 31
2335 PAL Procedure - PAL_CACHE_READ.
2337 Read tag and data of a cache line for diagnostic testing. It
2338 is optional. The PAL procedure supports the
2339 Satcked Registers calling convention. It could be called at
2342 @param Index Index of PAL_CACHE_READ within the list of PAL
2344 @param LineId 8-byte formatted value describing where in the
2345 cache to read the data.
2346 @param Address 64-bit 8-byte aligned physical address from
2347 which to read the data. The address must be an
2348 implemented physical address on the processor
2349 model with bit 63 set to zero.
2351 @retval 1 The word at address was found in the
2352 cache, but the line was invalid.
2353 @retval 0 Call completed without error
2354 @retval -2 Invalid argument
2355 @retval -3 Call completed with error.
2356 @retval -5 The word at address was not found in the
2358 @retval -7 The operation requested is not supported
2359 for this cache_type and level.
2361 @return R9 Right-justified value returned from the cache
2363 @return R10 The number of bits returned in data.
2364 @return R11 The status of the cache line.
2367 #define PAL_CACHE_READ 259
2371 PAL Procedure - PAL_CACHE_WRITE.
2373 Write tag and data of a cache for diagnostic testing. It is
2374 optional. The PAL procedure supports the Satcked Registers
2375 calling convention. It could be called at physical mode.
2377 @param Index Index of PAL_CACHE_WRITE within the list of PAL
2379 @param LineId 8-byte formatted value describing where in the
2380 cache to write the data.
2381 @param Address 64-bit 8-byte aligned physical address at
2382 which the data should be written. The address
2383 must be an implemented physical address on the
2384 processor model with bit 63 set to 0.
2385 @param Data Unsigned 64-bit integer value to write into
2386 the specified part of the cache.
2388 @retval 0 Call completed without error
2389 @retval -2 Invalid argument
2390 @retval -3 Call completed with error.
2391 @retval -7 The operation requested is not supported
2392 for this cache_type and level.
2395 #define PAL_CACHE_WRITE 260
2398 PAL Procedure - PAL_TEST_INFO.
2400 Returns alignment and size requirements needed for the memory
2401 buffer passed to the PAL_TEST_PROC procedure as well as
2402 information on self-test control words for the processor self
2403 tests. It is required by IPF. The PAL procedure supports the
2404 Static Registers calling convention. It could be called at
2407 @param Index Index of PAL_TEST_INFO within the list of PAL
2409 @param TestPhase Unsigned integer that specifies which phase
2410 of the processor self-test information is
2411 being requested on. A value of 0 indicates
2412 the phase two of the processor self-test and
2413 a value of 1 indicates phase one of the
2414 processor self-test. All other values are
2417 @retval 0 Call completed without error
2418 @retval -2 Invalid argument
2419 @retval -3 Call completed with error.
2421 @return R9 Unsigned 64-bit integer denoting the number of
2422 bytes of main memory needed to perform the second
2423 phase of processor self-test.
2424 @return R10 Unsigned 64-bit integer denoting the alignment
2425 required for the memory buffer.
2426 @return R11 48-bit wide bit-field indicating if control of
2427 the processor self-tests is supported and which
2428 bits of the test_control field are defined for
2432 #define PAL_TEST_INFO 37
2436 @param BufferSize Indicates the size in bytes of the memory
2437 buffer that is passed to this procedure.
2438 BufferSize must be greater than or equal in
2439 size to the bytes_needed return value from
2440 PAL_TEST_INFO, otherwise this procedure will
2441 return with an invalid argument return
2444 @param TestPhase Defines which phase of the processor
2445 self-tests are requested to be run. A value
2446 of zero indicates to run phase two of the
2447 processor self-tests. Phase two of the
2448 processor self-tests are ones that require
2449 external memory to execute correctly. A
2450 value of one indicates to run phase one of
2451 the processor self-tests. Phase one of the
2452 processor self-tests are tests run during
2453 PALE_RESET and do not depend on external
2454 memory to run correctly. When the caller
2455 requests to have phase one of the processor
2456 self-test run via this procedure call, a
2457 memory buffer may be needed to save and
2458 restore state as required by the PAL calling
2459 conventions. The procedure PAL_TEST_INFO
2460 informs the caller about the requirements of
2465 UINT64 BufferSize
:56;
2467 } PAL_TEST_INFO_INFO
;
2471 @param TestControl This is an ordered implementation-specific
2472 control word that allows the user control
2473 over the length and runtime of the
2474 processor self-tests. This control word is
2475 ordered from the longest running tests up
2476 to the shortest running tests with bit 0
2477 controlling the longest running test. PAL
2478 may not implement all 47-bits of the
2479 test_control word. PAL communicates if a
2480 bit provides control by placing a zero in
2481 that bit. If a bit provides no control,
2482 PAL will place a one in it. PAL will have
2483 two sets of test_control bits for the two
2484 phases of the processor self-test. PAL
2485 provides information about implemented
2486 test_control bits at the hand-off from PAL
2487 to SAL for the firmware recovery check.
2488 These test_control bits provide control
2489 for phase one of processor self-test. It
2490 also provides this information via the PAL
2491 procedure call PAL_TEST_INFO for both the
2492 phase one and phase two processor tests
2493 depending on which information the caller
2494 is requesting. PAL interprets these bits
2495 as input parameters on two occasions. The
2496 first time is when SAL passes control back
2497 to PAL after the firmware recovery check.
2498 The second time is when a call to
2499 PAL_TEST_PROC is made. When PAL interprets
2500 these bits it will only interpret
2501 implemented test_control bits and will
2502 ignore the values located in the
2503 unimplemented test_control bits. PAL
2504 interprets the implemented bits such that
2505 if a bit contains a zero, this indicates
2506 to run the test. If a bit contains a one,
2507 this indicates to PAL to skip the test. If
2508 the cs bit indicates that control is not
2509 available, the test_control bits will be
2510 ignored or generate an illegal argument in
2511 procedure calls if the caller sets these
2514 @param ControlSupport This bit defines if an implementation
2515 supports control of the PAL self-tests
2516 via the self-test control word. If
2517 this bit is 0, the implementation does
2518 not support control of the processor
2519 self-tests via the self-test control
2520 word. If this bit is 1, the
2521 implementation does support control of
2522 the processor self-tests via the
2523 self-test control word. If control is
2524 not supported, GR37 will be ignored at
2525 the hand-off between SAL and PAL after
2526 the firmware recovery check and the
2527 PAL procedures related to the
2528 processor self-tests may return
2529 illegal arguments if a user tries to
2530 use the self-test control features.
2534 UINT64 TestControl
:47;
2535 UINT64 ControlSupport
:1;
2537 } PAL_SELF_TEST_CONTROL
;
2541 @param Attributes Specifies the memory attributes that are
2542 allowed to be used with the memory buffer
2543 passed to this procedure. The attributes
2544 parameter is a vector where each bit
2545 represents one of the virtual memory
2546 attributes defined by the architecture.See
2547 MEMORY_AATRIBUTES. The caller is required
2548 to support the cacheable attribute for the
2549 memory buffer, otherwise an invalid
2550 argument will be returned.
2553 @param TestControl Is the self-test control word
2554 corresponding to the test_phase passed.
2555 This test_control directs the coverage and
2556 runtime of the processor self-tests
2557 specified by the test_phase input
2558 argument. Information on if this
2559 feature is implemented and the number of
2560 bits supported can be obtained by the
2561 PAL_TEST_INFO procedure call. If this
2562 feature is implemented by the processor,
2563 the caller can selectively skip parts of
2564 the processor self-test by setting
2565 test_control bits to a one. If a bit has a
2566 zero, this test will be run. The values in
2567 the unimplemented bits are ignored. If
2568 PAL_TEST_INFO indicated that the self-test
2569 control word is not implemented, this
2570 procedure will return with an invalid
2571 argument status if the caller sets any of
2572 the test_control bits. See
2573 PAL_SELF_TEST_CONTROL.
2576 UINT64 Attributes
:8;
2578 UINT64 TestControl
:48;
2582 PAL Procedure - PAL_TEST_PROC.
2584 Perform late processor self test. It is required by IPF. The
2585 PAL procedure supports the Static Registers calling
2586 convention. It could be called at physical mode.
2588 @param Index Index of PAL_TEST_PROC within the list of PAL
2590 @param TestAddress 64-bit physical address of main memory
2591 area to be used by processor self-test.
2592 The memory region passed must be
2593 cacheable, bit 63 must be zero.
2594 @param TestInfo Input argument specifying the size of the
2595 memory buffer passed and the phase of the
2596 processor self-test that should be run. See
2598 @param TestParam Input argument specifying the self-test
2599 control word and the allowable memory
2600 attributes that can be used with the memory
2601 buffer. See PAL_TEST_CONTROL.
2603 @retval 1 Call completed without error, but hardware
2604 failures occurred during self-test.
2605 @retval 0 Call completed without error
2606 @retval -2 Invalid argument
2607 @retval -3 Call completed with error.
2609 @return R9 Formatted 8-byte value denoting the state of the
2610 processor after self-test
2613 #define PAL_TEST_PROC 258
2617 @param NumberOfInterruptControllers Number of interrupt
2618 controllers currently
2619 enabled on the system.
2621 @param NumberOfProcessors Number of processors currently
2622 enabled on the system.
2626 UINT32 NumberOfInterruptControllers
;
2627 UINT32 NumberOfProcessors
;
2628 } PAL_PLATFORM_INFO
;
2631 PAL Procedure - PAL_COPY_INFO.
2633 Return information needed to relocate PAL procedures and PAL
2634 PMI code to memory. It is required by IPF. The PAL procedure
2635 supports the Static Registers calling convention. It could be
2636 called at physical mode.
2638 @param Index Index of PAL_COPY_INFO within the list of PAL
2640 @param CopyType Unsigned integer denoting type of procedures
2641 for which copy information is requested.
2642 @param PlatformInfo 8-byte formatted value describing the
2643 number of processors and the number of
2644 interrupt controllers currently enabled
2645 on the system. See PAL_PLATFORM_INFO.
2646 @param McaProcStateInfo Unsigned integer denoting the number
2647 of bytes that SAL needs for the
2648 min-state save area for each
2651 @retval 0 Call completed without error
2652 @retval -2 Invalid argument
2653 @retval -3 Call completed with error.
2655 @return R9 Unsigned integer denoting the number of bytes of
2656 PAL information that must be copied to main
2658 @return R10 Unsigned integer denoting the starting alignment
2659 of the data to be copied.
2662 #define PAL_COPY_INFO 30
2665 PAL Procedure - PAL_COPY_PAL.
2667 Relocate PAL procedures and PAL PMI code to memory. It is
2668 required by IPF. The PAL procedure supports the Stacked
2669 Registers calling convention. It could be called at physical
2672 @param Index Index of PAL_COPY_PAL within the list of PAL
2674 @param TargetAddress Physical address of a memory buffer to
2675 copy relocatable PAL procedures and PAL
2677 @param AllocSize Unsigned integer denoting the size of the
2678 buffer passed by SAL for the copy operation.
2679 @param CopyOption Unsigned integer indicating whether
2680 relocatable PAL code and PAL PMI code
2681 should be copied from firmware address
2682 space to main memory.
2684 @retval 0 Call completed without error
2685 @retval -2 Invalid argument
2686 @retval -3 Call completed with error.
2688 @return R9 Unsigned integer denoting the offset of PAL_PROC
2689 in the relocatable segment copied.
2692 #define PAL_COPY_PAL 256
2695 PAL Procedure - PAL_ENTER_IA_32_ENV.
2697 Enter IA-32 System environment. It is optional. The PAL
2698 procedure supports the Static Registers calling convention.
2699 It could be called at physical mode.
2701 Note: Since this is a special call, it does not follow the PAL
2702 static register calling convention. GR28 contains the index of
2703 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
2704 input arguments including GR29-GR31 are setup by SAL to values
2705 as required by the IA-32 operating system defined in Table
2706 11-67. The registers that are designated as preserved, scratch,
2707 input arguments and procedure return values by the static
2708 procedure calling convention are not followed by this call. For
2709 instance, GR5 and GR6 need not be preserved since these are
2710 regarded as scratch by the IA-32 operating system. Note: In an
2711 MP system, this call must be COMPLETED on the first CPU to enter
2712 the IA-32 System Environment (may or may not be the BSP) prior
2713 to being called on the remaining processors in the MP system.
2715 @param Index GR28 contains the index of the
2716 PAL_ENTER_IA_32_ENV call within the list of PAL
2720 @retval The status is returned in GR4.
2721 -1 - Un-implemented procedure 0 JMPE detected
2724 0 - 1 SAL allocated buffer for IA-32 System
2725 Environment operation is too small
2727 2 - IA-32 Firmware Checksum Error
2729 3 - SAL allocated buffer for IA-32 System
2730 Environment operation is not properly aligned
2732 4 - Error in SAL MP Info Table
2734 5 - Error in SAL Memory Descriptor Table
2736 6 - Error in SAL System Table
2738 7 - Inconsistent IA-32 state
2740 8 - IA-32 Firmware Internal Error
2742 9 - IA-32 Soft Reset (Note: remaining register
2743 state is undefined for this termination
2746 10 - Machine Check Error
2748 11 - Error in SAL I/O Intercept Table
2750 12 - Processor exit due to other processor in
2751 MP system terminating the IA32 system
2752 environment. (Note: remaining register state
2753 is undefined for this termination reason.)
2755 13 - Itanium architecture-based state
2756 corruption by either SAL PMI handler or I/O
2757 Intercept callback function.
2761 #define PAL_ENTER_IA_32_ENV 33
2764 PAL Procedure - PAL_PMI_ENTRYPOINT.
2766 Register PMI memory entrypoints with processor. It is required
2767 by IPF. The PAL procedure supports the Stacked Registers
2768 calling convention. It could be called at physical mode.
2770 @param Index Index of PAL_PMI_ENTRYPOINT within the list of
2772 @param SalPmiEntry 256-byte aligned physical address of SAL
2773 PMI entrypoint in memory.
2775 @retval 0 Call completed without error
2776 @retval -2 Invalid argument
2777 @retval -3 Call completed with error.
2780 #define PAL_PMI_ENTRYPOINT 32
2785 The ASCII brand identification string will be copied to the
2786 address specified in the address input argument. The processor
2787 brand identification string is defined to be a maximum of 128
2788 characters long; 127 bytes will contain characters and the 128th
2789 byte is defined to be NULL (0). A processor may return less than
2790 the 127 ASCII characters as long as the string is null
2791 terminated. The string length will be placed in the brand_info
2795 #define PAL_BRAND_INFO_ID_REQUEST 0
2798 PAL Procedure - PAL_BRAND_INFO.
2800 Provides processor branding information. It is optional by
2801 IPF. The PAL procedure supports the Stacked Registers calling
2802 convention. It could be called at physical and Virtual mode.
2804 @param Index Index of PAL_BRAND_INFO within the list of PAL
2806 @param InfoRequest Unsigned 64-bit integer specifying the
2807 information that is being requested. (See
2808 PAL_BRAND_INFO_ID_REQUEST)
2809 @param Address Unsigned 64-bit integer specifying the
2810 address of the 128-byte block to which the
2811 processor brand string shall be written.
2813 @retval 0 Call completed without error
2814 @retval -1 Unimplemented procedure
2815 @retval -2 Invalid argument
2816 @retval -3 Call completed with error.
2817 @retval -6 Input argument is not implemented.
2819 @return R9 Brand information returned. The format of this
2820 value is dependent on the input values passed.
2823 #define PAL_BRAND_INFO 274
2826 PAL Procedure - PAL_GET_HW_POLICY.
2828 Returns the current hardware resource sharing policy of the
2829 processor. It is optional by IPF. The PAL procedure supports
2830 the Static Registers calling convention. It could be called at
2831 physical and Virtual mode.
2834 @param Index Index of PAL_GET_HW_POLICY within the list of PAL
2836 @param ProcessorNumber Unsigned 64-bit integer that specifies
2837 for which logical processor
2838 information is being requested. This
2839 input argument must be zero for the
2840 first call to this procedure and can
2841 be a maximum value of one less than
2842 the number of logical processors
2843 impacted by the hardware resource
2844 sharing policy, which is returned by
2845 the R10 return value.
2847 @retval 0 Call completed without error
2848 @retval -1 Unimplemented procedure
2849 @retval -2 Invalid argument
2850 @retval -3 Call completed with error.
2851 @retval -9 Call requires PAL memory buffer.
2853 @return R9 Unsigned 64-bit integer representing the current
2854 hardware resource sharing policy.
2855 @return R10 Unsigned 64-bit integer that returns the number
2856 of logical processors impacted by the policy
2858 @return R11 Unsigned 64-bit integer containing the logical
2859 address of one of the logical processors
2860 impacted by policy modification.
2863 #define PAL_GET_HW_POLICY 48
2867 // Value of PAL_SET_HW_POLICY.Policy
2869 #define PAL_SET_HW_POLICY_PERFORMANCE 0
2870 #define PAL_SET_HW_POLICY_FAIRNESS 1
2871 #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
2872 #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
2875 PAL Procedure - PAL_SET_HW_POLICY.
2877 Sets the current hardware resource sharing policy of the
2878 processor. It is optional by IPF. The PAL procedure supports
2879 the Static Registers calling convention. It could be called at
2880 physical and Virtual mode.
2882 @param Index Index of PAL_SET_HW_POLICY within the list of PAL
2884 @param Policy Unsigned 64-bit integer specifying the hardware
2885 resource sharing policy the caller is setting.
2886 See Value of PAL_SET_HW_POLICY.Policy above.
2888 @retval 1 Call completed successfully but could not
2889 change the hardware policy since a
2890 competing logical processor is set in
2891 exclusive high priority.
2892 @retval 0 Call completed without error
2893 @retval -1 Unimplemented procedure
2894 @retval -2 Invalid argument
2895 @retval -3 Call completed with error.
2896 @retval -9 Call requires PAL memory buffer.
2899 #define PAL_SET_HW_POLICY 49
2904 @param Mode Bit2:0, Indicates the mode of operation for this
2905 procedure: 0 - Query mode 1 - Error inject mode
2906 (err_inj should also be specified) 2 - Cancel
2907 outstanding trigger. All other fields in
2908 PAL_MC_ERROR_TYPE_INFO,
2909 PAL_MC_ERROR_STRUCTURE_INFO and
2910 PAL_MC_ERROR_DATA_BUFFER are ignored. All other
2911 values are reserved.
2913 @param ErrorInjection Bit5:3, indicates the mode of error
2914 injection: 0 - Error inject only (no
2915 error consumption) 1 - Error inject
2916 and consume All other values are
2920 @param ErrorSeverity Bit7:6, indicates the severity desired
2921 for error injection/query. Definitions
2922 of the different error severity types
2923 0 - Corrected error 1 - Recoverable
2924 error 2 - Fatal error 3 - Reserved
2927 @param ErrorStructure Bit12:8, Indicates the structure
2928 identification for error
2929 injection/query: 0 - Any structure
2930 (cannot be used during query mode).
2931 When selected, the structure type used
2932 for error injection is determined by
2933 PAL. 1 - Cache 2 - TLB 3 - Register
2934 file 4 - Bus/System interconnect 5-15
2935 - Reserved 16-31 - Processor
2936 specific error injection
2937 capabilities.ErrorDataBuffer is used
2938 to specify error types. Please refer
2939 to the processor specific
2940 documentation for additional details.
2942 @param StructureHierarchy Bit15:13, Indicates the structure
2944 injection/query: 0 - Any level of
2945 hierarchy (cannot be used during
2946 query mode). When selected, the
2947 structure hierarchy used for error
2948 injection is determined by PAL. 1
2949 - Error structure hierarchy
2950 level-1 2 - Error structure
2951 hierarchy level-2 3 - Error
2952 structure hierarchy level-3 4 -
2953 Error structure hierarchy level-4
2954 All other values are reserved.
2955 Reserved 63:16 Reserved
2960 UINT64 ErrorInjection
:3;
2961 UINT64 ErrorSeverity
:2;
2962 UINT64 ErrorStructure
:5;
2963 UINT64 StructureHierarchy
:3;
2965 } PAL_MC_ERROR_TYPE_INFO
;
2969 @param StructInfoIsValid Bit0 When 1, indicates that the
2970 structure information fields
2971 (c_t,cl_p,cl_id) are valid and
2972 should be used for error injection.
2973 When 0, the structure information
2974 fields are ignored, and the values
2975 of these fields used for error
2977 implementation-specific.
2979 @param CacheType Bit2:1 Indicates which cache should be used
2980 for error injection: 0 - Reserved 1 -
2981 Instruction cache 2 - Data or unified cache
2985 @param PortionOfCacheLine Bit5:3 Indicates the portion of the
2986 cache line where the error should
2987 be injected: 0 - Reserved 1 - Tag
2988 2 - Data 3 - mesi All other
2989 values are reserved.
2991 @param Mechanism Bit8:6 Indicates which mechanism is used to
2992 identify the cache line to be used for error
2993 injection: 0 - Reserved 1 - Virtual address
2994 provided in the inj_addr field of the buffer
2995 pointed to by err_data_buffer should be used
2996 to identify the cache line for error
2997 injection. 2 - Physical address provided in
2998 the inj_addr field of the buffer pointed to
2999 by err_data_buffershould be used to identify
3000 the cache line for error injection. 3 - way
3001 and index fields provided in err_data_buffer
3002 should be used to identify the cache line
3003 for error injection. All other values are
3006 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a
3007 multiple bit, non-correctable
3008 error should be injected in the
3009 cache line specified by cl_id.
3010 If this injected error is not
3011 consumed, it may eventually
3012 cause a data-poisoning event
3013 resulting in a corrected error
3014 signal, when the associated
3015 cache line is cast out (implicit
3016 or explicit write-back of the
3017 cache line). The error severity
3018 specified by err_sev in
3019 err_type_info must be set to 0
3020 (corrected error) when this bit
3024 @param TrigerInfoIsValid Bit32 When 1, indicates that the
3025 trigger information fields (trigger,
3026 trigger_pl) are valid and should be
3027 used for error injection. When 0,
3028 the trigger information fields are
3029 ignored and error injection is
3030 performed immediately.
3032 @param Triger Bit36:33 Indicates the operation type to be
3033 used as the error trigger condition. The
3034 address corresponding to the trigger is
3035 specified in the trigger_addr field of the
3036 buffer pointed to by err_data_buffer: 0 -
3037 Instruction memory access. The trigger match
3038 conditions for this operation type are similar
3039 to the IBR address breakpoint match conditions
3040 1 - Data memory access. The trigger match
3041 conditions for this operation type are similar
3042 to the DBR address breakpoint match conditions
3043 All other values are reserved.
3045 @param PrivilegeOfTriger Bit39:37 Indicates the privilege
3046 level of the context during which
3047 the error should be injected: 0 -
3048 privilege level 0 1 - privilege
3049 level 1 2 - privilege level 2 3 -
3050 privilege level 3 All other values
3051 are reserved. If the implementation
3052 does not support privilege level
3053 qualifier for triggers (i.e. if
3054 trigger_pl is 0 in the capabilities
3055 vector), this field is ignored and
3056 triggers can be taken at any
3061 UINT64 StructInfoIsValid
:1;
3063 UINT64 PortionOfCacheLine
:3;
3065 UINT64 DataPoisonOfCacheLine
:1;
3066 UINT64 Reserved1
:22;
3067 UINT64 TrigerInfoIsValid
:1;
3069 UINT64 PrivilegeOfTriger
:3;
3070 UINT64 Reserved2
:24;
3071 } PAL_MC_ERROR_STRUCT_INFO
;
3075 Buffer Pointed to by err_data_buffer - TLB
3079 UINT64 TrigerAddress
;
3080 UINT64 VirtualPageNumber
:52;
3083 UINT64 Reserved2
:40;
3084 } PAL_MC_ERROR_DATA_BUFFER_TLB
;
3087 PAL Procedure - PAL_MC_ERROR_INJECT.
3089 Injects the requested processor error or returns information
3090 on the supported injection capabilities for this particular
3091 processor implementation. It is optional by IPF. The PAL
3092 procedure supports the Stacked Registers calling convention.
3093 It could be called at physical and Virtual mode.
3095 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
3097 @param ErrorTypeInfo Unsigned 64-bit integer specifying the
3098 first level error information which
3099 identifies the error structure and
3100 corresponding structure hierarchy, and
3102 @param ErrorStructInfo Unsigned 64-bit integer identifying
3103 the optional structure specific
3104 information that provides the second
3105 level details for the requested error.
3106 @param ErrorDataBuffer 64-bit physical address of a buffer
3107 providing additional parameters for
3108 the requested error. The address of
3109 this buffer must be 8-byte aligned.
3111 @retval 0 Call completed without error
3112 @retval -1 Unimplemented procedure
3113 @retval -2 Invalid argument
3114 @retval -3 Call completed with error.
3115 @retval -4 Call completed with error; the requested
3116 error could not be injected due to failure in
3117 locating the target location in the specified
3119 @retval -5 Argument was valid, but requested error
3120 injection capability is not supported.
3121 @retval -9 Call requires PAL memory buffer.
3123 @return R9 64-bit vector specifying the supported error
3124 injection capabilities for the input argument
3125 combination of struct_hier, err_struct and
3126 err_sev fields in ErrorTypeInfo.
3127 @return R10 64-bit vector specifying the architectural
3128 resources that are used by the procedure.
3131 #define PAL_MC_ERROR_INJECT 276
3135 // Types of PAL_GET_PSTATE.Type
3137 #define PAL_GET_PSTATE_RECENT 0
3138 #define PAL_GET_PSTATE_AVERAGE_NEW_START 1
3139 #define PAL_GET_PSTATE_AVERAGE 2
3140 #define PAL_GET_PSTATE_NOW 3
3143 PAL Procedure - PAL_GET_PSTATE.
3145 Returns the performance index of the processor. It is optional
3146 by IPF. The PAL procedure supports the Stacked Registers
3147 calling convention. It could be called at physical and Virtual
3150 @param Index Index of PAL_GET_PSTATE within the list of PAL
3152 @param Type Type of performance_index value to be returned
3153 by this procedure.See PAL_GET_PSTATE.Type above.
3155 @retval 1 Call completed without error, but accuracy
3156 of performance index has been impacted by a
3157 thermal throttling event, or a
3158 hardware-initiated event.
3159 @retval 0 Call completed without error
3160 @retval -1 Unimplemented procedure
3161 @retval -2 Invalid argument
3162 @retval -3 Call completed with error.
3163 @retval -9 Call requires PAL memory buffer.
3165 @return R9 Unsigned integer denoting the processor
3166 performance for the time duration since the last
3167 PAL_GET_PSTATE procedure call was made. The
3168 value returned is between 0 and 100, and is
3169 relative to the performance index of the highest
3173 #define PAL_GET_PSTATE 262
3177 Layout of PAL_PSTATE_INFO.PStateBuffer
3181 UINT32 PerformanceIndex
:7;
3183 UINT32 TypicalPowerDissipation
:20;
3184 UINT32 TransitionLatency1
;
3185 UINT32 TransitionLatency2
;
3187 } PAL_PSTATE_INFO_BUFFER
;
3191 PAL Procedure - PAL_PSTATE_INFO.
3193 Returns information about the P-states supported by the
3194 processor. It is optional by IPF. The PAL procedure supports
3195 the Static Registers calling convention. It could be called
3196 at physical and Virtual mode.
3198 @param Index Index of PAL_PSTATE_INFO within the list of PAL
3200 @param PStateBuffer 64-bit pointer to a 256-byte buffer
3201 aligned on an 8-byte boundary. See
3202 PAL_PSTATE_INFO_BUFFER above.
3204 @retval 0 Call completed without error
3205 @retval -1 Unimplemented procedure
3206 @retval -2 Invalid argument
3207 @retval -3 Call completed with error.
3209 @return R9 Unsigned integer denoting the number of P-states
3210 supported. The maximum value of this field is 16.
3211 @return R10 Dependency domain information
3214 #define PAL_PSTATE_INFO 44
3218 PAL Procedure - PAL_SET_PSTATE.
3220 To request a processor transition to a given P-state. It is
3221 optional by IPF. The PAL procedure supports the Stacked
3222 Registers calling convention. It could be called at physical
3225 @param Index Index of PAL_SET_PSTATE within the list of PAL
3227 @param PState Unsigned integer denoting the processor
3228 P-state being requested.
3229 @param ForcePState Unsigned integer denoting whether the
3230 P-state change should be forced for the
3233 @retval 1 Call completed without error, but
3234 transition request was not accepted
3235 @retval 0 Call completed without error
3236 @retval -1 Unimplemented procedure
3237 @retval -2 Invalid argument
3238 @retval -3 Call completed with error.
3239 @retval -9 Call requires PAL memory buffer.
3242 #define PAL_SET_PSTATE 263
3245 PAL Procedure - PAL_SHUTDOWN.
3247 Put the logical processor into a low power state which can be
3248 exited only by a reset event. It is optional by IPF. The PAL
3249 procedure supports the Static Registers calling convention. It
3250 could be called at physical mode.
3252 @param Index Index of PAL_SHUTDOWN within the list of PAL
3254 @param NotifyPlatform 8-byte aligned physical address
3255 pointer providing details on how to
3256 optionally notify the platform that
3257 the processor is entering a shutdown
3260 @retval -1 Unimplemented procedure
3261 @retval -2 Invalid argument
3262 @retval -3 Call completed with error.
3263 @retval -9 Call requires PAL memory buffer.
3266 #define PAL_SHUTDOWN 45
3270 Layout of PAL_MEMORY_BUFFER.ControlWord
3274 UINT64 Registration
:1;
3275 UINT64 ProbeInterrupt
:1;
3277 } PAL_MEMORY_CONTROL_WORD
;
3280 PAL Procedure - PAL_MEMORY_BUFFER.
3282 Provides cacheable memory to PAL for exclusive use during
3283 runtime. It is optional by IPF. The PAL procedure supports the
3284 Static Registers calling convention. It could be called at
3287 @param Index Index of PAL_MEMORY_BUFFER within the list of PAL
3289 @param BaseAddress Physical address of the memory buffer
3290 allocated for PAL use.
3291 @param AllocSize Unsigned integer denoting the size of the
3293 @param ControlWord Formatted bit vector that provides control
3294 options for this procedure. See
3295 PAL_MEMORY_CONTROL_WORD above.
3297 @retval 1 Call has not completed a buffer relocation
3298 due to a pending interrupt
3299 @retval 0 Call completed without error
3300 @retval -1 Unimplemented procedure
3301 @retval -2 Invalid argument
3302 @retval -3 Call completed with error.
3303 @retval -9 Call requires PAL memory buffer.
3305 @return R9 Returns the minimum size of the memory buffer
3306 required if the alloc_size input argument was
3310 #define PAL_MEMORY_BUFFER 277
3314 PAL Procedure - PAL_VP_CREATE.
3316 Initializes a new vpd for the operation of a new virtual
3317 processor in the virtual environment. It is optional by IPF.
3318 The PAL procedure supports the Stacked Registers calling
3319 convention. It could be called at Virtual mode.
3321 @param Index Index of PAL_VP_CREATE within the list of PAL
3323 @param Vpd 64-bit host virtual pointer to the Virtual
3324 Processor Descriptor (VPD).
3325 @param HostIva 64-bit host virtual pointer to the host IVT
3326 for the virtual processor
3327 @param OptionalHandler 64-bit non-zero host-virtual pointer
3328 to an optional handler for
3329 virtualization intercepts.
3331 @retval 0 Call completed without error
3332 @retval -1 Unimplemented procedure
3333 @retval -2 Invalid argument
3334 @retval -3 Call completed with error.
3335 @retval -9 Call requires PAL memory buffer.
3338 #define PAL_VP_CREATE 265
3342 Virtual Environment Information Parameter
3349 } PAL_VP_ENV_INFO_RETURN
;
3352 PAL Procedure - PAL_VP_ENV_INFO.
3354 Returns the parameters needed to enter a virtual environment.
3355 It is optional by IPF. The PAL procedure supports the Stacked
3356 Registers calling convention. It could be called at Virtual
3359 @param Index Index of PAL_VP_ENV_INFO within the list of PAL
3361 @param Vpd 64-bit host virtual pointer to the Virtual
3362 Processor Descriptor (VPD).
3363 @param HostIva 64-bit host virtual pointer to the host IVT
3364 for the virtual processor
3365 @param OptionalHandler 64-bit non-zero host-virtual pointer
3366 to an optional handler for
3367 virtualization intercepts.
3369 @retval 0 Call completed without error
3370 @retval -1 Unimplemented procedure
3371 @retval -2 Invalid argument
3372 @retval -3 Call completed with error.
3373 @retval -9 Call requires PAL memory buffer.
3375 @return R9 Unsigned integer denoting the number of bytes
3376 required by the PAL virtual environment buffer
3377 during PAL_VP_INIT_ENV
3378 @return R10 64-bit vector of virtual environment
3379 information. See PAL_VP_ENV_INFO_RETURN.
3383 #define PAL_VP_ENV_INFO 266
3386 PAL Procedure - PAL_VP_EXIT_ENV.
3388 Allows a logical processor to exit a virtual environment.
3389 It is optional by IPF. The PAL procedure supports the Stacked
3390 Registers calling convention. It could be called at Virtual
3393 @param Index Index of PAL_VP_EXIT_ENV within the list of PAL
3395 @param Iva Optional 64-bit host virtual pointer to the IVT
3396 when this procedure is done
3398 @retval 0 Call completed without error
3399 @retval -1 Unimplemented procedure
3400 @retval -2 Invalid argument
3401 @retval -3 Call completed with error.
3402 @retval -9 Call requires PAL memory buffer.
3405 #define PAL_VP_EXIT_ENV 267
3410 PAL Procedure - PAL_VP_INIT_ENV.
3412 Allows a logical processor to enter a virtual environment. It
3413 is optional by IPF. The PAL procedure supports the Stacked
3414 Registers calling convention. It could be called at Virtual
3417 @param Index Index of PAL_VP_INIT_ENV within the list of PAL
3419 @param ConfigOptions 64-bit vector of global configuration
3421 @param PhysicalBase Host physical base address of a block of
3422 contiguous physical memory for the PAL
3423 virtual environment buffer 1) This
3424 memory area must be allocated by the VMM
3425 and be 4K aligned. The first logical
3426 processor to enter the environment will
3427 initialize the physical block for
3428 virtualization operations.
3429 @param VirtualBase Host virtual base address of the
3430 corresponding physical memory block for
3431 the PAL virtual environment buffer : The
3432 VMM must maintain the host virtual to host
3433 physical data and instruction translations
3434 in TRs for addresses within the allocated
3435 address space. Logical processors in this
3436 virtual environment will use this address
3437 when transitioning to virtual mode
3440 @retval 0 Call completed without error
3441 @retval -1 Unimplemented procedure
3442 @retval -2 Invalid argument
3443 @retval -3 Call completed with error.
3444 @retval -9 Call requires PAL memory buffer.
3446 @return R9 Virtualization Service Address - VSA specifies
3447 the virtual base address of the PAL
3448 virtualization services in this virtual
3453 #define PAL_VP_INIT_ENV 268
3457 PAL Procedure - PAL_VP_REGISTER.
3459 Register a different host IVT and/or a different optional
3460 virtualization intercept handler for the virtual processor
3461 specified by vpd. It is optional by IPF. The PAL procedure
3462 supports the Stacked Registers calling convention. It could be
3463 called at Virtual mode.
3465 @param Index Index of PAL_VP_REGISTER within the list of PAL
3467 @param Vpd 64-bit host virtual pointer to the Virtual
3468 Processor Descriptor (VPD) host_iva 64-bit host
3469 virtual pointer to the host IVT for the virtual
3471 @param OptionalHandler 64-bit non-zero host-virtual pointer
3472 to an optional handler for
3473 virtualization intercepts.
3475 @retval 0 Call completed without error
3476 @retval -1 Unimplemented procedure
3477 @retval -2 Invalid argument
3478 @retval -3 Call completed with error.
3479 @retval -9 Call requires PAL memory buffer.
3482 #define PAL_VP_REGISTER 269
3486 PAL Procedure - PAL_VP_RESTORE.
3488 Restores virtual processor state for the specified vpd on the
3489 logical processor. It is optional by IPF. The PAL procedure
3490 supports the Stacked Registers calling convention. It could be
3491 called at Virtual mode.
3493 @param Index Index of PAL_VP_RESTORE within the list of PAL
3495 @param Vpd 64-bit host virtual pointer to the Virtual
3496 Processor Descriptor (VPD) host_iva 64-bit host
3497 virtual pointer to the host IVT for the virtual
3499 @param PalVector Vector specifies PAL procedure
3500 implementation-specific state to be
3503 @retval 0 Call completed without error
3504 @retval -1 Unimplemented procedure
3505 @retval -2 Invalid argument
3506 @retval -3 Call completed with error.
3507 @retval -9 Call requires PAL memory buffer.
3510 #define PAL_VP_RESTORE 270
3513 PAL Procedure - PAL_VP_SAVE.
3515 Saves virtual processor state for the specified vpd on the
3516 logical processor. It is optional by IPF. The PAL procedure
3517 supports the Stacked Registers calling convention. It could be
3518 called at Virtual mode.
3520 @param Index Index of PAL_VP_SAVE within the list of PAL
3522 @param Vpd 64-bit host virtual pointer to the Virtual
3523 Processor Descriptor (VPD) host_iva 64-bit host
3524 virtual pointer to the host IVT for the virtual
3526 @param PalVector Vector specifies PAL procedure
3527 implementation-specific state to be
3530 @retval 0 Call completed without error
3531 @retval -1 Unimplemented procedure
3532 @retval -2 Invalid argument
3533 @retval -3 Call completed with error.
3534 @retval -9 Call requires PAL memory buffer.
3537 #define PAL_VP_SAVE 271
3541 PAL Procedure - PAL_VP_TERMINATE.
3543 Terminates operation for the specified virtual processor. It
3544 is optional by IPF. The PAL procedure supports the Stacked
3545 Registers calling convention. It could be called at Virtual
3548 @param Index Index of PAL_VP_TERMINATE within the list of PAL
3550 @param Vpd 64-bit host virtual pointer to the Virtual
3551 Processor Descriptor (VPD)
3552 @param Iva Optional 64-bit host virtual pointer to the IVT
3553 when this procedure is done.
3555 @retval 0 Call completed without error
3556 @retval -1 Unimplemented procedure
3557 @retval -2 Invalid argument
3558 @retval -3 Call completed with error.
3559 @retval -9 Call requires PAL memory buffer.
3562 #define PAL_VP_TERMINATE 272
3566 Makes a PAL procedure call.
3568 This is a wrapper function to make a PAL procedure call. Based on the Index value,
3569 this API will make static or stacked PAL call. Architected procedures may be designated
3570 as required or optional. If a PAL procedure is specified as optional, a unique return
3571 code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
3572 This indicates that the procedure is not present in this PAL implementation. It is the
3573 caller's responsibility to check for this return code after calling any optional PAL
3574 procedure. No parameter checking is performed on the 4 input parameters, but there are
3575 some common rules that the caller should follow when making a PAL call. Any address
3576 passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
3577 may cause undefined results. For those parameters defined as reserved or some fields
3578 defined as reserved must be zero filled or the invalid argument return value may be
3579 returned or undefined result may occur during the execution of the procedure.
3580 This function is only available on IPF.
3582 @param Index The PAL procedure Index number.
3583 @param Arg2 The 2nd parameter for PAL procedure calls.
3584 @param Arg3 The 3rd parameter for PAL procedure calls.
3585 @param Arg4 The 4th parameter for PAL procedure calls.
3587 @return structure returned from the PAL Call procedure, including the status and return value.