4 Copyright (c) 2006 -2007, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef __PAL_CALL_LIB_H__
17 #define __PAL_CALL_LIB_H__
20 // CacheType of PAL_CACHE_FLUSH.
22 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
23 #define PAL_CACHE_FLUSH_DATA_ALL 2
24 #define PAL_CACHE_FLUSH_ALL 3
25 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
29 // Bitmask of Opearation of PAL_CACHE_FLUSH.
31 #define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
32 #define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
36 PAL Procedure - PAL_CACHE_FLUSH.
38 Flush the instruction or data caches. It is required by IPF.
39 The PAL procedure supports the Static Registers calling
40 convention. It could be called at virtual mode and physical
43 @param Index Index of PAL_CACHE_FLUSH within the
44 list of PAL procedures.
46 @param CacheType Unsigned 64-bit integer indicating
49 @param Operation Formatted bit vector indicating the
50 operation of this call.
52 @param ProgressIndicator Unsigned 64-bit integer specifying
53 the starting position of the flush
56 @return R9 Unsigned 64-bit integer specifying the vector
57 number of the pending interrupt.
59 @return R10 Unsigned 64-bit integer specifying the
60 starting position of the flush operation.
62 @return R11 Unsigned 64-bit integer specifying the vector
63 number of the pending interrupt.
65 @return Status 2 - Call completed without error, but a PMI
66 was taken during the execution of this
69 @return Status 1 - Call has not completed flushing due to
72 @return Status 0 - Call completed without error
74 @return Status -2 - Invalid argument
76 @return Status -3 - Call completed with error
79 #define PAL_CACHE_FLUSH 1
83 // Attributes of PAL_CACHE_CONFIG_INFO1
85 #define PAL_CACHE_ATTR_WT 0
86 #define PAL_CACHE_ATTR_WB 1
89 // PAL_CACHE_CONFIG_INFO1.StoreHint
91 #define PAL_CACHE_STORE_TEMPORAL 0
92 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
95 // PAL_CACHE_CONFIG_INFO1.StoreHint
97 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
98 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
101 // PAL_CACHE_CONFIG_INFO1.StoreHint
103 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
104 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
105 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
108 // Detail the characteristics of a given processor controlled
109 // cache in the cache hierarchy.
112 UINT64 IsUnified
: 1;
113 UINT64 Attributes
: 2;
114 UINT64 Associativity
:8;
117 UINT64 StoreLatency
:8;
120 } PAL_CACHE_INFO_RETURN1
;
123 // Detail the characteristics of a given processor controlled
124 // cache in the cache hierarchy.
128 UINT64 AliasBoundary
:8;
131 } PAL_CACHE_INFO_RETURN2
;
135 PAL Procedure - PAL_CACHE_INFO.
137 Return detailed instruction or data cache information. It is
138 required by IPF. The PAL procedure supports the Static
139 Registers calling convention. It could be called at virtual
140 mode and physical mode.
142 @param Index Index of PAL_CACHE_INFO within the list of
145 @param CacheLevel Unsigned 64-bit integer specifying the
146 level in the cache hierarchy for which
147 information is requested. This value must
148 be between 0 and one less than the value
149 returned in the cache_levels return value
150 from PAL_CACHE_SUMMARY.
152 @param CacheType Unsigned 64-bit integer with a value of 1
153 for instruction cache and 2 for data or
154 unified cache. All other values are
157 @param Reserved Should be 0.
160 @return R9 Detail the characteristics of a given
161 processor controlled cache in the cache
162 hierarchy. See PAL_CACHE_INFO_RETURN1.
164 @return R10 Detail the characteristics of a given
165 processor controlled cache in the cache
166 hierarchy. See PAL_CACHE_INFO_RETURN2.
168 @return R11 Reserved with 0.
171 @return Status 0 - Call completed without error
173 @return Status -2 - Invalid argument
175 @return Status -3 - Call completed with error
178 #define PAL_CACHE_INFO 2
183 // Level of PAL_CACHE_INIT.
185 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
188 // Restrict of PAL_CACHE_INIT.
190 #define PAL_CACHE_INIT_NO_RESTRICT 0
191 #define PAL_CACHE_INIT_RESTRICTED 1
195 PAL Procedure - PAL_CACHE_INIT.
197 Initialize the instruction or data caches. It is required by
198 IPF. The PAL procedure supports the Static Registers calling
199 convention. It could be called at physical mode.
201 @param Index Index of PAL_CACHE_INIT within the list of PAL
204 @param Level Unsigned 64-bit integer containing the level of
205 cache to initialize. If the cache level can be
206 initialized independently, only that level will
207 be initialized. Otherwise
208 implementation-dependent side-effects will
211 @param CacheType Unsigned 64-bit integer with a value of 1 to
212 initialize the instruction cache, 2 to
213 initialize the data cache, or 3 to
214 initialize both. All other values are
217 @param Restrict Unsigned 64-bit integer with a value of 0 or
218 1. All other values are reserved. If
219 restrict is 1 and initializing the specified
220 level and cache_type of the cache would
221 cause side-effects, PAL_CACHE_INIT will
222 return -4 instead of initializing the cache.
225 @return Status 0 - Call completed without error
227 @return Status -2 - Invalid argument
229 @return Status -3 - Call completed with error.
231 @return Status -4 - Call could not initialize the specified
232 level and cache_type of the cache without
233 side-effects and restrict was 1.
236 #define PAL_CACHE_INIT 3
240 // PAL_CACHE_PROTECTION.Method.
242 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
243 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
244 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
245 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
250 // PAL_CACHE_PROTECTION.TagOrData.
252 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
253 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
254 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
255 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
258 // 32-bit protection information structures.
267 } PAL_CACHE_PROTECTION
;
271 PAL Procedure - PAL_CACHE_PROT_INFO.
273 Return instruction or data cache protection information. It is
274 required by IPF. The PAL procedure supports the Static
275 Registers calling convention. It could be called at physical
276 mode and Virtual mode.
278 @param Index Index of PAL_CACHE_PROT_INFO within the list of
281 @param CacheLevel Unsigned 64-bit integer specifying the level
282 in the cache hierarchy for which information
283 is requested. This value must be between 0
284 and one less than the value returned in the
285 cache_levels return value from
288 @param CacheType Unsigned 64-bit integer with a value of 1
289 for instruction cache and 2 for data or
290 unified cache. All other values are
293 @return R9 Detail the characteristics of a given
294 processor controlled cache in the cache
295 hierarchy. See PAL_CACHE_PROTECTION[0..1].
297 @return R10 Detail the characteristics of a given
298 processor controlled cache in the cache
299 hierarchy. See PAL_CACHE_PROTECTION[2..3].
301 @return R11 Detail the characteristics of a given
302 processor controlled cache in the cache
303 hierarchy. See PAL_CACHE_PROTECTION[4..5].
306 @return Status 0 - Call completed without error
308 @return Status -2 - Invalid argument
310 @return Status -3 - Call completed with error.
313 #define PAL_CACHE_PROT_INFO 38
317 @param ThreadId The thread identifier of the logical
318 processor for which information is being
319 returned. This value will be unique on a per
322 @param CoreId The core identifier of the logical processor
323 for which information is being returned.
324 This value will be unique on a per physical
325 processor package basis.
329 UINT64 ThreadId
: 16;
330 UINT64 Reserved1
: 16;
332 UINT64 Reserved2
: 16;
333 } PAL_PCOC_N_CACHE_INFO1
;
337 @param LogicalAddress Logical address: geographical address
338 of the logical processor for which
339 information is being returned. This is
340 the same value that is returned by the
341 PAL_FIXED_ADDR procedure when it is
342 called on the logical processor.
346 UINT64 LogicalAddress
: 16;
347 UINT64 Reserved1
: 16;
348 UINT64 Reserved2
: 32;
349 } PAL_PCOC_N_CACHE_INFO2
;
353 PAL Procedure - PAL_CACHE_SHARED_INFO.
355 Returns information on which logical processors share caches.
356 It is optional. The PAL procedure supports the Static
357 Registers calling convention. It could be called at physical
358 mode and Virtual mode.
360 @param Index Index of PAL_CACHE_SHARED_INFO within the list
363 @param CacheLevel Unsigned 64-bit integer specifying the
364 level in the cache hierarchy for which
365 information is requested. This value must
366 be between 0 and one less than the value
367 returned in the cache_levels return value
368 from PAL_CACHE_SUMMARY.
370 @param CacheType Unsigned 64-bit integer with a value of 1
371 for instruction cache and 2 for data or
372 unified cache. All other values are
375 @param ProcNumber Unsigned 64-bit integer that specifies for
376 which logical processor information is
377 being requested. This input argument must
378 be zero for the first call to this
379 procedure and can be a maximum value of
380 one less than the number of logical
381 processors sharing this cache, which is
382 returned by the num_shared return value.
384 @return R9 Unsigned integer that returns the number of
385 logical processors that share the processor
386 cache level and type, for which information was
389 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
391 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
393 @return Status 0 - Call completed without error
395 @return Status -1 - Unimplemented procedure
397 @return Status -2 - Invalid argument
399 @return Status -3 - Call completed with error.
402 #define PAL_CACHE_SHARED_INFO 43
407 PAL Procedure - PAL_CACHE_SUMMARY.
409 Return a summary of the cache hierarchy. It is required by
410 IPF. The PAL procedure supports the Static Registers calling
411 convention. It could be called at physical mode and Virtual
414 @param Index Index of PAL_CACHE_SUMMARY within the list of
418 @return R9 CacheLevels Unsigned 64-bit integer denoting the
419 number of levels of cache
420 implemented by the processor.
421 Strictly, this is the number of
422 levels for which the cache
423 controller is integrated into the
424 processor (the cache SRAMs may be
425 external to the processor).
427 @return R10 UniqueCaches Unsigned 64-bit integer denoting the
428 number of unique caches implemented
429 by the processor. This has a maximum
430 of 2*cache_levels, but may be less
431 if any of the levels in the cache
432 hierarchy are unified caches or do
433 not have both instruction and data
436 @return Status 0 - Call completed without error
438 @return Status -2 - Invalid argument
440 @return Status -3 - Call completed with error.
443 #define PAL_CACHE_SUMMARY 4
447 // Virtual Memory Attributes implemented by processor.
449 #define PAL_MEMORY_ATTR_WB 0
450 #define PAL_MEMORY_ATTR_WC 6
451 #define PAL_MEMORY_ATTR_UC 4
452 #define PAL_MEMORY_ATTR_UCE 5
453 #define PAL_MEMORY_ATTR_NATPAGE 7
457 PAL Procedure - PAL_MEM_ATTRIB.
459 Return a list of supported memory attributes.. It is required
460 by IPF. The PAL procedure supports the Static Registers calling
461 convention. It could be called at physical mode and Virtual
464 @param Index Index of PAL_MEM_ATTRIB within the list of PAL
468 @return R9 Attributes 8-bit vector of memory attributes
469 implemented by processor. See Virtual
470 Memory Attributes above.
472 @return Status 0 - Call completed without error
474 @return Status -2 - Invalid argument
476 @return Status -3 - Call completed with error.
480 #define PAL_MEM_ATTRIB 5
484 PAL Procedure - PAL_PREFETCH_VISIBILITY.
486 Used in architected sequence to transition pages from a
487 cacheable, speculative attribute to an uncacheable attribute.
488 It is required by IPF. The PAL procedure supports the Static
489 Registers calling convention. It could be called at physical
490 mode and Virtual mode.
492 @param Index Index of PAL_PREFETCH_VISIBILITY within the list
495 @param TransitionType Unsigned integer specifying the type
496 of memory attribute transition that is
499 @return Status 1 Call completed without error; this
500 call is not necessary on remote
503 @return Status 0 - Call completed without error
505 @return Status -2 - Invalid argument
507 @return Status -3 - Call completed with error.
510 #define PAL_PREFETCH_VISIBILITY 41
514 PAL Procedure - PAL_PTCE_INFO.
516 Return information needed for ptc.e instruction to purge
517 entire TC. It is required by IPF. The PAL procedure supports
518 the Static Registers calling convention. It could be called at
519 physical mode and Virtual mode.
521 @param Index Index of PAL_PTCE_INFO within the list
524 @return R9 Unsigned 64-bit integer denoting the beginning
525 address to be used by the first PTCE instruction
528 @return R10 Two unsigned 32-bit integers denoting the loop
529 counts of the outer (loop 1) and inner (loop 2)
530 purge loops. count1 (loop 1) is contained in bits
531 63:32 of the parameter, and count2 (loop 2) is
532 contained in bits 31:0 of the parameter.
534 @return R11 Two unsigned 32-bit integers denoting the loop
535 strides of the outer (loop 1) and inner (loop 2)
536 purge loops. stride1 (loop 1) is contained in bits
537 63:32 of the parameter, and stride2 (loop 2) is
538 contained in bits 31:0 of the parameter.
540 @return Status 0 - Call completed without error
542 @return Status -2 - Invalid argument
544 @return Status -3 - Call completed with error.
547 #define PAL_PTCE_INFO 6
553 @param NumberSets Unsigned 8-bit integer denoting the number
554 of hash sets for the specified level
555 (1=fully associative)
557 @param NumberWays Unsigned 8-bit integer denoting the
558 associativity of the specified level
561 @param NumberEntries Unsigned 16-bit integer denoting the
562 number of entries in the specified TC.
565 @param PageSizeIsOptimized Flag denoting whether the
566 specified level is optimized for
567 the region's preferred page size
568 (1=optimized) tc_pages indicates
569 which page sizes are usable by
570 this translation cache.
572 @param TcIsUnified Flag denoting whether the specified TC is
575 @param EntriesReduction Flag denoting whether installed
576 translation registers will reduce
577 the number of entries within the
584 UINT64 NumberEntries
:16;
585 UINT64 PageSizeIsOptimized
:1;
586 UINT64 TcIsUnified
:1;
587 UINT64 EntriesReduction
:1;
592 PAL Procedure - PAL_VM_INFO.
594 Return detailed information about virtual memory features
595 supported in the processor. It is required by IPF. The PAL
596 procedure supports the Static Registers calling convention. It
597 could be called at physical mode and Virtual mode.
599 @param Index Index of PAL_VM_INFO within the list
602 @param TcLevel Unsigned 64-bit integer specifying the level
603 in the TLB hierarchy for which information is
604 required. This value must be between 0 and one
605 less than the value returned in the
606 vm_info_1.num_tc_levels return value from
609 @param TcType Unsigned 64-bit integer with a value of 1 for
610 instruction translation cache and 2 for data
611 or unified translation cache. All other values
614 @return R9 8-byte formatted value returning information
615 about the specified TC. See PAL_TC_INFO above.
617 @return R10 64-bit vector containing a bit for each page
618 size supported in the specified TC, where bit
619 position n indicates a page size of 2**n.
621 @return Status 0 - Call completed without error
623 @return Status -2 - Invalid argument
625 @return Status -3 - Call completed with error.
628 #define PAL_VM_INFO 7
633 PAL Procedure - PAL_VM_PAGE_SIZE.
635 Return virtual memory TC and hardware walker page sizes
636 supported in the processor. It is required by IPF. The PAL
637 procedure supports the Static Registers calling convention. It
638 could be called at physical mode and Virtual mode.
640 @param Index Index of PAL_VM_PAGE_SIZE within the list
644 @return R9 64-bit vector containing a bit for each
645 architected page size that is supported for
646 TLB insertions and region registers.
648 @return R10 64-bit vector containing a bit for each
649 architected page size supported for TLB purge
652 @return Status 0 - Call completed without error
654 @return Status -2 - Invalid argument
656 @return Status -3 - Call completed with error.
659 #define PAL_VM_PAGE_SIZE 34
663 @param WalkerPresent 1-bit flag indicating whether a hardware
664 TLB walker is implemented (1 = walker
667 @param WidthOfPhysicalAddress Unsigned 7-bit integer
668 denoting the number of bits of
669 physical address implemented.
671 @param WidthOfKey Unsigned 8-bit integer denoting the number
672 of bits mplemented in the PKR.key field.
674 @param MaxPkrIndex Unsigned 8-bit integer denoting the
675 maximum PKR index (number of PKRs-1).
677 @param HashTagId Unsigned 8-bit integer which uniquely
678 identifies the processor hash and tag
681 @param MaxDtrIndex Unsigned 8 bit integer denoting the
682 maximum data translation register index
683 (number of dtr entries - 1).
685 @param MaxItrIndex Unsigned 8 bit integer denoting the
686 maximum instruction translation register
687 index (number of itr entries - 1).
689 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the
690 number of unique TCs implemented.
694 @param NumberOfTcLevels Unsigned 8-bit integer denoting the
699 UINT64 WalkerPresent
:1;
700 UINT64 WidthOfPhysicalAddress
: 7;
702 UINT64 MaxPkrIndex
:8;
704 UINT64 MaxDtrIndex
:8;
705 UINT64 MaxItrIndex
:8;
706 UINT64 NumberOfUniqueTc
:8;
707 UINT64 NumberOfTcLevels
:8;
712 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting
713 is the total number of virtual
716 @param WidthOfRid Unsigned 8-bit integer denoting the number
717 of bits implemented in the RR.rid field.
719 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the
720 maximum number of concurrent outstanding
721 TLB purges allowed by the processor. A
722 value of 0 indicates one outstanding
723 purge allowed. A value of 216-1
724 indicates no limit on outstanding
725 purges. All other values indicate the
726 actual number of concurrent outstanding
731 UINT64 WidthOfVirtualAddress
:8;
733 UINT64 MaxPurgedTlbs
:16;
739 PAL Procedure - PAL_VM_SUMMARY.
741 Return summary information about virtual memory features
742 supported in the processor. It is required by IPF. The PAL
743 procedure supports the Static Registers calling convention. It
744 could be called at physical mode and Virtual mode.
746 @param Index Index of PAL_VM_SUMMARY within the list
750 @return R9 8-byte formatted value returning global virtual
751 memory information. See PAL_VM_INFO1 above.
753 @return R10 8-byte formatted value returning global virtual
754 memory information. See PAL_VM_INFO2 above.
756 @return Status 0 - Call completed without error
758 @return Status -2 - Invalid argument
760 @return Status -3 - Call completed with error.
763 #define PAL_VM_SUMMARY 8
767 // Bit mask of TR_valid flag.
769 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
770 #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
771 #define PAL_TR_DIRTY_IS_VALID BIT2
772 #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
777 PAL Procedure - PAL_VM_TR_READ.
779 Read contents of a translation register. It is required by
780 IPF. The PAL procedure supports the Stacked Register calling
781 convention. It could be called at physical mode.
783 @param Index Index of PAL_VM_TR_READ within the list
786 @param RegNumber Unsigned 64-bit number denoting which TR to
789 @param TrType Unsigned 64-bit number denoting whether to
790 read an ITR (0) or DTR (1). All other values
793 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
794 which translation data is returned.
796 @return R9 Formatted bit vector denoting which fields are
797 valid. See TR_valid above.
799 @return Status 0 - Call completed without error
801 @return Status -2 - Invalid argument
803 @return Status -3 - Call completed with error.
806 #define PAL_VM_TR_READ 261
812 // Bit Mask of Processor Bus Fesatures .
817 When 0, bus data errors are detected and single bit errors are
818 corrected. When 1, no error detection or correction is done.
821 #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
826 When 0, bus address errors are signalled on the bus. When 1,
827 no bus errors are signalled on the bus. If Disable Bus Address
828 Error Checking is 1, this bit is ignored.
831 #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
838 When 0, bus errors are detected, single bit errors are
839 corrected., and a CMCI or MCA is generated internally to the
840 processor. When 1, no bus address errors are detected or
844 #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
849 When 0, bus protocol errors (BINIT#) are signaled by the
850 processor on the bus. When 1, bus protocol errors (BINIT#) are
851 not signaled on the bus. If Disable Bus Initialization Event
852 Checking is 1, this bit is ignored.
855 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
860 When 0, bus protocol errors (BINIT#) are detected and sampled
861 and an MCA is generated internally to the processor. When 1,
862 the processor will ignore bus protocol error conditions
866 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
872 When 0, BERR# is signalled if a bus error is detected. When 1,
873 bus errors are not signalled on the bus.
876 #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
883 When 0, BERR# is signalled when internal processor requestor
884 initiated bus errors are detected. When 1, internal requester
885 bus errors are not signalled on the bus.
888 #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
893 When 0, the processor takes an MCA if BERR# is asserted. When
894 1, the processor ignores the BERR# signal.
897 #define PAL_BUS_DISABLE_ERROR_CHECK BIT56
902 When 0, the processor asserts BINIT# if it detects a parity
903 error on the signals which identify the transactions to which
904 this is a response. When 1, the processor ignores parity on
908 #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
913 When 0, the in-order transaction queue is limited only by the
914 number of hardware entries. When 1, the processor's in-order
915 transactions queue is limited to one entry.
918 #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
922 Enable a bus cache line replacement transaction when a cache
923 line in the exclusive state is replaced from the highest level
924 processor cache and is not present in the lower level processor
925 caches. When 0, no bus cache line replacement transaction will
926 be seen on the bus. When 1, bus cache line replacement
927 transactions will be seen on the bus when the above condition is
931 #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
936 Enable a bus cache line replacement transaction when a cache
937 line in the shared or exclusive state is replaced from the
938 highest level processor cache and is not present in the lower
939 level processor caches.
940 When 0, no bus cache line replacement transaction will be seen
941 on the bus. When 1, bus cache line replacement transactions
942 will be seen on the bus when the above condition is detected.
945 #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
951 When 0, the data bus is configured at the 2x data transfer
952 rate.When 1, the data bus is configured at the 1x data
953 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
954 processor executes locked transactions atomically. When 1, the
955 processor masks the bus lock signal and executes locked
956 transactions as a non-atomic series of transactions.
959 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
963 When 0, the processor will deassert bus request when finished
964 with each transaction. When 1, the processor will continue to
965 assert bus request after it has finished, if it was the last
966 agent to own the bus and if there are no other pending
970 #define PAL_BUS_REQUEST_BUS_PARKING BIT29
975 PAL Procedure - PAL_BUS_GET_FEATURES.
977 Return configurable processor bus interface features and their
978 current settings. It is required by IPF. The PAL procedure
979 supports the Stacked Register calling convention. It could be
980 called at physical mode.
982 @param Index Index of PAL_BUS_GET_FEATURES within the list
985 @return R9 64-bit vector of features implemented.
986 (1=implemented, 0=not implemented)
988 @return R10 64-bit vector of current feature settings.
990 @return R11 64-bit vector of features controllable by
991 software. (1=controllable, 0= not controllable)
993 @return Status 0 - Call completed without error
995 @return Status -2 - Invalid argument
997 @return Status -3 - Call completed with error.
1000 #define PAL_BUS_GET_FEATURES 9
1004 PAL Procedure - PAL_BUS_SET_FEATURES.
1006 Enable or disable configurable features in processor bus
1007 interface. It is required by IPF. It is required by IPF. The PAL procedure
1008 supports the Static Registers calling convention. It could be
1009 called at physical mode.
1011 @param Index Index of PAL_BUS_SET_FEATURES within the list
1014 @param FeatureSelect 64-bit vector denoting desired state of
1015 each feature (1=select, 0=non-select).
1017 @return Status 0 - Call completed without error
1019 @return Status -2 - Invalid argument
1021 @return Status -3 - Call completed with error.
1024 #define PAL_BUS_SET_FEATURES 10
1029 PAL Procedure - PAL_DEBUG_INFO.
1031 Return the number of instruction and data breakpoint
1032 registers. It is required by IPF. It is required by IPF. The
1033 PAL procedure supports the Static Registers calling
1034 convention. It could be called at physical mode and virtual
1037 @param Index Index of PAL_DEBUG_INFO within the list of PAL
1040 @return R9 Unsigned 64-bit integer denoting the number of
1041 pairs of instruction debug registers implemented
1044 @return R10 Unsigned 64-bit integer denoting the number of
1045 pairs of data debug registers implemented by the
1048 @return Status 0 - Call completed without error
1050 @return Status -2 - Invalid argument
1052 @return Status -3 - Call completed with error.
1055 #define PAL_DEBUG_INFO 11
1059 PAL Procedure - PAL_FIXED_ADDR.
1061 Return the fixed component of a processor¡¯s directed address.
1062 It is required by IPF. It is required by IPF. The PAL
1063 procedure supports the Static Registers calling convention. It
1064 could be called at physical mode and virtual mode.
1066 @param Index Index of PAL_FIXED_ADDR within the list of PAL
1069 @return R9 Fixed geographical address of this processor.
1072 @return Status 0 - Call completed without error
1074 @return Status -2 - Invalid argument
1076 @return Status -3 - Call completed with error.
1079 #define PAL_FIXED_ADDR 12
1083 PAL Procedure - PAL_FREQ_BASE.
1085 Return the frequency of the output clock for use by the
1086 platform, if generated by the processor. It is optinal. The
1087 PAL procedure supports the Static Registers calling
1088 convention. It could be called at physical mode and virtual
1091 @param Index Index of PAL_FREQ_BASE within the list of PAL
1094 @return R9 Base frequency of the platform if generated by the
1098 @return Status 0 - Call completed without error
1100 @return Status -1 - Unimplemented procedure
1102 @return Status -2 - Invalid argument
1104 @return Status -3 - Call completed with error.
1107 #define PAL_FREQ_BASE 13
1112 PAL Procedure - PAL_FREQ_RATIOS.
1114 Return ratio of processor, bus, and interval time counter to
1115 processor input clock or output clock for platform use, if
1116 generated by the processor. It is required by IPF. The PAL
1117 procedure supports the Static Registers calling convention. It
1118 could be called at physical mode and virtual mode.
1120 @param Index Index of PAL_FREQ_RATIOS within the list of PAL
1123 @return R9 Ratio of the processor frequency to the input
1124 clock of the processor, if the platform clock is
1125 generated externally or to the output clock to the
1126 platform, if the platform clock is generated by
1129 @return R10 Ratio of the bus frequency to the input clock of
1130 the processor, if the platform clock is generated
1131 externally or to the output clock to the platform,
1132 if the platform clock is generated by the
1135 @return R11 Ratio of the interval timer counter rate to input
1136 clock of the processor, if the platform clock is
1137 generated externally or to the output clock to the
1138 platform, if the platform clock is generated by
1141 @return Status 0 - Call completed without error
1143 @return Status -2 - Invalid argument
1145 @return Status -3 - Call completed with error.
1148 #define PAL_FREQ_RATIOS 14
1152 @param NumberOfLogicalProcessors Total number of logical
1153 processors on this physical
1154 processor package that are
1157 @param ThreadsPerCore Number of threads per core.
1159 @param CoresPerProcessor Total number of cores on this
1160 physical processor package.
1162 @param PhysicalProcessorPackageId Physical processor package
1163 identifier which was
1164 assigned at reset by the
1166 controller. This value may
1167 or may not be unique
1168 across the entire platform
1169 since it depends on the
1170 platform vendor's policy.
1173 UINT64 NumberOfLogicalProcessors
:16;
1174 UINT64 ThreadsPerCore
:8;
1176 UINT64 CoresPerProcessor
;
1178 UINT64 PhysicalProcessorPackageId
:8;
1180 } PAL_LOGICAL_PROCESSPR_OVERVIEW
;
1184 @param ThreadId The thread identifier of the logical
1185 processor for which information is being
1186 returned. This value will be unique on a per
1189 @param CoreId The core identifier of the logical processor
1190 for which information is being returned.
1191 This value will be unique on a per physical
1192 processor package basis.
1197 UINT64 Reserved1
:16;
1199 UINT64 Reserved2
:16;
1200 } PAL_LOGICAL_PROCESSORN_INFO1
;
1205 @param LogicalAddress Geographical address of the logical
1206 processor for which information is being
1207 returned. This is the same value that is
1208 returned by the PAL_FIXED_ADDR procedure
1209 when it is called on the logical
1215 UINT64 LogicalAddress
:16;
1217 } PAL_LOGICAL_PROCESSORN_INFO2
;
1221 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
1223 Return information on which logical processors map to a
1224 physical processor die. It is optinal. The PAL procedure
1225 supports the Static Registers calling convention. It could be
1226 called at physical mode and virtual mode.
1228 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
1231 @param ProcessorNumber Signed 64-bit integer that specifies
1232 for which logical processor
1233 information is being requested. When
1234 this input argument is -1, information
1235 is returned about the logical
1236 processor on which the procedure call
1237 is made. This input argument must be
1238 in the range of 1 up to one less than
1239 the number of logical processors
1240 returned by num_log in the
1241 log_overview return value.
1244 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
1246 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
1248 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
1251 @return Status 0 - Call completed without error
1253 @return Status -1 - Unimplemented procedure
1255 @return Status -2 - Invalid argument
1257 @return Status -3 - Call completed with error.
1260 #define PAL_LOGICAL_TO_PHYSICAL 42
1265 @param NumberOfPmcPairs Unsigned 8-bit number defining the
1266 number of generic PMC/PMD pairs.
1268 @param WidthOfCounter Unsigned 8-bit number in the range
1269 0:60 defining the number of
1270 implemented counter bits.
1272 @param TypeOfCycleCounting Unsigned 8-bit number defining the
1273 event type for counting processor
1277 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
1279 event type for retired
1280 instruction bundles.
1284 UINT64 NumberOfPmcPairs
:8;
1285 UINT64 WidthOfCounter
:8;
1286 UINT64 TypeOfCycleCounting
:8;
1287 UINT64 TypeOfRetiredInstructionBundle
:8;
1289 } PAL_PERFORMANCE_INFO
;
1293 PAL Procedure - PAL_PERF_MON_INFO.
1295 Return the number and type of performance monitors. It is
1296 required by IPF. The PAL procedure supports the Static
1297 Registers calling convention. It could be called at physical
1298 mode and virtual mode.
1300 @param Index Index of PAL_PERF_MON_INFO within the list of
1303 @param PerformanceBuffer An address to an 8-byte aligned
1304 128-byte memory buffer.
1307 @return R9 Information about the performance monitors
1308 implemented. See PAL_PERFORMANCE_INFO;
1310 @return Status 0 - Call completed without error
1312 @return Status -2 - Invalid argument
1314 @return Status -3 - Call completed with error.
1317 #define PAL_PERF_MON_INFO 15
1321 PAL Procedure - PAL_PLATFORM_ADDR.
1323 Specify processor interrupt block address and I/O port space
1324 address. It is required by IPF. The PAL procedure supports the
1325 Static Registers calling convention. It could be called at
1326 physical mode and virtual mode.
1328 @param Index Index of PAL_PLATFORM_ADDR within the list of
1331 @param Type Unsigned 64-bit integer specifying the type of
1332 block. 0 indicates that the processor interrupt
1333 block pointer should be initialized. 1 indicates
1334 that the processor I/O block pointer should be
1337 @param Address Unsigned 64-bit integer specifying the address
1338 to which the processor I/O block or interrupt
1339 block shall be set. The address must specify
1340 an implemented physical address on the
1341 processor model, bit 63 is ignored.
1344 @return Status 0 - Call completed without error
1346 @return Status -1 - Unimplemented procedure.
1348 @return Status -2 - Invalid argument
1350 @return Status -3 - Call completed with error.
1353 #define PAL_PLATFORM_ADDR 16
1358 @param EnableBerrPromotion Bit63. Enable BERR promotion. When
1359 1, the Bus Error (BERR) signal is
1360 promoted to the Bus Initialization
1361 (BINIT) signal, and the BINIT pin
1362 is asserted on the occurrence of
1363 each Bus Error. Setting this bit
1364 has no effect if BINIT signalling
1366 PAL_BUS_GET/SET_FEATURES)
1368 @param EnableMcaPromotion Bit62, Enable MCA promotion. When
1369 1, machine check aborts (MCAs) are
1370 promoted to the Bus Error signal,
1371 and the BERR pin is assert on each
1372 occurrence of an MCA. Setting this
1373 bit has no effect if BERR
1374 signalling is disabled. (See
1375 PAL_BUS_GET/SET_FEATURES)
1377 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
1378 promotion. When 1, machine
1379 check aborts (MCAs) are
1381 Initialization signal, and
1382 the BINIT pin is assert on
1383 each occurrence of an MCA.
1384 Setting this bit has no
1385 effect if BINIT signalling
1387 PAL_BUS_GET/SET_FEATURES)
1389 @param EnableCmciPromotion Bit60, Enable CMCI promotion When
1390 1, Corrected Machine Check
1391 Interrupts (CMCI) are promoted to
1392 MCAs. They are also further
1393 promoted to BERR if bit 39, Enable
1394 MCA promotion, is also set and
1395 they are promoted to BINIT if bit
1396 38, Enable MCA to BINIT promotion,
1397 is also set. This bit has no
1398 effect if MCA signalling is
1400 PAL_BUS_GET/SET_FEATURES)
1402 @param DisableCache Bit59, Disable Cache. When 0, the
1403 processor performs cast outs on
1404 cacheable pages and issues and responds
1405 to coherency requests normally. When 1,
1406 the processor performs a memory access
1407 for each reference regardless of cache
1408 contents and issues no coherence
1409 requests and responds as if the line
1410 were not present. Cache contents cannot
1411 be relied upon when the cache is
1412 disabled. WARNING: Semaphore
1413 instructions may not be atomic or may
1414 cause Unsupported Data Reference faults
1415 if caches are disabled.
1417 @param DisableCoherency Bit58, Disable Coherency. When 0,
1418 the processor uses normal coherency
1419 requests and responses. When 1, the
1420 processor answers all requests as if
1421 the line were not present.
1423 @param DisableDPM Bit57, Disable Dynamic Power Management
1424 (DPM). When 0, the hardware may reduce
1425 power consumption by removing the clock
1426 input from idle functional units. When 1,
1427 all functional units will receive clock
1428 input, even when idle.
1430 @param DisableBinitWithTimeout Bit56, Disable a BINIT on
1431 internal processor time-out.
1432 When 0, the processor may
1433 generate a BINIT on an
1434 internal processor time-out.
1435 When 1, the processor will not
1436 generate a BINIT on an
1437 internal processor time-out.
1438 The event is silently ignored.
1441 @param EnableEnvNotification Bit55, Enable external
1442 notification when the processor
1443 detects hardware errors caused
1444 by environmental factors that
1446 deterministic behavior of the
1447 processor. When 1, this bit will
1448 enable external notification,
1449 when 0 external notification is
1450 not provided. The type of
1451 external notification of these
1452 errors is processor-dependent. A
1453 loss of processor deterministic
1454 behavior is considered to have
1456 environmentally induced errors
1457 cause the processor to deviate
1458 from its normal execution and
1459 eventually causes different
1460 behavior which can be observed
1461 at the processor bus pins.
1462 Processor errors that do not
1463 have this effects (i.e.,
1464 software induced machine checks)
1465 may or may not be promoted
1466 depending on the processor
1469 @param EnableVmsw Bit54, Enable the use of the vmsw
1470 instruction. When 0, the vmsw instruction
1471 causes a Virtualization fault when
1472 executed at the most privileged level.
1473 When 1, this bit will enable normal
1474 operation of the vmsw instruction.
1476 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
1477 on data-poisoning event
1478 detection. When 0, a CMCI
1479 will be signaled on error
1480 detection. When 1, an MCA
1481 will be signaled on error
1482 detection. If this feature
1483 is not supported, then the
1484 corresponding argument is
1485 ignored when calling
1486 PAL_PROC_SET_FEATURES. Note
1487 that the functionality of
1488 this bit is independent of
1489 the setting in bit 60
1490 (Enable CMCI promotion), and
1491 that the bit 60 setting does
1492 not affect CMCI signaling
1493 for data-poisoning related
1494 events. Volume 2: Processor
1495 Abstraction Layer 2:431
1496 PAL_PROC_GET_FEATURES
1498 @param DisablePState Bit52, Disable P-states. When 1, the PAL
1499 P-state procedures (PAL_PSTATE_INFO,
1500 PAL_SET_PSTATE, PAL_GET_PSTATE) will
1501 return with a status of -1
1502 (Unimplemented procedure).
1504 @param DisableBranchPrediction Bit47, Disable Dynamic branch
1505 prediction. When 0, the
1506 processor may predict branch
1507 targets and speculatively
1508 execute, but may not commit
1509 results. When 1, the processor
1510 must wait until branch targets
1511 are known to execute.
1513 @param DisableDynamicInsCachePrefetch Bit46, Disable
1514 DynamicInstruction Cache
1515 Prefetch. When 0, the
1516 processor may prefetch
1518 instruction which has
1519 not been executed, but
1522 instructions may not be
1523 fetched until needed or
1524 hinted for execution.
1525 (Prefetch for a hinted
1526 branch is allowed even
1527 when dynamic instruction
1531 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
1532 Data Cache Prefetch.
1533 When 0, the processor
1534 may prefetch into the
1535 caches any data which
1536 has not been accessed
1538 execution, but which
1540 accessed. When 1, no
1542 until it is needed for
1543 instruction execution
1547 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous
1548 Deferral. When 1, the
1549 processor may optionally
1550 defer speculative loads
1551 that do not encounter any
1552 exception conditions, but
1554 implementation-dependent
1555 conditions (e.g., cache
1556 miss). When 0, spontaneous
1557 deferral is disabled.
1559 @param DisableDynamicPrediction Bit43, Disable Dynamic
1560 Predicate Prediction. When
1561 0, the processor may predict
1562 predicate results and
1563 execute speculatively, but
1564 may not commit results until
1565 the actual predicates are
1566 known. When 1, the processor
1567 shall not execute predicated
1568 instructions until the
1569 actual predicates are known.
1571 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
1572 Denotes whether XR1 XR3 are
1573 implemented for machine check
1574 recovery. This feature may only be
1575 interrogated by PAL_PROC_GET_FEATURES.
1576 It may not be enabled or disabled by
1577 PAL_PROC_SET_FEATURES. The
1578 corresponding argument is ignored.
1580 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
1581 implemented. Denotes whether XIP, XPSR,
1582 and XFS are implemented for machine
1583 check recovery. This feature may only be
1584 interrogated by PAL_PROC_GET_FEATURES.
1585 It may not be enabled or disabled by
1586 PAL_PROC_SET_FEATURES. The corresponding
1587 argument is ignored.
1589 @param NoVM Bit40, No Virtual Machine features implemented.
1590 Denotes whether PSR.vm is implemented. This
1591 feature may only be interrogated by
1592 PAL_PROC_GET_FEATURES. It may not be enabled or
1593 disabled by PAL_PROC_SET_FEATURES. The
1594 corresponding argument is ignored.
1596 @param NoVariablePState Bit39, No Variable P-state
1597 performance: A value of 1, indicates
1598 that a processor implements
1599 techniques to optimize performance
1600 for the given P-state power budget
1601 by dynamically varying the
1602 frequency, such that maximum
1603 performance is achieved for the
1604 power budget. A value of 0,
1605 indicates that P-states have no
1606 frequency variation or very small
1607 frequency variations for their given
1608 power budget. This feature may only
1610 PAL_PROC_GET_FEATURES. it may not be
1611 enabled or disabled by
1612 PAL_PROC_SET_FEATURES. The
1613 corresponding argument is ignored.
1616 @param NoSimpleImpInUndefinedIns Bit38, No Simple
1618 unimplemented instruction
1619 addresses. Denotes how an
1620 unimplemented instruction
1621 address is recorded in IIP
1623 Instruction Address trap or
1624 fault. When 1, the full
1625 unimplemented address is
1626 recorded in IIP; when 0, the
1627 address is sign extended
1628 (virtual addresses) or zero
1630 addresses). This feature may
1631 only be interrogated by
1632 PAL_PROC_GET_FEATURES. It
1633 may not be enabled or
1635 PAL_PROC_SET_FEATURES. The
1636 corresponding argument is
1639 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
1640 present. Denotes the absence of INIT,
1641 PMI, LINT0 and LINT1 pins on the
1642 processor. When 1, the pins are absent.
1643 When 0, the pins are present. This
1644 feature may only be interrogated by
1645 PAL_PROC_GET_FEATURES. It may not be
1646 enabled or disabled by
1647 PAL_PROC_SET_FEATURES. The corresponding
1648 argument is ignored.
1650 @param FaultInUndefinedIns Bit36, No Unimplemented
1651 instruction address reported as
1652 fault. Denotes how the processor
1653 reports the detection of
1654 unimplemented instruction
1655 addresses. When 1, the processor
1656 reports an Unimplemented
1657 Instruction Address fault on the
1658 unimplemented address; when 0, it
1659 reports an Unimplemented
1660 Instruction Address trap on the
1661 previous instruction in program
1662 order. This feature may only be
1664 PAL_PROC_GET_FEATURES. It may not
1665 be enabled or disabled by
1666 PAL_PROC_SET_FEATURES. The
1667 corresponding argument is
1672 UINT64 Reserved1
:36;
1673 UINT64 FaultInUndefinedIns
:1;
1674 UINT64 NoPresentPmi
:1;
1675 UINT64 NoSimpleImpInUndefinedIns
:1;
1676 UINT64 NoVariablePState
:1;
1678 UINT64 NoXipXpsrXfs
:1;
1679 UINT64 NoXr1ThroughXr3
:1;
1680 UINT64 DisableDynamicPrediction
:1;
1681 UINT64 DisableSpontaneousDeferral
:1;
1682 UINT64 DisableDynamicDataCachePrefetch
:1;
1683 UINT64 DisableDynamicInsCachePrefetch
:1;
1684 UINT64 DisableBranchPrediction
:1;
1686 UINT64 DisablePState
:1;
1687 UINT64 EnableMcaOnDataPoisoning
:1;
1688 UINT64 EnableVmsw
:1;
1689 UINT64 EnableEnvNotification
:1;
1690 UINT64 DisableBinitWithTimeout
:1;
1691 UINT64 DisableDPM
:1;
1692 UINT64 DisableCoherency
:1;
1693 UINT64 DisableCache
:1;
1694 UINT64 EnableCmciPromotion
:1;
1695 UINT64 EnableMcaToBinitPromotion
:1;
1696 UINT64 EnableMcaPromotion
:1;
1697 UINT64 EnableBerrPromotion
:1;
1698 } PAL_PROCESSOR_FEATURES
;
1702 PAL Procedure - PAL_PROC_GET_FEATURES.
1704 Return configurable processor features and their current
1705 setting. It is required by IPF. The PAL procedure supports the
1706 Static Registers calling convention. It could be called at
1707 physical mode and virtual mode.
1709 @param Index Index of PAL_PROC_GET_FEATURES within the list of
1712 @param Reserved Reserved parameter.
1714 @param FeatureSet Feature set information is being requested
1718 @return R9 64-bit vector of features implemented. See
1719 PAL_PROCESSOR_FEATURES.
1721 @return R10 64-bit vector of current feature settings. See
1722 PAL_PROCESSOR_FEATURES.
1724 @return R11 64-bit vector of features controllable by
1727 @return Status 1 - Call completed without error; The
1728 feature_set passed is not supported but a
1729 feature_set of a larger value is supported.
1731 @return Status 0 - Call completed without error
1733 @return Status -2 - Invalid argument
1735 @return Status -3 - Call completed with error.
1737 @return Status -8 - feature_set passed is beyond the maximum
1738 feature_set supported
1741 #define PAL_PROC_GET_FEATURES 17
1746 PAL Procedure - PAL_PROC_SET_FEATURES.
1748 Enable or disable configurable processor features. It is
1749 required by IPF. The PAL procedure supports the Static
1750 Registers calling convention. It could be called at physical
1753 @param Index Index of PAL_PROC_SET_FEATURES within the list of
1756 @param FeatureSelect 64-bit vector denoting desired state of
1757 each feature (1=select, 0=non-select).
1759 @param FeatureSet Feature set to apply changes to. See
1760 PAL_PROC_GET_FEATURES for more information
1765 @return Status 1 - Call completed without error; The
1766 feature_set passed is not supported but a
1767 feature_set of a larger value is supported
1769 @return Status 0 - Call completed without error
1771 @return Status -2 - Invalid argument
1773 @return Status -3 - Call completed with error.
1775 @return Status -8 - feature_set passed is beyond the maximum
1776 feature_set supported
1779 #define PAL_PROC_SET_FEATURES 18
1783 // Value of PAL_REGISTER_INFO.InfoRequest.
1785 #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
1786 #define PAL_APPLICATION_REGISTER_READABLE 1
1787 #define PAL_CONTROL_REGISTER_IMPLEMENTED 2
1788 #define PAL_CONTROL_REGISTER_READABLE 3
1793 PAL Procedure - PAL_REGISTER_INFO.
1795 Return AR and CR register information. It is required by IPF.
1796 The PAL procedure supports the Static Registers calling
1797 convention. It could be called at physical mode and virtual
1800 @param Index Index of PAL_REGISTER_INFO within the list of
1803 @param InfoRequest Unsigned 64-bit integer denoting what
1804 register information is requested. See
1805 PAL_REGISTER_INFO.InfoRequest above.
1807 @return R9 64-bit vector denoting information for registers
1808 0-63. Bit 0 is register 0, bit 63 is register 63.
1810 @return R10 64-bit vector denoting information for registers
1811 64-127. Bit 0 is register 64, bit 63 is register
1815 @return Status 0 - Call completed without error
1817 @return Status -2 - Invalid argument
1819 @return Status -3 - Call completed with error.
1823 #define PAL_REGISTER_INFO 39
1827 PAL Procedure - PAL_RSE_INFO.
1829 Return RSE information. It is required by IPF. The PAL
1830 procedure supports the Static Registers calling convention. It
1831 could be called at physical mode and virtual mode.
1833 @param Index Index of PAL_RSE_INFO within the list of
1836 @param InfoRequest Unsigned 64-bit integer denoting what
1837 register information is requested. See
1838 PAL_REGISTER_INFO.InfoRequest above.
1840 @return R9 Number of physical stacked general registers.
1842 @return R10 RSE hints supported by processor.
1844 @return Status 0 - Call completed without error
1846 @return Status -2 - Invalid argument
1848 @return Status -3 - Call completed with error.
1852 #define PAL_RSE_INFO 19
1856 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1857 number that provides identification
1858 information about the PAL_B firmware.
1860 @param PalVendor Is an unsigned 8-bit integer indicating the
1861 vendor of the PAL code.
1863 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1864 number that provides identification
1865 information about the PAL_A firmware. In
1866 the split PAL_A model, this return value
1867 is the version number of the
1868 processor-specific PAL_A. The generic
1869 PAL_A version is not returned by this
1870 procedure in the split PAL_A model.
1874 UINT64 VersionOfPalB
:16;
1877 UINT64 VersionOfPalA
:16;
1878 UINT64 Reserved2
:16;
1883 PAL Procedure - PAL_VERSION.
1885 Return version of PAL code. It is required by IPF. The PAL
1886 procedure supports the Static Registers calling convention. It
1887 could be called at physical mode and virtual mode.
1889 @param Index Index of PAL_VERSION within the list of
1892 @param InfoRequest Unsigned 64-bit integer denoting what
1893 register information is requested. See
1894 PAL_REGISTER_INFO.InfoRequest above.
1896 @return R9 8-byte formatted value returning the minimum PAL
1897 version needed for proper operation of the
1898 processor. See PAL_VERSION_INFO above.
1900 @return R10 8-byte formatted value returning the current PAL
1901 version running on the processor. See
1902 PAL_VERSION_INFO above.
1904 @return Status 0 - Call completed without error
1906 @return Status -2 - Invalid argument
1908 @return Status -3 - Call completed with error.
1912 #define PAL_VERSION 20
1917 // Vectors of PAL_MC_CLEAR_LOG.pending
1919 #define PAL_MC_PENDING BIT0
1920 #define PAL_INIT_PENDING BIT1
1924 PAL Procedure - PAL_MC_CLEAR_LOG.
1926 Clear all error information from processor error logging
1927 registers. It is required by IPF. The PAL procedure supports
1928 the Static Registers calling convention. It could be called at
1929 physical mode and virtual mode.
1931 @param Index Index of PAL_MC_CLEAR_LOG within the list of
1935 @return R9 64-bit vector denoting whether an event is
1936 pending. See PAL_MC_CLEAR_LOG.pending above.
1939 @return Status 0 - Call completed without error
1941 @return Status -2 - Invalid argument
1943 @return Status -3 - Call completed with error.
1947 #define PAL_MC_CLEAR_LOG 21
1951 PAL Procedure - PAL_MC_DRAIN.
1953 Ensure that all operations that could cause an MCA have
1954 completed. It is required by IPF. The PAL procedure supports
1955 the Static Registers calling convention. It could be called at
1956 physical mode and virtual mode.
1958 @param Index Index of PAL_MC_DRAIN within the list of PAL
1962 @return Status 0 - Call completed without error
1964 @return Status -2 - Invalid argument
1966 @return Status -3 - Call completed with error.
1970 #define PAL_MC_DRAIN 22
1975 PAL Procedure - PAL_MC_DYNAMIC_STATE.
1977 Return Processor Dynamic State for logging by SAL. It is
1978 optional. The PAL procedure supports the Static Registers
1979 calling convention. It could be called at physical mode.
1981 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
1984 @param Offset Offset of the next 8 bytes of Dynamic Processor
1985 State to return. (multiple of 8).
1987 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
1988 Processor State returned.
1990 @return R10 Next 8 bytes of Dynamic Processor State.
1992 @return Status 0 - Call completed without error
1994 @return Status -1 - Unimplemented procedure.
1996 @return Status -2 - Invalid argument
1998 @return Status -3 - Call completed with error.
2002 #define PAL_MC_DYNAMIC_STATE 24
2007 // Values of PAL_MC_ERROR_INFO.InfoIndex.
2009 #define PAL_PROCESSOR_ERROR_MAP 0
2010 #define PAL_PROCESSOR_STATE_PARAM 1
2011 #define PAL_STRUCTURE_SPECIFIC_ERROR 2
2015 @param CoreId Bit3:0, Processor core ID (default is 0 for
2016 processors with a single core)
2018 @param ThreadId Bit7:4, Logical thread ID (default is 0 for
2019 processors that execute a single thread)
2021 @param InfoOfInsCache Bit11:8, Error information is
2022 available for 1st, 2nd, 3rd, and 4th
2023 level instruction caches.
2025 @param InfoOfDataCache Bit15:12, Error information is
2026 available for 1st, 2nd, 3rd, and 4th
2027 level data/unified caches.
2029 @param InfoOfInsTlb Bit19:16 Error information is available
2030 for 1st, 2nd, 3rd, and 4th level
2033 @param InfoOfDataTlb Bit23:20, Error information is available
2034 for 1st, 2nd, 3rd, and 4th level
2037 @param InfoOfProcessorBus Bit27:24 Error information is
2038 available for the 1st, 2nd, 3rd,
2039 and 4th level processor bus
2042 @param InfoOfRegisterFile Bit31:28 Error information is
2043 available on register file
2046 @param InfoOfMicroArch Bit47:32, Error information is
2047 available on micro-architectural
2054 UINT64 InfoOfInsCache
:4;
2055 UINT64 InfoOfDataCache
:4;
2056 UINT64 InfoOfInsTlb
:4;
2057 UINT64 InfoOfDataTlb
:4;
2058 UINT64 InfoOfProcessorBus
:4;
2059 UINT64 InfoOfRegisterFile
:4;
2060 UINT64 InfoOfMicroArch
:4;
2062 } PAL_MC_ERROR_INFO_LEVEL_INDEX
;
2065 // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
2067 #define PAL_ERR_INFO_BY_LEVEL_INDEX 0
2068 #define PAL_ERR_INFO_TARGET_ADDRESS 1
2069 #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
2070 #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
2071 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
2075 @param Operation Bit3:0, Type of cache operation that caused
2076 the machine check: 0 - unknown or internal
2077 error 1 - load 2 - store 3 - instruction
2078 fetch or instruction prefetch 4 - data
2079 prefetch (both hardware and software) 5 -
2080 snoop (coherency check) 6 - cast out
2081 (explicit or implicit write-back of a cache
2082 line) 7 - move in (cache line fill)
2084 @param FailedCacheLevel Bit5:4 Level of cache where the
2085 error occurred. A value of 0
2086 indicates the first level of cache.
2088 @param FailedInDataPart Bit8, Failure located in the data
2089 part of the cache line.
2091 @param FailedInTagPart Bit9, Failure located in the tag part
2094 @param FailedInDataCache Bit10, Failure located in the data
2097 @param FailedInInsCache Bit11, Failure located in the
2101 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
2102 line is held shared. 2 - cache line is held
2103 exclusive. 3 - cache line is modified. All other
2104 values are reserved.
2106 @param MesiIsValid Bit15, The mesi field in the cache_check
2109 @param FailedWay Bit20:16, Failure located in the way of
2110 the cache indicated by this value.
2112 @param WayIndexIsValid Bit21, The way and index field in the
2113 cache_check parameter is valid.
2115 @param MultipleBitsError Bit23, A multiple-bit error was
2116 detected, and data was poisoned for
2117 the corresponding cache line during
2120 @param IndexOfCacheLineError Bit51:32, Index of the cache
2121 line where the error occurred.
2123 @param InstructionSet Bit54, Instruction set. If this value
2124 is set to zero, the instruction that
2125 generated the machine check was an
2126 Intel Itanium instruction. If this bit
2127 is set to one, the instruction that
2128 generated the machine check was IA-32
2131 @param InstructionSetIsValid Bit55, The is field in the
2132 cache_check parameter is valid.
2134 @param PrivilegeLevel Bit57:56, Privilege level. The
2135 privilege level of the instruction
2136 bundle responsible for generating the
2139 @param PrivilegeLevelIsValide Bit58, The pl field of the
2140 cache_check parameter is
2143 @param McCorrected Bit59, Machine check corrected: This bit
2144 is set to one to indicate that the machine
2145 check has been corrected.
2147 @param TargetAddressIsValid Bit60, Target address is valid:
2148 This bit is set to one to
2149 indicate that a valid target
2150 address has been logged.
2152 @param RequesterIdentifier Bit61, Requester identifier: This
2153 bit is set to one to indicate that
2154 a valid requester identifier has
2157 @param ResponserIdentifier Bit62, Responder identifier: This
2158 bit is set to one to indicate that
2159 a valid responder identifier has
2162 @param PreciseInsPointer Bit63, Precise instruction pointer.
2163 This bit is set to one to indicate
2164 that a valid precise instruction
2165 pointer has been logged.
2170 UINT64 FailedCacheLevel
:2;
2172 UINT64 FailedInDataPart
:1;
2173 UINT64 FailedInTagPart
:1;
2174 UINT64 FailedInDataCache
:1;
2175 UINT64 FailedInInsCache
:1;
2177 UINT64 MesiIsValid
:1;
2179 UINT64 WayIndexIsValid
:1;
2182 UINT64 MultipleBitsError
:1;
2184 UINT64 IndexOfCacheLineError
:20;
2186 UINT64 InstructionSet
:1;
2187 UINT64 InstructionSetIsValid
:1;
2189 UINT64 PrivilegeLevel
:2;
2190 UINT64 PrivilegeLevelIsValide
:1;
2192 UINT64 McCorrected
:1;
2194 UINT64 TargetAddressIsValid
:1;
2195 UINT64 RequesterIdentifier
:1;
2196 UINT64 ResponserIdentifier
:1;
2197 UINT64 PreciseInsPointer
:1;
2199 } PAL_CACHE_CHECK_INFO
;
2203 @param FailedSlot Bit7:0, Slot number of the translation
2204 register where the failure occurred.
2206 @param FailedSlotIsValid Bit8, The tr_slot field in the
2207 TLB_check parameter is valid.
2209 @param TlbLevel Bit11:10, The level of the TLB where the
2210 error occurred. A value of 0 indicates the
2213 @param FailedInDataTr Bit16, Error occurred in the data
2214 translation registers.
2216 @param FailedInInsTr Bit17, Error occurred in the instruction
2217 translation registers
2219 @param FailedInDataTc Bit18, Error occurred in data
2222 @param FailedInInsTc Bit19, Error occurred in the instruction
2225 @param FailedOperation Bit23:20, Type of cache operation that
2226 caused the machine check: 0 - unknown
2227 1 - TLB access due to load instruction
2228 2 - TLB access due to store
2229 instruction 3 - TLB access due to
2230 instruction fetch or instruction
2231 prefetch 4 - TLB access due to data
2232 prefetch (both hardware and software)
2233 5 - TLB shoot down access 6 - TLB
2234 probe instruction (probe, tpa) 7 -
2235 move in (VHPT fill) 8 - purge (insert
2236 operation that purges entries or a TLB
2237 purge instruction) All other values
2240 @param InstructionSet Bit54, Instruction set. If this value
2241 is set to zero, the instruction that
2242 generated the machine check was an
2243 Intel Itanium instruction. If this bit
2244 is set to one, the instruction that
2245 generated the machine check was IA-32
2248 @param InstructionSetIsValid Bit55, The is field in the
2249 TLB_check parameter is valid.
2251 @param PrivelegeLevel Bit57:56, Privilege level. The
2252 privilege level of the instruction
2253 bundle responsible for generating the
2256 @param PrivelegeLevelIsValid Bit58, The pl field of the
2257 TLB_check parameter is valid.
2259 @param McCorrected Bit59, Machine check corrected: This bit
2260 is set to one to indicate that the machine
2261 check has been corrected.
2263 @param TargetAddressIsValid Bit60, Target address is valid:
2264 This bit is set to one to
2265 indicate that a valid target
2266 address has been logged.
2268 @param RequesterIdentifier Bit61 Requester identifier: This
2269 bit is set to one to indicate that
2270 a valid requester identifier has
2273 @param ResponserIdentifier Bit62, Responder identifier: This
2274 bit is set to one to indicate that
2275 a valid responder identifier has
2278 @param PreciseInsPointer Bit63 Precise instruction pointer.
2279 This bit is set to one to indicate
2280 that a valid precise instruction
2281 pointer has been logged.
2284 UINT64 FailedSlot
:8;
2285 UINT64 FailedSlotIsValid
:1;
2286 UINT64 Reserved1
:1;
2288 UINT64 Reserved2
:4;
2289 UINT64 FailedInDataTr
:1;
2290 UINT64 FailedInInsTr
:1;
2291 UINT64 FailedInDataTc
:1;
2292 UINT64 FailedInInsTc
:1;
2293 UINT64 FailedOperation
:4;
2294 UINT64 Reserved3
:30;
2295 UINT64 InstructionSet
:1;
2296 UINT64 InstructionSetIsValid
:1;
2297 UINT64 PrivelegeLevel
:2;
2298 UINT64 PrivelegeLevelIsValid
:1;
2299 UINT64 McCorrected
:1;
2300 UINT64 TargetAddressIsValid
:1;
2301 UINT64 RequesterIdentifier
:1;
2302 UINT64 ResponserIdentifier
:1;
2303 UINT64 PreciseInsPointer
:1;
2304 } PAL_TLB_CHECK_INFO
;
2308 PAL Procedure - PAL_MC_ERROR_INFO.
2310 Return Processor Machine Check Information and Processor
2311 Static State for logging by SAL. It is required by IPF. The
2312 PAL procedure supports the Static Registers calling
2313 convention. It could be called at physical and virtual mode.
2315 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
2318 @param InfoIndex Unsigned 64-bit integer identifying the
2319 error information that is being requested.
2320 See PAL_MC_ERROR_INFO.InfoIndex.
2322 @param LevelIndex 8-byte formatted value identifying the
2323 structure to return error information
2324 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
2326 @param ErrorTypeIndex Unsigned 64-bit integer denoting the
2327 type of error information that is
2328 being requested for the structure
2329 identified in LevelIndex.
2332 @return R9 Error information returned. The format of this
2333 value is dependant on the input values passed.
2335 @return R10 If this value is zero, all the error information
2336 specified by err_type_index has been returned. If
2337 this value is one, more structure-specific error
2338 information is available and the caller needs to
2339 make this procedure call again with level_index
2340 unchanged and err_type_index, incremented.
2343 @return Status 0 - Call completed without error
2345 @return Status -2 - Invalid argument
2347 @return Status -3 - Call completed with error.
2349 @return Status -6 - Argument was valid, but no error
2350 information was available
2354 #define PAL_MC_ERROR_INFO 25
2358 PAL Procedure - PAL_MC_EXPECTED.
2360 Set/Reset Expected Machine Check Indicator. It is required by
2361 IPF. The PAL procedure supports the Static Registers calling
2362 convention. It could be called at physical mode.
2364 @param Index Index of PAL_MC_EXPECTED within the list of PAL
2367 @param Expected Unsigned integer with a value of 0 or 1 to
2368 set or reset the hardware resource
2369 PALE_CHECK examines for expected machine
2373 @return R9 Unsigned integer denoting whether a machine check
2374 was previously expected.
2377 @return Status 0 - Call completed without error
2379 @return Status -2 - Invalid argument
2381 @return Status -3 - Call completed with error.
2384 #define PAL_MC_EXPECTED 23
2388 PAL Procedure - PAL_MC_REGISTER_MEM.
2390 Register min-state save area with PAL for machine checks and
2391 inits. It is required by IPF. The PAL procedure supports the
2392 Static Registers calling convention. It could be called at
2395 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
2398 @param Address Physical address of the buffer to be
2399 registered with PAL.
2403 @return Status 0 - Call completed without error
2405 @return Status -2 - Invalid argument
2407 @return Status -3 - Call completed with error.
2410 #define PAL_MC_REGISTER_MEM 27
2414 PAL Procedure - PAL_MC_RESUME.
2416 Restore minimal architected state and return to interrupted
2417 process. It is required by IPF. The PAL procedure supports the
2418 Static Registers calling convention. It could be called at
2421 @param Index Index of PAL_MC_RESUME within the list of PAL
2424 @param SetCmci Unsigned 64 bit integer denoting whether to
2425 set the CMC interrupt. A value of 0 indicates
2426 not to set the interrupt, a value of 1
2427 indicated to set the interrupt, and all other
2428 values are reserved.
2430 @param SavePtr Physical address of min-state save area used
2431 to used to restore processor state.
2433 @param NewContext Unsigned 64-bit integer denoting whether
2434 the caller is returning to a new context.
2435 A value of 0 indicates the caller is
2436 returning to the interrupted context, a
2437 value of 1 indicates that the caller is
2438 returning to a new context.
2442 @return Status -2 - Invalid argument
2444 @return Status -3 - Call completed with error.
2447 #define PAL_MC_RESUME 26
2451 PAL Procedure - PAL_HALT.
2453 Enter the low-power HALT state or an implementation-dependent
2454 low-power state. It is optinal. The PAL procedure supports the
2455 Static Registers calling convention. It could be called at
2458 @param Index Index of PAL_HALT within the list of PAL
2461 @param HaltState Unsigned 64-bit integer denoting low power
2464 @param IoDetailPtr 8-byte aligned physical address pointer to
2465 information on the type of I/O
2466 (load/store) requested.
2469 @return R9 Value returned if a load instruction is requested
2470 in the io_detail_ptr
2473 @return Status 0 - Call completed without error
2475 @return Status -1 - Unimplemented procedure
2477 @return Status -2 - Invalid argument
2479 @return Status -3 - Call completed with error.
2487 PAL Procedure - PAL_HALT_INFO.
2489 Return the low power capabilities of the processor. It is
2490 required by IPF. The PAL procedure supports the
2491 Stacked Registers calling convention. It could be called at
2492 physical and virtual mode.
2494 @param Index Index of PAL_HALT_INFO within the list of PAL
2497 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
2498 on an 8-byte boundary.
2502 @return Status 0 - Call completed without error
2504 @return Status -2 - Invalid argument
2506 @return Status -3 - Call completed with error.
2509 #define PAL_HALT_INFO 257
2514 PAL Procedure - PAL_HALT_LIGHT.
2516 Enter the low power LIGHT HALT state. It is required by
2517 IPF. The PAL procedure supports the Static Registers calling
2518 convention. It could be called at physical and virtual mode.
2520 @param Index Index of PAL_HALT_LIGHT within the list of PAL
2524 @return Status 0 - Call completed without error
2526 @return Status -2 - Invalid argument
2528 @return Status -3 - Call completed with error.
2531 #define PAL_HALT_LIGHT 29
2535 PAL Procedure - PAL_CACHE_LINE_INIT.
2537 Initialize tags and data of a cache line for processor
2538 testing. It is required by IPF. The PAL procedure supports the
2539 Static Registers calling convention. It could be called at
2540 physical and virtual mode.
2542 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
2545 @param Address Unsigned 64-bit integer value denoting the
2546 physical address from which the physical page
2547 number is to be generated. The address must be
2548 an implemented physical address, bit 63 must
2551 @param DataValue 64-bit data value which is used to
2552 initialize the cache line.
2555 @return Status 0 - Call completed without error
2557 @return Status -2 - Invalid argument
2559 @return Status -3 - Call completed with error.
2562 #define PAL_CACHE_LINE_INIT 31
2566 PAL Procedure - PAL_CACHE_READ.
2568 Read tag and data of a cache line for diagnostic testing. It
2569 is optional. The PAL procedure supports the
2570 Satcked Registers calling convention. It could be called at
2573 @param Index Index of PAL_CACHE_READ within the list of PAL
2576 @param LineId 8-byte formatted value describing where in the
2577 cache to read the data.
2579 @param Address 64-bit 8-byte aligned physical address from
2580 which to read the data. The address must be an
2581 implemented physical address on the processor
2582 model with bit 63 set to zero.
2584 @return R9 Right-justified value returned from the cache
2587 @return R10 The number of bits returned in data.
2589 @return R11 The status of the cache line.
2593 @return Status 1 - The word at address was found in the
2594 cache, but the line was invalid.
2596 @return Status 0 - Call completed without error
2598 @return Status -2 - Invalid argument
2600 @return Status -3 - Call completed with error.
2602 @return Status -5 - The word at address was not found in the
2605 @return Status -7 - The operation requested is not supported
2606 for this cache_type and level.
2609 #define PAL_CACHE_READ 259
2614 Write tag and data of a cache for diagnostic testing. It is
2615 optional. The PAL procedure supports the Satcked Registers
2616 calling convention. It could be called at physical mode.
2618 @param Index Index of PAL_CACHE_WRITE within the list of PAL
2621 @param LineId 8-byte formatted value describing where in the
2622 cache to write the data.
2624 @param Address 64-bit 8-byte aligned physical address at
2625 which the data should be written. The address
2626 must be an implemented physical address on the
2627 processor model with bit 63 set to 0.
2629 @param Data Unsigned 64-bit integer value to write into
2630 the specified part of the cache.
2633 @return Status 0 - Call completed without error
2635 @return Status -2 - Invalid argument
2637 @return Status -3 - Call completed with error.
2640 @return Status -7 - The operation requested is not supported
2641 for this cache_type and level.
2644 #define PAL_CACHE_WRITE 260
2648 PAL Procedure - PAL_TEST_INFO.
2650 Returns alignment and size requirements needed for the memory
2651 buffer passed to the PAL_TEST_PROC procedure as well as
2652 information on self-test control words for the processor self
2653 tests. It is required by IPF. The PAL procedure supports the
2654 Static Registers calling convention. It could be called at
2657 @param Index Index of PAL_TEST_INFO within the list of PAL
2660 @param TestPhase Unsigned integer that specifies which phase
2661 of the processor self-test information is
2662 being requested on. A value of 0 indicates
2663 the phase two of the processor self-test and
2664 a value of 1 indicates phase one of the
2665 processor self-test. All other values are
2668 @return R9 Unsigned 64-bit integer denoting the number of
2669 bytes of main memory needed to perform the second
2670 phase of processor self-test.
2672 @return R10 Unsigned 64-bit integer denoting the alignment
2673 required for the memory buffer.
2675 @return R11 48-bit wide bit-field indicating if control of
2676 the processor self-tests is supported and which
2677 bits of the test_control field are defined for
2681 @return Status 0 - Call completed without error
2683 @return Status -2 - Invalid argument
2685 @return Status -3 - Call completed with error.
2689 #define PAL_TEST_INFO 37
2693 @param BufferSize Indicates the size in bytes of the memory
2694 buffer that is passed to this procedure.
2695 BufferSize must be greater than or equal in
2696 size to the bytes_needed return value from
2697 PAL_TEST_INFO, otherwise this procedure will
2698 return with an invalid argument return
2701 @param TestPhase Defines which phase of the processor
2702 self-tests are requested to be run. A value
2703 of zero indicates to run phase two of the
2704 processor self-tests. Phase two of the
2705 processor self-tests are ones that require
2706 external memory to execute correctly. A
2707 value of one indicates to run phase one of
2708 the processor self-tests. Phase one of the
2709 processor self-tests are tests run during
2710 PALE_RESET and do not depend on external
2711 memory to run correctly. When the caller
2712 requests to have phase one of the processor
2713 self-test run via this procedure call, a
2714 memory buffer may be needed to save and
2715 restore state as required by the PAL calling
2716 conventions. The procedure PAL_TEST_INFO
2717 informs the caller about the requirements of
2722 UINT64 BufferSize
:56;
2724 } PAL_TEST_INFO_INFO
;
2728 @param TestControl This is an ordered implementation-specific
2729 control word that allows the user control
2730 over the length and runtime of the
2731 processor self-tests. This control word is
2732 ordered from the longest running tests up
2733 to the shortest running tests with bit 0
2734 controlling the longest running test. PAL
2735 may not implement all 47-bits of the
2736 test_control word. PAL communicates if a
2737 bit provides control by placing a zero in
2738 that bit. If a bit provides no control,
2739 PAL will place a one in it. PAL will have
2740 two sets of test_control bits for the two
2741 phases of the processor self-test. PAL
2742 provides information about implemented
2743 test_control bits at the hand-off from PAL
2744 to SAL for the firmware recovery check.
2745 These test_control bits provide control
2746 for phase one of processor self-test. It
2747 also provides this information via the PAL
2748 procedure call PAL_TEST_INFO for both the
2749 phase one and phase two processor tests
2750 depending on which information the caller
2751 is requesting. PAL interprets these bits
2752 as input parameters on two occasions. The
2753 first time is when SAL passes control back
2754 to PAL after the firmware recovery check.
2755 The second time is when a call to
2756 PAL_TEST_PROC is made. When PAL interprets
2757 these bits it will only interpret
2758 implemented test_control bits and will
2759 ignore the values located in the
2760 unimplemented test_control bits. PAL
2761 interprets the implemented bits such that
2762 if a bit contains a zero, this indicates
2763 to run the test. If a bit contains a one,
2764 this indicates to PAL to skip the test. If
2765 the cs bit indicates that control is not
2766 available, the test_control bits will be
2767 ignored or generate an illegal argument in
2768 procedure calls if the caller sets these
2771 @param ControlSupport This bit defines if an implementation
2772 supports control of the PAL self-tests
2773 via the self-test control word. If
2774 this bit is 0, the implementation does
2775 not support control of the processor
2776 self-tests via the self-test control
2777 word. If this bit is 1, the
2778 implementation does support control of
2779 the processor self-tests via the
2780 self-test control word. If control is
2781 not supported, GR37 will be ignored at
2782 the hand-off between SAL and PAL after
2783 the firmware recovery check and the
2784 PAL procedures related to the
2785 processor self-tests may return
2786 illegal arguments if a user tries to
2787 use the self-test control features.
2791 UINT64 TestControl
:47;
2792 UINT64 ControlSupport
:1;
2794 } PAL_SELF_TEST_CONTROL
;
2798 @param Attributes Specifies the memory attributes that are
2799 allowed to be used with the memory buffer
2800 passed to this procedure. The attributes
2801 parameter is a vector where each bit
2802 represents one of the virtual memory
2803 attributes defined by the architecture.See
2804 MEMORY_AATRIBUTES. The caller is required
2805 to support the cacheable attribute for the
2806 memory buffer, otherwise an invalid
2807 argument will be returned.
2810 @param TestControl Is the self-test control word
2811 corresponding to the test_phase passed.
2812 This test_control directs the coverage and
2813 runtime of the processor self-tests
2814 specified by the test_phase input
2815 argument. Information on if this
2816 feature is implemented and the number of
2817 bits supported can be obtained by the
2818 PAL_TEST_INFO procedure call. If this
2819 feature is implemented by the processor,
2820 the caller can selectively skip parts of
2821 the processor self-test by setting
2822 test_control bits to a one. If a bit has a
2823 zero, this test will be run. The values in
2824 the unimplemented bits are ignored. If
2825 PAL_TEST_INFO indicated that the self-test
2826 control word is not implemented, this
2827 procedure will return with an invalid
2828 argument status if the caller sets any of
2829 the test_control bits. See
2830 PAL_SELF_TEST_CONTROL.
2833 UINT64 Attributes
:8;
2835 UINT64 TestControl
:48;
2840 PAL Procedure - PAL_TEST_PROC.
2842 Perform late processor self test. It is required by IPF. The
2843 PAL procedure supports the Static Registers calling
2844 convention. It could be called at physical mode.
2846 @param Index Index of PAL_TEST_PROC within the list of PAL
2849 @param TestAddress 64-bit physical address of main memory
2850 area to be used by processor self-test.
2851 The memory region passed must be
2852 cacheable, bit 63 must be zero.
2854 @param TestInfo Input argument specifying the size of the
2855 memory buffer passed and the phase of the
2856 processor self-test that should be run. See
2859 @param TestParam Input argument specifying the self-test
2860 control word and the allowable memory
2861 attributes that can be used with the memory
2862 buffer. See PAL_TEST_CONTROL.
2864 @return R9 Formatted 8-byte value denoting the state of the
2865 processor after self-test
2869 @return Status 1 - Call completed without error, but hardware
2870 failures occurred during self-test.
2872 @return Status 0 - Call completed without error
2874 @return Status -2 - Invalid argument
2876 @return Status -3 - Call completed with error.
2880 #define PAL_TEST_PROC 258
2884 @param NumberOfInterruptControllers Number of interrupt
2885 controllers currently
2886 enabled on the system.
2888 @param NumberOfProcessors Number of processors currently
2889 enabled on the system.
2893 UINT32 NumberOfInterruptControllers
;
2894 UINT32 NumberOfProcessors
;
2895 } PAL_PLATFORM_INFO
;
2899 PAL Procedure - PAL_COPY_INFO.
2901 Return information needed to relocate PAL procedures and PAL
2902 PMI code to memory. It is required by IPF. The PAL procedure
2903 supports the Static Registers calling convention. It could be
2904 called at physical mode.
2906 @param Index Index of PAL_COPY_INFO within the list of PAL
2909 @param CopyType Unsigned integer denoting type of procedures
2910 for which copy information is requested.
2912 @param PlatformInfo 8-byte formatted value describing the
2913 number of processors and the number of
2914 interrupt controllers currently enabled
2915 on the system. See PAL_PLATFORM_INFO.
2918 @param McaProcStateInfo Unsigned integer denoting the number
2919 of bytes that SAL needs for the
2920 min-state save area for each
2925 @return R9 Unsigned integer denoting the number of bytes of
2926 PAL information that must be copied to main
2929 @return R10 Unsigned integer denoting the starting alignment
2930 of the data to be copied.
2932 @return Status 0 - Call completed without error
2934 @return Status -2 - Invalid argument
2936 @return Status -3 - Call completed with error.
2940 #define PAL_COPY_INFO 30
2944 PAL Procedure - PAL_COPY_PAL.
2946 Relocate PAL procedures and PAL PMI code to memory. It is
2947 required by IPF. The PAL procedure supports the Stacked
2948 Registers calling convention. It could be called at physical
2951 @param Index Index of PAL_COPY_PAL within the list of PAL
2954 @param TargetAddress Physical address of a memory buffer to
2955 copy relocatable PAL procedures and PAL
2958 @param AllocSize Unsigned integer denoting the size of the
2959 buffer passed by SAL for the copy operation.
2962 @param CopyOption Unsigned integer indicating whether
2963 relocatable PAL code and PAL PMI code
2964 should be copied from firmware address
2965 space to main memory.
2968 @return R9 Unsigned integer denoting the offset of PAL_PROC
2969 in the relocatable segment copied.
2971 @return Status 0 - Call completed without error
2973 @return Status -2 - Invalid argument
2975 @return Status -3 - Call completed with error.
2979 #define PAL_COPY_PAL 256
2983 PAL Procedure - PAL_ENTER_IA_32_ENV.
2985 Enter IA-32 System environment. It is optional. The PAL
2986 procedure supports the Static Registers calling convention.
2987 It could be called at physical mode.
2989 Note: Since this is a special call, it does not follow the PAL
2990 static register calling convention. GR28 contains the index of
2991 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
2992 input arguments including GR29-GR31 are setup by SAL to values
2993 as required by the IA-32 operating system defined in Table
2994 11-67. The registers that are designated as preserved, scratch,
2995 input arguments and procedure return values by the static
2996 procedure calling convention are not followed by this call. For
2997 instance, GR5 and GR6 need not be preserved since these are
2998 regarded as scratch by the IA-32 operating system. Note: In an
2999 MP system, this call must be COMPLETED on the first CPU to enter
3000 the IA-32 System Environment (may or may not be the BSP) prior
3001 to being called on the remaining processors in the MP system.
3003 @param Index GR28 contains the index of the
3004 PAL_ENTER_IA_32_ENV call within the list of PAL
3008 @return Status The status is returned in GR4.
3009 -1 - Un-implemented procedure 0 JMPE detected
3012 0 - 1 SAL allocated buffer for IA-32 System
3013 Environment operation is too small
3015 2 - IA-32 Firmware Checksum Error
3017 3 - SAL allocated buffer for IA-32 System
3018 Environment operation is not properly aligned
3020 4 - Error in SAL MP Info Table
3022 5 - Error in SAL Memory Descriptor Table
3024 6 - Error in SAL System Table
3026 7 - Inconsistent IA-32 state
3028 8 - IA-32 Firmware Internal Error
3030 9 - IA-32 Soft Reset (Note: remaining register
3031 state is undefined for this termination
3034 10 - Machine Check Error
3036 11 - Error in SAL I/O Intercept Table
3038 12 - Processor exit due to other processor in
3039 MP system terminating the IA32 system
3040 environment. (Note: remaining register state
3041 is undefined for this termination reason.)
3043 13 - Itanium architecture-based state
3044 corruption by either SAL PMI handler or I/O
3045 Intercept callback function.
3049 #define PAL_ENTER_IA_32_ENV 33
3053 PAL Procedure - PAL_PMI_ENTRYPOINT.
3055 Register PMI memory entrypoints with processor. It is required
3056 by IPF. The PAL procedure supports the Stacked Registers
3057 calling convention. It could be called at physical mode.
3059 @param Index Index of PAL_PMI_ENTRYPOINT within the list of
3062 @param SalPmiEntry 256-byte aligned physical address of SAL
3063 PMI entrypoint in memory.
3066 @return Status 0 - Call completed without error
3068 @return Status -2 - Invalid argument
3070 @return Status -3 - Call completed with error.
3074 #define PAL_PMI_ENTRYPOINT 32
3079 The ASCII brand identification string will be copied to the
3080 address specified in the address input argument. The processor
3081 brand identification string is defined to be a maximum of 128
3082 characters long; 127 bytes will contain characters and the 128th
3083 byte is defined to be NULL (0). A processor may return less than
3084 the 127 ASCII characters as long as the string is null
3085 terminated. The string length will be placed in the brand_info
3089 #define PAL_BRAND_INFO_ID_REQUEST 0
3093 PAL Procedure - PAL_BRAND_INFO.
3095 Provides processor branding information. It is optional by
3096 IPF. The PAL procedure supports the Stacked Registers calling
3097 convention. It could be called at physical and Virtual mode.
3100 @param Index Index of PAL_BRAND_INFO within the list of PAL
3103 @param InfoRequest Unsigned 64-bit integer specifying the
3104 information that is being requested. (See
3105 PAL_BRAND_INFO_ID_REQUEST)
3107 @param Address Unsigned 64-bit integer specifying the
3108 address of the 128-byte block to which the
3109 processor brand string shall be written.
3112 @reture R9 Brand information returned. The format of this
3113 value is dependent on the input values passed.
3116 @return Status 0 - Call completed without error
3118 @return Status -1 - Unimplemented procedure
3120 @return Status -2 - Invalid argument
3122 @return Status -3 - Call completed with error.
3124 @return Status -6 - Input argument is not implemented.
3127 #define PAL_BRAND_INFO 274
3131 PAL Procedure - PAL_GET_HW_POLICY.
3133 Returns the current hardware resource sharing policy of the
3134 processor. It is optional by IPF. The PAL procedure supports
3135 the Static Registers calling convention. It could be called at
3136 physical and Virtual mode.
3139 @param Index Index of PAL_GET_HW_POLICY within the list of PAL
3142 @param ProcessorNumber Unsigned 64-bit integer that specifies
3143 for which logical processor
3144 information is being requested. This
3145 input argument must be zero for the
3146 first call to this procedure and can
3147 be a maximum value of one less than
3148 the number of logical processors
3149 impacted by the hardware resource
3150 sharing policy, which is returned by
3151 the R10 return value.
3154 @reture R9 Unsigned 64-bit integer representing the current
3155 hardware resource sharing policy.
3157 @return R10 Unsigned 64-bit integer that returns the number
3158 of logical processors impacted by the policy
3161 @return R11 Unsigned 64-bit integer containing the logical
3162 address of one of the logical processors
3163 impacted by policy modification.
3166 @return Status 0 - Call completed without error
3168 @return Status -1 - Unimplemented procedure
3170 @return Status -2 - Invalid argument
3172 @return Status -3 - Call completed with error.
3174 @return Status -9 - Call requires PAL memory buffer.
3177 #define PAL_GET_HW_POLICY 48
3181 // Value of PAL_SET_HW_POLICY.Policy
3183 #define PAL_SET_HW_POLICY_PERFORMANCE 0
3184 #define PAL_SET_HW_POLICY_FAIRNESS 1
3185 #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
3186 #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
3190 PAL Procedure - PAL_SET_HW_POLICY.
3192 Sets the current hardware resource sharing policy of the
3193 processor. It is optional by IPF. The PAL procedure supports
3194 the Static Registers calling convention. It could be called at
3195 physical and Virtual mode.
3198 @param Index Index of PAL_SET_HW_POLICY within the list of PAL
3201 @param Policy Unsigned 64-bit integer specifying the hardware
3202 resource sharing policy the caller is setting.
3203 See Value of PAL_SET_HW_POLICY.Policy above.
3206 @return Status 1 - Call completed successfully but could not
3207 change the hardware policy since a
3208 competing logical processor is set in
3209 exclusive high priority.
3211 @return Status 0 - Call completed without error
3213 @return Status -1 - Unimplemented procedure
3215 @return Status -2 - Invalid argument
3217 @return Status -3 - Call completed with error.
3219 @return Status -9 - Call requires PAL memory buffer.
3222 #define PAL_SET_HW_POLICY 49
3227 @param Mode Bit2:0, Indicates the mode of operation for this
3228 procedure: 0 - Query mode 1 ¨C Error inject mode
3229 (err_inj should also be specified) 2 - Cancel
3230 outstanding trigger. All other fields in
3231 PAL_MC_ERROR_TYPE_INFO,
3232 PAL_MC_ERROR_STRUCTURE_INFO and
3233 PAL_MC_ERROR_DATA_BUFFER are ignored. All other
3234 values are reserved.
3236 @param ErrorInjection Bit5:3, indicates the mode of error
3237 injection: 0 - Error inject only (no
3238 error consumption) 1 - Error inject
3239 and consume All other values are
3243 @param ErrorSeverity Bit7:6, indicates the severity desired
3244 for error injection/query. Definitions
3245 of the different error severity types
3246 0 - Corrected error 1 - Recoverable
3247 error 2 - Fatal error 3 - Reserved
3250 @param ErrorStructure Bit12:8, Indicates the structure
3251 identification for error
3252 injection/query: 0 - Any structure
3253 (cannot be used during query mode).
3254 When selected, the structure type used
3255 for error injection is determined by
3256 PAL. 1 - Cache 2 - TLB 3 - Register
3257 file 4 - Bus/System interconnect 5-15
3258 - Reserved 16-31 - Processor
3259 specific error injection
3260 capabilities.ErrorDataBuffer is used
3261 to specify error types. Please refer
3262 to the processor specific
3263 documentation for additional details.
3265 @param StructureHierarchy Bit15:13, Indicates the structure
3267 injection/query: 0 - Any level of
3268 hierarchy (cannot be used during
3269 query mode). When selected, the
3270 structure hierarchy used for error
3271 injection is determined by PAL. 1
3272 - Error structure hierarchy
3273 level-1 2 - Error structure
3274 hierarchy level-2 3 - Error
3275 structure hierarchy level-3 4 -
3276 Error structure hierarchy level-4
3277 All other values are reserved.
3278 Reserved 63:16 Reserved
3283 UINT64 ErrorInjection
:3;
3284 UINT64 ErrorSeverity
:2;
3285 UINT64 ErrorStructure
:5;
3286 UINT64 StructureHierarchy
:3;
3288 } PAL_MC_ERROR_TYPE_INFO
;
3292 @param StructInfoIsValid Bit0 When 1, indicates that the
3293 structure information fields
3294 (c_t,cl_p,cl_id) are valid and
3295 should be used for error injection.
3296 When 0, the structure information
3297 fields are ignored, and the values
3298 of these fields used for error
3300 implementation-specific.
3302 @param CacheType Bit2:1 Indicates which cache should be used
3303 for error injection: 0 - Reserved 1 -
3304 Instruction cache 2 - Data or unified cache
3308 @param PortionOfCacheLine Bit5:3 Indicates the portion of the
3309 cache line where the error should
3310 be injected: 0 - Reserved 1 - Tag
3311 2 - Data 3 - mesi All other
3312 values are reserved.
3314 @param Mechanism Bit8:6 Indicates which mechanism is used to
3315 identify the cache line to be used for error
3316 injection: 0 - Reserved 1 - Virtual address
3317 provided in the inj_addr field of the buffer
3318 pointed to by err_data_buffer should be used
3319 to identify the cache line for error
3320 injection. 2 - Physical address provided in
3321 the inj_addr field of the buffer pointed to
3322 by err_data_buffershould be used to identify
3323 the cache line for error injection. 3 - way
3324 and index fields provided in err_data_buffer
3325 should be used to identify the cache line
3326 for error injection. All other values are
3329 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a
3330 multiple bit, non-correctable
3331 error should be injected in the
3332 cache line specified by cl_id.
3333 If this injected error is not
3334 consumed, it may eventually
3335 cause a data-poisoning event
3336 resulting in a corrected error
3337 signal, when the associated
3338 cache line is cast out (implicit
3339 or explicit write-back of the
3340 cache line). The error severity
3341 specified by err_sev in
3342 err_type_info must be set to 0
3343 (corrected error) when this bit
3347 @param TrigerInfoIsValid Bit32 When 1, indicates that the
3348 trigger information fields (trigger,
3349 trigger_pl) are valid and should be
3350 used for error injection. When 0,
3351 the trigger information fields are
3352 ignored and error injection is
3353 performed immediately.
3355 @param Triger Bit36:33 Indicates the operation type to be
3356 used as the error trigger condition. The
3357 address corresponding to the trigger is
3358 specified in the trigger_addr field of the
3359 buffer pointed to by err_data_buffer: 0 -
3360 Instruction memory access. The trigger match
3361 conditions for this operation type are similar
3362 to the IBR address breakpoint match conditions
3363 1 - Data memory access. The trigger match
3364 conditions for this operation type are similar
3365 to the DBR address breakpoint match conditions
3366 All other values are reserved.
3368 @param PrivilegeOfTriger Bit39:37 Indicates the privilege
3369 level of the context during which
3370 the error should be injected: 0 -
3371 privilege level 0 1 - privilege
3372 level 1 2 - privilege level 2 3 -
3373 privilege level 3 All other values
3374 are reserved. If the implementation
3375 does not support privilege level
3376 qualifier for triggers (i.e. if
3377 trigger_pl is 0 in the capabilities
3378 vector), this field is ignored and
3379 triggers can be taken at any
3384 UINT64 StructInfoIsValid
:1;
3386 UINT64 PortionOfCacheLine
:3;
3388 UINT64 DataPoisonOfCacheLine
:1;
3389 UINT64 Reserved1
:22;
3390 UINT64 TrigerInfoIsValid
:1;
3392 UINT64 PrivilegeOfTriger
:3;
3393 UINT64 Reserved2
:24;
3394 } PAL_MC_ERROR_STRUCT_INFO
;
3398 Buffer Pointed to by err_data_buffer ¨C TLB
3402 UINT64 TrigerAddress
;
3403 UINT64 VirtualPageNumber
:52;
3406 UINT64 Reserved2
:40;
3407 } PAL_MC_ERROR_DATA_BUFFER_TLB
;
3411 PAL Procedure - PAL_MC_ERROR_INJECT.
3413 Injects the requested processor error or returns information
3414 on the supported injection capabilities for this particular
3415 processor implementation. It is optional by IPF. The PAL
3416 procedure supports the Stacked Registers calling convention.
3417 It could be called at physical and Virtual mode.
3420 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
3423 @param ErrorTypeInfo Unsigned 64-bit integer specifying the
3424 first level error information which
3425 identifies the error structure and
3426 corresponding structure hierarchy, and
3429 @param ErrorStructInfo Unsigned 64-bit integer identifying
3430 the optional structure specific
3431 information that provides the second
3432 level details for the requested error.
3434 @param ErrorDataBuffer 64-bit physical address of a buffer
3435 providing additional parameters for
3436 the requested error. The address of
3437 this buffer must be 8-byte aligned.
3439 @return R9 64-bit vector specifying the supported error
3440 injection capabilities for the input argument
3441 combination of struct_hier, err_struct and
3442 err_sev fields in ErrorTypeInfo.
3444 @return R10 64-bit vector specifying the architectural
3445 resources that are used by the procedure.
3448 @return Status 0 - Call completed without error
3450 @return Status -1 - Unimplemented procedure
3452 @return Status -2 - Invalid argument
3454 @return Status -3 - Call completed with error.
3456 @return Status -4 - Call completed with error; the requested
3457 error could not be injected due to failure in
3458 locating the target location in the specified
3461 @return Status -5 - Argument was valid, but requested error
3462 injection capability is not supported.
3464 @return Status -9 - Call requires PAL memory buffer.
3467 #define PAL_MC_ERROR_INJECT 276
3471 // Types of PAL_GET_PSTATE.Type
3473 #define PAL_GET_PSTATE_RECENT 0
3474 #define PAL_GET_PSTATE_AVERAGE_NEW_START 1
3475 #define PAL_GET_PSTATE_AVERAGE 2
3476 #define PAL_GET_PSTATE_NOW 3
3480 PAL Procedure - PAL_GET_PSTATE.
3482 Returns the performance index of the processor. It is optional
3483 by IPF. The PAL procedure supports the Stacked Registers
3484 calling convention. It could be called at physical and Virtual
3488 @param Index Index of PAL_GET_PSTATE within the list of PAL
3491 @param Type Type of performance_index value to be returned
3492 by this procedure.See PAL_GET_PSTATE.Type above.
3495 @return R9 Unsigned integer denoting the processor
3496 performance for the time duration since the last
3497 PAL_GET_PSTATE procedure call was made. The
3498 value returned is between 0 and 100, and is
3499 relative to the performance index of the highest
3502 @return Status 1 - Call completed without error, but accuracy
3503 of performance index has been impacted by a
3504 thermal throttling event, or a
3505 hardware-initiated event.
3507 @return Status 0 - Call completed without error
3509 @return Status -1 - Unimplemented procedure
3511 @return Status -2 - Invalid argument
3513 @return Status -3 - Call completed with error.
3515 @return Status -9 - Call requires PAL memory buffer.
3518 #define PAL_GET_PSTATE 262
3522 Layout of PAL_PSTATE_INFO.PStateBuffer
3526 UINT32 PerformanceIndex
:7;
3528 UINT32 TypicalPowerDissipation
:20;
3529 UINT32 TransitionLatency1
;
3530 UINT32 TransitionLatency2
;
3532 } PAL_PSTATE_INFO_BUFFER
;
3537 PAL Procedure - PAL_PSTATE_INFO.
3539 Returns information about the P-states supported by the
3540 processor. It is optional by IPF. The PAL procedure supports
3541 the Static Registers calling convention. It could be called
3542 at physical and Virtual mode.
3545 @param Index Index of PAL_PSTATE_INFO within the list of PAL
3548 @param PStateBuffer 64-bit pointer to a 256-byte buffer
3549 aligned on an 8-byte boundary. See
3550 PAL_PSTATE_INFO_BUFFER above.
3553 @return R9 Unsigned integer denoting the number of P-states
3554 supported. The maximum value of this field is 16.
3556 @return R10 Dependency domain information
3559 @return Status 0 - Call completed without error
3561 @return Status -1 - Unimplemented procedure
3563 @return Status -2 - Invalid argument
3565 @return Status -3 - Call completed with error.
3568 #define PAL_PSTATE_INFO 44
3573 PAL Procedure - PAL_SET_PSTATE.
3575 To request a processor transition to a given P-state. It is
3576 optional by IPF. The PAL procedure supports the Stacked
3577 Registers calling convention. It could be called at physical
3581 @param Index Index of PAL_SET_PSTATE within the list of PAL
3584 @param PState Unsigned integer denoting the processor
3585 P-state being requested.
3587 @param ForcePState Unsigned integer denoting whether the
3588 P-state change should be forced for the
3595 @return Status 1 - Call completed without error, but
3596 transition request was not accepted
3598 @return Status 0 - Call completed without error
3600 @return Status -1 - Unimplemented procedure
3602 @return Status -2 - Invalid argument
3604 @return Status -3 - Call completed with error.
3606 @return Status -9 - Call requires PAL memory buffer.
3609 #define PAL_SET_PSTATE 263
3613 PAL Procedure - PAL_SHUTDOWN.
3615 Put the logical processor into a low power state which can be
3616 exited only by a reset event. It is optional by IPF. The PAL
3617 procedure supports the Static Registers calling convention. It
3618 could be called at physical mode.
3621 @param Index Index of PAL_SHUTDOWN within the list of PAL
3624 @param NotifyPlatform 8-byte aligned physical address
3625 pointer providing details on how to
3626 optionally notify the platform that
3627 the processor is entering a shutdown
3630 @return Status -1 - Unimplemented procedure
3632 @return Status -2 - Invalid argument
3634 @return Status -3 - Call completed with error.
3636 @return Status -9 - Call requires PAL memory buffer.
3639 #define PAL_SHUTDOWN 45
3643 Layout of PAL_MEMORY_BUFFER.ControlWord
3647 UINT64 Registration
:1;
3648 UINT64 ProbeInterrupt
:1;
3650 } PAL_MEMORY_CONTROL_WORD
;
3654 PAL Procedure - PAL_MEMORY_BUFFER.
3656 Provides cacheable memory to PAL for exclusive use during
3657 runtime. It is optional by IPF. The PAL procedure supports the
3658 Static Registers calling convention. It could be called at
3662 @param Index Index of PAL_MEMORY_BUFFER within the list of PAL
3665 @param BaseAddress Physical address of the memory buffer
3666 allocated for PAL use.
3668 @param AllocSize Unsigned integer denoting the size of the
3671 @param ControlWord Formatted bit vector that provides control
3672 options for this procedure. See
3673 PAL_MEMORY_CONTROL_WORD above.
3675 @return R9 Returns the minimum size of the memory buffer
3676 required if the alloc_size input argument was
3679 @return Status 1 - Call has not completed a buffer relocation
3680 due to a pending interrupt
3682 @return Status 0 - Call completed without error
3684 @return Status -1 - Unimplemented procedure
3686 @return Status -2 - Invalid argument
3688 @return Status -3 - Call completed with error.
3690 @return Status -9 - Call requires PAL memory buffer.
3693 #define PAL_MEMORY_BUFFER 277
3698 PAL Procedure - PAL_VP_CREATE.
3700 Initializes a new vpd for the operation of a new virtual
3701 processor in the virtual environment. It is optional by IPF.
3702 The PAL procedure supports the Stacked Registers calling
3703 convention. It could be called at Virtual mode.
3706 @param Index Index of PAL_VP_CREATE within the list of PAL
3709 @param Vpd 64-bit host virtual pointer to the Virtual
3710 Processor Descriptor (VPD).
3712 @param HostIva 64-bit host virtual pointer to the host IVT
3713 for the virtual processor
3715 @param OptionalHandler 64-bit non-zero host-virtual pointer
3716 to an optional handler for
3717 virtualization intercepts.
3720 @return Status 0 - Call completed without error
3722 @return Status -1 - Unimplemented procedure
3724 @return Status -2 - Invalid argument
3726 @return Status -3 - Call completed with error.
3728 @return Status -9 - Call requires PAL memory buffer.
3731 #define PAL_VP_CREATE 265
3735 Virtual Environment Information Parameter
3742 } PAL_VP_ENV_INFO_RETURN
;
3746 PAL Procedure - PAL_VP_ENV_INFO.
3748 Returns the parameters needed to enter a virtual environment.
3749 It is optional by IPF. The PAL procedure supports the Stacked
3750 Registers calling convention. It could be called at Virtual
3754 @param Index Index of PAL_VP_ENV_INFO within the list of PAL
3757 @param Vpd 64-bit host virtual pointer to the Virtual
3758 Processor Descriptor (VPD).
3760 @param HostIva 64-bit host virtual pointer to the host IVT
3761 for the virtual processor
3763 @param OptionalHandler 64-bit non-zero host-virtual pointer
3764 to an optional handler for
3765 virtualization intercepts.
3766 @return R9 Unsigned integer denoting the number of bytes
3767 required by the PAL virtual environment buffer
3768 during PAL_VP_INIT_ENV
3770 @return R10 64-bit vector of virtual environment
3771 information. See PAL_VP_ENV_INFO_RETURN.
3774 @return Status 0 - Call completed without error
3776 @return Status -1 - Unimplemented procedure
3778 @return Status -2 - Invalid argument
3780 @return Status -3 - Call completed with error.
3782 @return Status -9 - Call requires PAL memory buffer.
3785 #define PAL_VP_ENV_INFO 266
3789 PAL Procedure - PAL_VP_EXIT_ENV.
3791 Allows a logical processor to exit a virtual environment.
3792 It is optional by IPF. The PAL procedure supports the Stacked
3793 Registers calling convention. It could be called at Virtual
3797 @param Index Index of PAL_VP_EXIT_ENV within the list of PAL
3800 @param Iva Optional 64-bit host virtual pointer to the IVT
3801 when this procedure is done
3803 @return Status 0 - Call completed without error
3805 @return Status -1 - Unimplemented procedure
3807 @return Status -2 - Invalid argument
3809 @return Status -3 - Call completed with error.
3811 @return Status -9 - Call requires PAL memory buffer.
3814 #define PAL_VP_EXIT_ENV 267
3820 PAL Procedure - PAL_VP_INIT_ENV.
3822 Allows a logical processor to enter a virtual environment. It
3823 is optional by IPF. The PAL procedure supports the Stacked
3824 Registers calling convention. It could be called at Virtual
3828 @param Index Index of PAL_VP_INIT_ENV within the list of PAL
3831 @param ConfigOptions 64-bit vector of global configuration
3834 @param PhysicalBase Host physical base address of a block of
3835 contiguous physical memory for the PAL
3836 virtual environment buffer 1) This
3837 memory area must be allocated by the VMM
3838 and be 4K aligned. The first logical
3839 processor to enter the environment will
3840 initialize the physical block for
3841 virtualization operations.
3843 @param VirtualBase Host virtual base address of the
3844 corresponding physical memory block for
3845 the PAL virtual environment buffer : The
3846 VMM must maintain the host virtual to host
3847 physical data and instruction translations
3848 in TRs for addresses within the allocated
3849 address space. Logical processors in this
3850 virtual environment will use this address
3851 when transitioning to virtual mode
3854 @return R9 Virtualization Service Address ¨C VSA specifies
3855 the virtual base address of the PAL
3856 virtualization services in this virtual
3860 @return Status 0 - Call completed without error
3862 @return Status -1 - Unimplemented procedure
3864 @return Status -2 - Invalid argument
3866 @return Status -3 - Call completed with error.
3868 @return Status -9 - Call requires PAL memory buffer.
3871 #define PAL_VP_INIT_ENV 268
3876 PAL Procedure - PAL_VP_REGISTER.
3878 Register a different host IVT and/or a different optional
3879 virtualization intercept handler for the virtual processor
3880 specified by vpd. It is optional by IPF. The PAL procedure
3881 supports the Stacked Registers calling convention. It could be
3882 called at Virtual mode.
3885 @param Index Index of PAL_VP_REGISTER within the list of PAL
3888 @param Vpd 64-bit host virtual pointer to the Virtual
3889 Processor Descriptor (VPD) host_iva 64-bit host
3890 virtual pointer to the host IVT for the virtual
3893 @param OptionalHandler 64-bit non-zero host-virtual pointer
3894 to an optional handler for
3895 virtualization intercepts.
3898 @return Status 0 - Call completed without error
3900 @return Status -1 - Unimplemented procedure
3902 @return Status -2 - Invalid argument
3904 @return Status -3 - Call completed with error.
3906 @return Status -9 - Call requires PAL memory buffer.
3909 #define PAL_VP_REGISTER 269
3914 PAL Procedure - PAL_VP_RESTORE.
3916 Restores virtual processor state for the specified vpd on the
3917 logical processor. It is optional by IPF. The PAL procedure
3918 supports the Stacked Registers calling convention. It could be
3919 called at Virtual mode.
3922 @param Index Index of PAL_VP_RESTORE within the list of PAL
3925 @param Vpd 64-bit host virtual pointer to the Virtual
3926 Processor Descriptor (VPD) host_iva 64-bit host
3927 virtual pointer to the host IVT for the virtual
3930 @param PalVector Vector specifies PAL procedure
3931 implementation-specific state to be
3935 @return Status 0 - Call completed without error
3937 @return Status -1 - Unimplemented procedure
3939 @return Status -2 - Invalid argument
3941 @return Status -3 - Call completed with error.
3943 @return Status -9 - Call requires PAL memory buffer.
3946 #define PAL_VP_RESTORE 270
3950 PAL Procedure - PAL_VP_SAVE.
3952 Saves virtual processor state for the specified vpd on the
3953 logical processor. It is optional by IPF. The PAL procedure
3954 supports the Stacked Registers calling convention. It could be
3955 called at Virtual mode.
3958 @param Index Index of PAL_VP_SAVE within the list of PAL
3961 @param Vpd 64-bit host virtual pointer to the Virtual
3962 Processor Descriptor (VPD) host_iva 64-bit host
3963 virtual pointer to the host IVT for the virtual
3966 @param PalVector Vector specifies PAL procedure
3967 implementation-specific state to be
3971 @return Status 0 - Call completed without error
3973 @return Status -1 - Unimplemented procedure
3975 @return Status -2 - Invalid argument
3977 @return Status -3 - Call completed with error.
3979 @return Status -9 - Call requires PAL memory buffer.
3982 #define PAL_VP_SAVE 271
3987 PAL Procedure - PAL_VP_TERMINATE.
3989 Terminates operation for the specified virtual processor. It
3990 is optional by IPF. The PAL procedure supports the Stacked
3991 Registers calling convention. It could be called at Virtual
3995 @param Index Index of PAL_VP_TERMINATE within the list of PAL
3998 @param Vpd 64-bit host virtual pointer to the Virtual
3999 Processor Descriptor (VPD)
4001 @param Iva Optional 64-bit host virtual pointer to the IVT
4002 when this procedure is done.
4004 @return Status 0 - Call completed without error
4006 @return Status -1 - Unimplemented procedure
4008 @return Status -2 - Invalid argument
4010 @return Status -3 - Call completed with error.
4012 @return Status -9 - Call requires PAL memory buffer.
4015 #define PAL_VP_TERMINATE 272
4018 Makes a PAL procedure call.
4020 This is a wrapper function to make a PAL procedure call. Based on the Index value,
4021 this API will make static or stacked PAL call. Architected procedures may be designated
4022 as required or optional. If a PAL procedure is specified as optional, a unique return
4023 code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
4024 This indicates that the procedure is not present in this PAL implementation. It is the
4025 caller¡¯s responsibility to check for this return code after calling any optional PAL
4026 procedure. No parameter checking is performed on the 4 input parameters, but there are
4027 some common rules that the caller should follow when making a PAL call. Any address
4028 passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
4029 may cause undefined results. For those parameters defined as reserved or some fields
4030 defined as reserved must be zero filled or the invalid argument return value may be
4031 returned or undefined result may occur during the execution of the procedure.
4032 This function is only available on IPF.
4034 @param Index - The PAL procedure Index number.
4035 @param Arg2 - The 2nd parameter for PAL procedure calls.
4036 @param Arg3 - The 3rd parameter for PAL procedure calls.
4037 @param Arg4 - The 4th parameter for PAL procedure calls.
4039 @return structure returned from the PAL Call procedure, including the status and return value.