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2 PCI CF8 Library Services for PCI Segment #0
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 Module Name: PciCf8Lib.h
17 #ifndef __PCI_CF8_LIB_H__
18 #define __PCI_CF8_LIB_H__
22 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
23 address that can be passed to the PCI Library functions.
25 Computes an address that is compatible with the PCI Library functions. The
26 unused upper bits of Bus, Device, Function and Register are stripped prior to
27 the generation of the address.
29 @param Bus PCI Bus number. Range 0..255.
30 @param Device PCI Device number. Range 0..31.
31 @param Function PCI Function number. Range 0..7.
32 @param Register PCI Register number. Range 0..255.
34 @return The encode PCI address.
37 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
38 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
41 Reads an 8-bit PCI configuration register.
43 Reads and returns the 8-bit PCI configuration register specified by Address.
44 This function must guarantee that all PCI read and write operations are
47 If Address > 0x0FFFFFFF, then ASSERT().
48 If the register specified by Address >= 0x100, then ASSERT().
50 @param Address Address that encodes the PCI Bus, Device, Function and
53 @return The read value from the PCI configuration register.
63 Writes an 8-bit PCI configuration register.
65 Writes the 8-bit PCI configuration register specified by Address with the
66 value specified by Value. Value is returned. This function must guarantee
67 that all PCI read and write operations are serialized.
69 If Address > 0x0FFFFFFF, then ASSERT().
70 If the register specified by Address >= 0x100, then ASSERT().
72 @param Address Address that encodes the PCI Bus, Device, Function and
74 @param Value The value to write.
76 @return The value written to the PCI configuration register.
87 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
90 Reads the 8-bit PCI configuration register specified by Address, performs a
91 bitwise inclusive OR between the read result and the value specified by
92 OrData, and writes the result to the 8-bit PCI configuration register
93 specified by Address. The value written to the PCI configuration register is
94 returned. This function must guarantee that all PCI read and write operations
97 If Address > 0x0FFFFFFF, then ASSERT().
98 If the register specified by Address >= 0x100, then ASSERT().
100 @param Address Address that encodes the PCI Bus, Device, Function and
102 @param OrData The value to OR with the PCI configuration register.
104 @return The value written back to the PCI configuration register.
115 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
118 Reads the 8-bit PCI configuration register specified by Address, performs a
119 bitwise AND between the read result and the value specified by AndData, and
120 writes the result to the 8-bit PCI configuration register specified by
121 Address. The value written to the PCI configuration register is returned.
122 This function must guarantee that all PCI read and write operations are
125 If Address > 0x0FFFFFFF, then ASSERT().
126 If the register specified by Address >= 0x100, then ASSERT().
128 @param Address Address that encodes the PCI Bus, Device, Function and
130 @param AndData The value to AND with the PCI configuration register.
132 @return The value written back to the PCI configuration register.
143 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
144 value, followed a bitwise inclusive OR with another 8-bit value.
146 Reads the 8-bit PCI configuration register specified by Address, performs a
147 bitwise AND between the read result and the value specified by AndData,
148 performs a bitwise inclusive OR between the result of the AND operation and
149 the value specified by OrData, and writes the result to the 8-bit PCI
150 configuration register specified by Address. The value written to the PCI
151 configuration register is returned. This function must guarantee that all PCI
152 read and write operations are serialized.
154 If Address > 0x0FFFFFFF, then ASSERT().
155 If the register specified by Address >= 0x100, then ASSERT().
157 @param Address Address that encodes the PCI Bus, Device, Function and
159 @param AndData The value to AND with the PCI configuration register.
160 @param OrData The value to OR with the result of the AND operation.
162 @return The value written back to the PCI configuration register.
174 Reads a bit field of a PCI configuration register.
176 Reads the bit field in an 8-bit PCI configuration register. The bit field is
177 specified by the StartBit and the EndBit. The value of the bit field is
180 If Address > 0x0FFFFFFF, then ASSERT().
181 If the register specified by Address >= 0x100, then ASSERT().
182 If StartBit is greater than 7, then ASSERT().
183 If EndBit is greater than 7, then ASSERT().
184 If EndBit is less than StartBit, then ASSERT().
186 @param Address PCI configuration register to read.
187 @param StartBit The ordinal of the least significant bit in the bit field.
189 @param EndBit The ordinal of the most significant bit in the bit field.
192 @return The value of the bit field read from the PCI configuration register.
197 PciCf8BitFieldRead8 (
204 Writes a bit field to a PCI configuration register.
206 Writes Value to the bit field of the PCI configuration register. The bit
207 field is specified by the StartBit and the EndBit. All other bits in the
208 destination PCI configuration register are preserved. The new value of the
209 8-bit register is returned.
211 If Address > 0x0FFFFFFF, then ASSERT().
212 If the register specified by Address >= 0x100, then ASSERT().
213 If StartBit is greater than 7, then ASSERT().
214 If EndBit is greater than 7, then ASSERT().
215 If EndBit is less than StartBit, then ASSERT().
217 @param Address PCI configuration register to write.
218 @param StartBit The ordinal of the least significant bit in the bit field.
220 @param EndBit The ordinal of the most significant bit in the bit field.
222 @param Value New value of the bit field.
224 @return The value written back to the PCI configuration register.
229 PciCf8BitFieldWrite8 (
237 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
238 writes the result back to the bit field in the 8-bit port.
240 Reads the 8-bit PCI configuration register specified by Address, performs a
241 bitwise inclusive OR between the read result and the value specified by
242 OrData, and writes the result to the 8-bit PCI configuration register
243 specified by Address. The value written to the PCI configuration register is
244 returned. This function must guarantee that all PCI read and write operations
245 are serialized. Extra left bits in OrData are stripped.
247 If Address > 0x0FFFFFFF, then ASSERT().
248 If the register specified by Address >= 0x100, then ASSERT().
249 If StartBit is greater than 7, then ASSERT().
250 If EndBit is greater than 7, then ASSERT().
251 If EndBit is less than StartBit, then ASSERT().
253 @param Address PCI configuration register to write.
254 @param StartBit The ordinal of the least significant bit in the bit field.
256 @param EndBit The ordinal of the most significant bit in the bit field.
258 @param OrData The value to OR with the PCI configuration register.
260 @return The value written back to the PCI configuration register.
273 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
274 AND, and writes the result back to the bit field in the 8-bit register.
276 Reads the 8-bit PCI configuration register specified by Address, performs a
277 bitwise AND between the read result and the value specified by AndData, and
278 writes the result to the 8-bit PCI configuration register specified by
279 Address. The value written to the PCI configuration register is returned.
280 This function must guarantee that all PCI read and write operations are
281 serialized. Extra left bits in AndData are stripped.
283 If Address > 0x0FFFFFFF, then ASSERT().
284 If the register specified by Address >= 0x100, then ASSERT().
285 If StartBit is greater than 7, then ASSERT().
286 If EndBit is greater than 7, then ASSERT().
287 If EndBit is less than StartBit, then ASSERT().
289 @param Address PCI configuration register to write.
290 @param StartBit The ordinal of the least significant bit in the bit field.
292 @param EndBit The ordinal of the most significant bit in the bit field.
294 @param AndData The value to AND with the PCI configuration register.
296 @return The value written back to the PCI configuration register.
309 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
310 bitwise inclusive OR, and writes the result back to the bit field in the
313 Reads the 8-bit PCI configuration register specified by Address, performs a
314 bitwise AND followed by a bitwise inclusive OR between the read result and
315 the value specified by AndData, and writes the result to the 8-bit PCI
316 configuration register specified by Address. The value written to the PCI
317 configuration register is returned. This function must guarantee that all PCI
318 read and write operations are serialized. Extra left bits in both AndData and
321 If Address > 0x0FFFFFFF, then ASSERT().
322 If the register specified by Address >= 0x100, then ASSERT().
323 If StartBit is greater than 7, then ASSERT().
324 If EndBit is greater than 7, then ASSERT().
325 If EndBit is less than StartBit, then ASSERT().
327 @param Address PCI configuration register to write.
328 @param StartBit The ordinal of the least significant bit in the bit field.
330 @param EndBit The ordinal of the most significant bit in the bit field.
332 @param AndData The value to AND with the PCI configuration register.
333 @param OrData The value to OR with the result of the AND operation.
335 @return The value written back to the PCI configuration register.
340 PciCf8BitFieldAndThenOr8 (
349 Reads a 16-bit PCI configuration register.
351 Reads and returns the 16-bit PCI configuration register specified by Address.
352 This function must guarantee that all PCI read and write operations are
355 If Address > 0x0FFFFFFF, then ASSERT().
356 If Address is not aligned on a 16-bit boundary, then ASSERT().
357 If the register specified by Address >= 0x100, then ASSERT().
359 @param Address Address that encodes the PCI Bus, Device, Function and
362 @return The read value from the PCI configuration register.
372 Writes a 16-bit PCI configuration register.
374 Writes the 16-bit PCI configuration register specified by Address with the
375 value specified by Value. Value is returned. This function must guarantee
376 that all PCI read and write operations are serialized.
378 If Address > 0x0FFFFFFF, then ASSERT().
379 If Address is not aligned on a 16-bit boundary, then ASSERT().
380 If the register specified by Address >= 0x100, then ASSERT().
382 @param Address Address that encodes the PCI Bus, Device, Function and
384 @param Value The value to write.
386 @return The value written to the PCI configuration register.
397 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
400 Reads the 16-bit PCI configuration register specified by Address, performs a
401 bitwise inclusive OR between the read result and the value specified by
402 OrData, and writes the result to the 16-bit PCI configuration register
403 specified by Address. The value written to the PCI configuration register is
404 returned. This function must guarantee that all PCI read and write operations
407 If Address > 0x0FFFFFFF, then ASSERT().
408 If Address is not aligned on a 16-bit boundary, then ASSERT().
409 If the register specified by Address >= 0x100, then ASSERT().
411 @param Address Address that encodes the PCI Bus, Device, Function and
413 @param OrData The value to OR with the PCI configuration register.
415 @return The value written back to the PCI configuration register.
426 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
429 Reads the 16-bit PCI configuration register specified by Address, performs a
430 bitwise AND between the read result and the value specified by AndData, and
431 writes the result to the 16-bit PCI configuration register specified by
432 Address. The value written to the PCI configuration register is returned.
433 This function must guarantee that all PCI read and write operations are
436 If Address > 0x0FFFFFFF, then ASSERT().
437 If Address is not aligned on a 16-bit boundary, then ASSERT().
438 If the register specified by Address >= 0x100, then ASSERT().
440 @param Address Address that encodes the PCI Bus, Device, Function and
442 @param AndData The value to AND with the PCI configuration register.
444 @return The value written back to the PCI configuration register.
455 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
456 value, followed a bitwise inclusive OR with another 16-bit value.
458 Reads the 16-bit PCI configuration register specified by Address, performs a
459 bitwise AND between the read result and the value specified by AndData,
460 performs a bitwise inclusive OR between the result of the AND operation and
461 the value specified by OrData, and writes the result to the 16-bit PCI
462 configuration register specified by Address. The value written to the PCI
463 configuration register is returned. This function must guarantee that all PCI
464 read and write operations are serialized.
466 If Address > 0x0FFFFFFF, then ASSERT().
467 If Address is not aligned on a 16-bit boundary, then ASSERT().
468 If the register specified by Address >= 0x100, then ASSERT().
470 @param Address Address that encodes the PCI Bus, Device, Function and
472 @param AndData The value to AND with the PCI configuration register.
473 @param OrData The value to OR with the result of the AND operation.
475 @return The value written back to the PCI configuration register.
487 Reads a bit field of a PCI configuration register.
489 Reads the bit field in a 16-bit PCI configuration register. The bit field is
490 specified by the StartBit and the EndBit. The value of the bit field is
493 If Address > 0x0FFFFFFF, then ASSERT().
494 If Address is not aligned on a 16-bit boundary, then ASSERT().
495 If the register specified by Address >= 0x100, then ASSERT().
496 If StartBit is greater than 15, then ASSERT().
497 If EndBit is greater than 15, then ASSERT().
498 If EndBit is less than StartBit, then ASSERT().
500 @param Address PCI configuration register to read.
501 @param StartBit The ordinal of the least significant bit in the bit field.
503 @param EndBit The ordinal of the most significant bit in the bit field.
506 @return The value of the bit field read from the PCI configuration register.
511 PciCf8BitFieldRead16 (
518 Writes a bit field to a PCI configuration register.
520 Writes Value to the bit field of the PCI configuration register. The bit
521 field is specified by the StartBit and the EndBit. All other bits in the
522 destination PCI configuration register are preserved. The new value of the
523 16-bit register is returned.
525 If Address > 0x0FFFFFFF, then ASSERT().
526 If Address is not aligned on a 16-bit boundary, then ASSERT().
527 If the register specified by Address >= 0x100, then ASSERT().
528 If StartBit is greater than 15, then ASSERT().
529 If EndBit is greater than 15, then ASSERT().
530 If EndBit is less than StartBit, then ASSERT().
532 @param Address PCI configuration register to write.
533 @param StartBit The ordinal of the least significant bit in the bit field.
535 @param EndBit The ordinal of the most significant bit in the bit field.
537 @param Value New value of the bit field.
539 @return The value written back to the PCI configuration register.
544 PciCf8BitFieldWrite16 (
552 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
553 writes the result back to the bit field in the 16-bit port.
555 Reads the 16-bit PCI configuration register specified by Address, performs a
556 bitwise inclusive OR between the read result and the value specified by
557 OrData, and writes the result to the 16-bit PCI configuration register
558 specified by Address. The value written to the PCI configuration register is
559 returned. This function must guarantee that all PCI read and write operations
560 are serialized. Extra left bits in OrData are stripped.
562 If Address > 0x0FFFFFFF, then ASSERT().
563 If Address is not aligned on a 16-bit boundary, then ASSERT().
564 If the register specified by Address >= 0x100, then ASSERT().
565 If StartBit is greater than 15, then ASSERT().
566 If EndBit is greater than 15, then ASSERT().
567 If EndBit is less than StartBit, then ASSERT().
569 @param Address PCI configuration register to write.
570 @param StartBit The ordinal of the least significant bit in the bit field.
572 @param EndBit The ordinal of the most significant bit in the bit field.
574 @param OrData The value to OR with the PCI configuration register.
576 @return The value written back to the PCI configuration register.
589 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
590 AND, and writes the result back to the bit field in the 16-bit register.
592 Reads the 16-bit PCI configuration register specified by Address, performs a
593 bitwise AND between the read result and the value specified by AndData, and
594 writes the result to the 16-bit PCI configuration register specified by
595 Address. The value written to the PCI configuration register is returned.
596 This function must guarantee that all PCI read and write operations are
597 serialized. Extra left bits in AndData are stripped.
599 If Address > 0x0FFFFFFF, then ASSERT().
600 If Address is not aligned on a 16-bit boundary, then ASSERT().
601 If the register specified by Address >= 0x100, then ASSERT().
602 If StartBit is greater than 15, then ASSERT().
603 If EndBit is greater than 15, then ASSERT().
604 If EndBit is less than StartBit, then ASSERT().
606 @param Address PCI configuration register to write.
607 @param StartBit The ordinal of the least significant bit in the bit field.
609 @param EndBit The ordinal of the most significant bit in the bit field.
611 @param AndData The value to AND with the PCI configuration register.
613 @return The value written back to the PCI configuration register.
618 PciCf8BitFieldAnd16 (
626 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
627 bitwise inclusive OR, and writes the result back to the bit field in the
630 Reads the 16-bit PCI configuration register specified by Address, performs a
631 bitwise AND followed by a bitwise inclusive OR between the read result and
632 the value specified by AndData, and writes the result to the 16-bit PCI
633 configuration register specified by Address. The value written to the PCI
634 configuration register is returned. This function must guarantee that all PCI
635 read and write operations are serialized. Extra left bits in both AndData and
638 If Address > 0x0FFFFFFF, then ASSERT().
639 If Address is not aligned on a 16-bit boundary, then ASSERT().
640 If the register specified by Address >= 0x100, then ASSERT().
641 If StartBit is greater than 15, then ASSERT().
642 If EndBit is greater than 15, then ASSERT().
643 If EndBit is less than StartBit, then ASSERT().
645 @param Address PCI configuration register to write.
646 @param StartBit The ordinal of the least significant bit in the bit field.
648 @param EndBit The ordinal of the most significant bit in the bit field.
650 @param AndData The value to AND with the PCI configuration register.
651 @param OrData The value to OR with the result of the AND operation.
653 @return The value written back to the PCI configuration register.
658 PciCf8BitFieldAndThenOr16 (
667 Reads a 32-bit PCI configuration register.
669 Reads and returns the 32-bit PCI configuration register specified by Address.
670 This function must guarantee that all PCI read and write operations are
673 If Address > 0x0FFFFFFF, then ASSERT().
674 If Address is not aligned on a 32-bit boundary, then ASSERT().
675 If the register specified by Address >= 0x100, then ASSERT().
677 @param Address Address that encodes the PCI Bus, Device, Function and
680 @return The read value from the PCI configuration register.
690 Writes a 32-bit PCI configuration register.
692 Writes the 32-bit PCI configuration register specified by Address with the
693 value specified by Value. Value is returned. This function must guarantee
694 that all PCI read and write operations are serialized.
696 If Address > 0x0FFFFFFF, then ASSERT().
697 If Address is not aligned on a 32-bit boundary, then ASSERT().
698 If the register specified by Address >= 0x100, then ASSERT().
700 @param Address Address that encodes the PCI Bus, Device, Function and
702 @param Value The value to write.
704 @return The value written to the PCI configuration register.
715 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
718 Reads the 32-bit PCI configuration register specified by Address, performs a
719 bitwise inclusive OR between the read result and the value specified by
720 OrData, and writes the result to the 32-bit PCI configuration register
721 specified by Address. The value written to the PCI configuration register is
722 returned. This function must guarantee that all PCI read and write operations
725 If Address > 0x0FFFFFFF, then ASSERT().
726 If Address is not aligned on a 32-bit boundary, then ASSERT().
727 If the register specified by Address >= 0x100, then ASSERT().
729 @param Address Address that encodes the PCI Bus, Device, Function and
731 @param OrData The value to OR with the PCI configuration register.
733 @return The value written back to the PCI configuration register.
744 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
747 Reads the 32-bit PCI configuration register specified by Address, performs a
748 bitwise AND between the read result and the value specified by AndData, and
749 writes the result to the 32-bit PCI configuration register specified by
750 Address. The value written to the PCI configuration register is returned.
751 This function must guarantee that all PCI read and write operations are
754 If Address > 0x0FFFFFFF, then ASSERT().
755 If Address is not aligned on a 32-bit boundary, then ASSERT().
756 If the register specified by Address >= 0x100, then ASSERT().
758 @param Address Address that encodes the PCI Bus, Device, Function and
760 @param AndData The value to AND with the PCI configuration register.
762 @return The value written back to the PCI configuration register.
773 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
774 value, followed a bitwise inclusive OR with another 32-bit value.
776 Reads the 32-bit PCI configuration register specified by Address, performs a
777 bitwise AND between the read result and the value specified by AndData,
778 performs a bitwise inclusive OR between the result of the AND operation and
779 the value specified by OrData, and writes the result to the 32-bit PCI
780 configuration register specified by Address. The value written to the PCI
781 configuration register is returned. This function must guarantee that all PCI
782 read and write operations are serialized.
784 If Address > 0x0FFFFFFF, then ASSERT().
785 If Address is not aligned on a 32-bit boundary, then ASSERT().
786 If the register specified by Address >= 0x100, then ASSERT().
788 @param Address Address that encodes the PCI Bus, Device, Function and
790 @param AndData The value to AND with the PCI configuration register.
791 @param OrData The value to OR with the result of the AND operation.
793 @return The value written back to the PCI configuration register.
805 Reads a bit field of a PCI configuration register.
807 Reads the bit field in a 32-bit PCI configuration register. The bit field is
808 specified by the StartBit and the EndBit. The value of the bit field is
811 If Address > 0x0FFFFFFF, then ASSERT().
812 If Address is not aligned on a 32-bit boundary, then ASSERT().
813 If the register specified by Address >= 0x100, then ASSERT().
814 If StartBit is greater than 31, then ASSERT().
815 If EndBit is greater than 31, then ASSERT().
816 If EndBit is less than StartBit, then ASSERT().
818 @param Address PCI configuration register to read.
819 @param StartBit The ordinal of the least significant bit in the bit field.
821 @param EndBit The ordinal of the most significant bit in the bit field.
824 @return The value of the bit field read from the PCI configuration register.
829 PciCf8BitFieldRead32 (
836 Writes a bit field to a PCI configuration register.
838 Writes Value to the bit field of the PCI configuration register. The bit
839 field is specified by the StartBit and the EndBit. All other bits in the
840 destination PCI configuration register are preserved. The new value of the
841 32-bit register is returned.
843 If Address > 0x0FFFFFFF, then ASSERT().
844 If Address is not aligned on a 32-bit boundary, then ASSERT().
845 If the register specified by Address >= 0x100, then ASSERT().
846 If StartBit is greater than 31, then ASSERT().
847 If EndBit is greater than 31, then ASSERT().
848 If EndBit is less than StartBit, then ASSERT().
850 @param Address PCI configuration register to write.
851 @param StartBit The ordinal of the least significant bit in the bit field.
853 @param EndBit The ordinal of the most significant bit in the bit field.
855 @param Value New value of the bit field.
857 @return The value written back to the PCI configuration register.
862 PciCf8BitFieldWrite32 (
870 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
871 writes the result back to the bit field in the 32-bit port.
873 Reads the 32-bit PCI configuration register specified by Address, performs a
874 bitwise inclusive OR between the read result and the value specified by
875 OrData, and writes the result to the 32-bit PCI configuration register
876 specified by Address. The value written to the PCI configuration register is
877 returned. This function must guarantee that all PCI read and write operations
878 are serialized. Extra left bits in OrData are stripped.
880 If Address > 0x0FFFFFFF, then ASSERT().
881 If Address is not aligned on a 32-bit boundary, then ASSERT().
882 If the register specified by Address >= 0x100, then ASSERT().
883 If StartBit is greater than 31, then ASSERT().
884 If EndBit is greater than 31, then ASSERT().
885 If EndBit is less than StartBit, then ASSERT().
887 @param Address PCI configuration register to write.
888 @param StartBit The ordinal of the least significant bit in the bit field.
890 @param EndBit The ordinal of the most significant bit in the bit field.
892 @param OrData The value to OR with the PCI configuration register.
894 @return The value written back to the PCI configuration register.
907 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
908 AND, and writes the result back to the bit field in the 32-bit register.
910 Reads the 32-bit PCI configuration register specified by Address, performs a
911 bitwise AND between the read result and the value specified by AndData, and
912 writes the result to the 32-bit PCI configuration register specified by
913 Address. The value written to the PCI configuration register is returned.
914 This function must guarantee that all PCI read and write operations are
915 serialized. Extra left bits in AndData are stripped.
917 If Address > 0x0FFFFFFF, then ASSERT().
918 If Address is not aligned on a 32-bit boundary, then ASSERT().
919 If the register specified by Address >= 0x100, then ASSERT().
920 If StartBit is greater than 31, then ASSERT().
921 If EndBit is greater than 31, then ASSERT().
922 If EndBit is less than StartBit, then ASSERT().
924 @param Address PCI configuration register to write.
925 @param StartBit The ordinal of the least significant bit in the bit field.
927 @param EndBit The ordinal of the most significant bit in the bit field.
929 @param AndData The value to AND with the PCI configuration register.
931 @return The value written back to the PCI configuration register.
936 PciCf8BitFieldAnd32 (
944 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
945 bitwise inclusive OR, and writes the result back to the bit field in the
948 Reads the 32-bit PCI configuration register specified by Address, performs a
949 bitwise AND followed by a bitwise inclusive OR between the read result and
950 the value specified by AndData, and writes the result to the 32-bit PCI
951 configuration register specified by Address. The value written to the PCI
952 configuration register is returned. This function must guarantee that all PCI
953 read and write operations are serialized. Extra left bits in both AndData and
956 If Address > 0x0FFFFFFF, then ASSERT().
957 If Address is not aligned on a 32-bit boundary, then ASSERT().
958 If the register specified by Address >= 0x100, then ASSERT().
959 If StartBit is greater than 31, then ASSERT().
960 If EndBit is greater than 31, then ASSERT().
961 If EndBit is less than StartBit, then ASSERT().
963 @param Address PCI configuration register to write.
964 @param StartBit The ordinal of the least significant bit in the bit field.
966 @param EndBit The ordinal of the most significant bit in the bit field.
968 @param AndData The value to AND with the PCI configuration register.
969 @param OrData The value to OR with the result of the AND operation.
971 @return The value written back to the PCI configuration register.
976 PciCf8BitFieldAndThenOr32 (
985 Reads a range of PCI configuration registers into a caller supplied buffer.
987 Reads the range of PCI configuration registers specified by StartAddress and
988 Size into the buffer specified by Buffer. This function only allows the PCI
989 configuration registers from a single PCI function to be read. Size is
990 returned. When possible 32-bit PCI configuration read cycles are used to read
991 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
992 and 16-bit PCI configuration read cycles may be used at the beginning and the
995 If StartAddress > 0x0FFFFFFF, then ASSERT().
996 If the register specified by StartAddress >= 0x100, then ASSERT().
997 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
998 If Size > 0 and Buffer is NULL, then ASSERT().
1000 @param StartAddress Starting address that encodes the PCI Bus, Device,
1001 Function and Register.
1002 @param Size Size in bytes of the transfer.
1003 @param Buffer Pointer to a buffer receiving the data read.
1011 IN UINTN StartAddress
,
1017 Copies the data in a caller supplied buffer to a specified range of PCI
1018 configuration space.
1020 Writes the range of PCI configuration registers specified by StartAddress and
1021 Size from the buffer specified by Buffer. This function only allows the PCI
1022 configuration registers from a single PCI function to be written. Size is
1023 returned. When possible 32-bit PCI configuration write cycles are used to
1024 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1025 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1026 and the end of the range.
1028 If StartAddress > 0x0FFFFFFF, then ASSERT().
1029 If the register specified by StartAddress >= 0x100, then ASSERT().
1030 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1031 If Size > 0 and Buffer is NULL, then ASSERT().
1033 @param StartAddress Starting address that encodes the PCI Bus, Device,
1034 Function and Register.
1035 @param Size Size in bytes of the transfer.
1036 @param Buffer Pointer to a buffer containing the data to write.
1044 IN UINTN StartAddress
,