]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Library/PciCf8Lib.h
2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
6 access to PCI Segment #0.
8 Copyright (c) 2006 - 2009, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __PCI_CF8_LIB_H__
20 #define __PCI_CF8_LIB_H__
24 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
25 address that can be passed to the PCI Library functions.
27 Computes an address that is compatible with the PCI Library functions. The
28 unused upper bits of Bus, Device, Function and Register are stripped prior to
29 the generation of the address.
31 @param Bus PCI Bus number. Range 0..255.
32 @param Device PCI Device number. Range 0..31.
33 @param Function PCI Function number. Range 0..7.
34 @param Register PCI Register number. Range 0..255.
36 @return The encode PCI address.
39 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
40 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
43 Registers a PCI device so PCI configuration registers may be accessed after
44 SetVirtualAddressMap().
46 Registers the PCI device specified by Address so all the PCI configuration registers
47 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
49 If Address > 0x0FFFFFFF, then ASSERT().
50 If the register specified by Address >= 0x100, then ASSERT().
52 @param Address Address that encodes the PCI Bus, Device, Function and
55 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
56 @retval RETURN_UNSUPPORTED An attempt was made to call this function
57 after ExitBootServices().
58 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
59 at runtime could not be mapped.
60 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
61 complete the registration.
66 PciCf8RegisterForRuntimeAccess (
71 Reads an 8-bit PCI configuration register.
73 Reads and returns the 8-bit PCI configuration register specified by Address.
74 This function must guarantee that all PCI read and write operations are
77 If Address > 0x0FFFFFFF, then ASSERT().
78 If the register specified by Address >= 0x100, then ASSERT().
80 @param Address Address that encodes the PCI Bus, Device, Function and
83 @return The read value from the PCI configuration register.
93 Writes an 8-bit PCI configuration register.
95 Writes the 8-bit PCI configuration register specified by Address with the
96 value specified by Value. Value is returned. This function must guarantee
97 that all PCI read and write operations are serialized.
99 If Address > 0x0FFFFFFF, then ASSERT().
100 If the register specified by Address >= 0x100, then ASSERT().
102 @param Address Address that encodes the PCI Bus, Device, Function and
104 @param Value The value to write.
106 @return The value written to the PCI configuration register.
117 Performs a bitwise OR of an 8-bit PCI configuration register with
120 Reads the 8-bit PCI configuration register specified by Address, performs a
121 bitwise OR between the read result and the value specified by
122 OrData, and writes the result to the 8-bit PCI configuration register
123 specified by Address. The value written to the PCI configuration register is
124 returned. This function must guarantee that all PCI read and write operations
127 If Address > 0x0FFFFFFF, then ASSERT().
128 If the register specified by Address >= 0x100, then ASSERT().
130 @param Address Address that encodes the PCI Bus, Device, Function and
132 @param OrData The value to OR with the PCI configuration register.
134 @return The value written back to the PCI configuration register.
145 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
148 Reads the 8-bit PCI configuration register specified by Address, performs a
149 bitwise AND between the read result and the value specified by AndData, and
150 writes the result to the 8-bit PCI configuration register specified by
151 Address. The value written to the PCI configuration register is returned.
152 This function must guarantee that all PCI read and write operations are
155 If Address > 0x0FFFFFFF, then ASSERT().
156 If the register specified by Address >= 0x100, then ASSERT().
158 @param Address Address that encodes the PCI Bus, Device, Function and
160 @param AndData The value to AND with the PCI configuration register.
162 @return The value written back to the PCI configuration register.
173 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
174 value, followed a bitwise OR with another 8-bit value.
176 Reads the 8-bit PCI configuration register specified by Address, performs a
177 bitwise AND between the read result and the value specified by AndData,
178 performs a bitwise OR between the result of the AND operation and
179 the value specified by OrData, and writes the result to the 8-bit PCI
180 configuration register specified by Address. The value written to the PCI
181 configuration register is returned. This function must guarantee that all PCI
182 read and write operations are serialized.
184 If Address > 0x0FFFFFFF, then ASSERT().
185 If the register specified by Address >= 0x100, then ASSERT().
187 @param Address Address that encodes the PCI Bus, Device, Function and
189 @param AndData The value to AND with the PCI configuration register.
190 @param OrData The value to OR with the result of the AND operation.
192 @return The value written back to the PCI configuration register.
204 Reads a bit field of a PCI configuration register.
206 Reads the bit field in an 8-bit PCI configuration register. The bit field is
207 specified by the StartBit and the EndBit. The value of the bit field is
210 If Address > 0x0FFFFFFF, then ASSERT().
211 If the register specified by Address >= 0x100, then ASSERT().
212 If StartBit is greater than 7, then ASSERT().
213 If EndBit is greater than 7, then ASSERT().
214 If EndBit is less than StartBit, then ASSERT().
216 @param Address PCI configuration register to read.
217 @param StartBit The ordinal of the least significant bit in the bit field.
219 @param EndBit The ordinal of the most significant bit in the bit field.
222 @return The value of the bit field read from the PCI configuration register.
227 PciCf8BitFieldRead8 (
234 Writes a bit field to a PCI configuration register.
236 Writes Value to the bit field of the PCI configuration register. The bit
237 field is specified by the StartBit and the EndBit. All other bits in the
238 destination PCI configuration register are preserved. The new value of the
239 8-bit register is returned.
241 If Address > 0x0FFFFFFF, then ASSERT().
242 If the register specified by Address >= 0x100, then ASSERT().
243 If StartBit is greater than 7, then ASSERT().
244 If EndBit is greater than 7, then ASSERT().
245 If EndBit is less than StartBit, then ASSERT().
247 @param Address PCI configuration register to write.
248 @param StartBit The ordinal of the least significant bit in the bit field.
250 @param EndBit The ordinal of the most significant bit in the bit field.
252 @param Value New value of the bit field.
254 @return The value written back to the PCI configuration register.
259 PciCf8BitFieldWrite8 (
267 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
268 writes the result back to the bit field in the 8-bit port.
270 Reads the 8-bit PCI configuration register specified by Address, performs a
271 bitwise OR between the read result and the value specified by
272 OrData, and writes the result to the 8-bit PCI configuration register
273 specified by Address. The value written to the PCI configuration register is
274 returned. This function must guarantee that all PCI read and write operations
275 are serialized. Extra left bits in OrData are stripped.
277 If Address > 0x0FFFFFFF, then ASSERT().
278 If the register specified by Address >= 0x100, then ASSERT().
279 If StartBit is greater than 7, then ASSERT().
280 If EndBit is greater than 7, then ASSERT().
281 If EndBit is less than StartBit, then ASSERT().
283 @param Address PCI configuration register to write.
284 @param StartBit The ordinal of the least significant bit in the bit field.
286 @param EndBit The ordinal of the most significant bit in the bit field.
288 @param OrData The value to OR with the PCI configuration register.
290 @return The value written back to the PCI configuration register.
303 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
304 AND, and writes the result back to the bit field in the 8-bit register.
306 Reads the 8-bit PCI configuration register specified by Address, performs a
307 bitwise AND between the read result and the value specified by AndData, and
308 writes the result to the 8-bit PCI configuration register specified by
309 Address. The value written to the PCI configuration register is returned.
310 This function must guarantee that all PCI read and write operations are
311 serialized. Extra left bits in AndData are stripped.
313 If Address > 0x0FFFFFFF, then ASSERT().
314 If the register specified by Address >= 0x100, then ASSERT().
315 If StartBit is greater than 7, then ASSERT().
316 If EndBit is greater than 7, then ASSERT().
317 If EndBit is less than StartBit, then ASSERT().
319 @param Address PCI configuration register to write.
320 @param StartBit The ordinal of the least significant bit in the bit field.
322 @param EndBit The ordinal of the most significant bit in the bit field.
324 @param AndData The value to AND with the PCI configuration register.
326 @return The value written back to the PCI configuration register.
339 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
340 bitwise OR, and writes the result back to the bit field in the
343 Reads the 8-bit PCI configuration register specified by Address, performs a
344 bitwise AND followed by a bitwise OR between the read result and
345 the value specified by AndData, and writes the result to the 8-bit PCI
346 configuration register specified by Address. The value written to the PCI
347 configuration register is returned. This function must guarantee that all PCI
348 read and write operations are serialized. Extra left bits in both AndData and
351 If Address > 0x0FFFFFFF, then ASSERT().
352 If the register specified by Address >= 0x100, then ASSERT().
353 If StartBit is greater than 7, then ASSERT().
354 If EndBit is greater than 7, then ASSERT().
355 If EndBit is less than StartBit, then ASSERT().
357 @param Address PCI configuration register to write.
358 @param StartBit The ordinal of the least significant bit in the bit field.
360 @param EndBit The ordinal of the most significant bit in the bit field.
362 @param AndData The value to AND with the PCI configuration register.
363 @param OrData The value to OR with the result of the AND operation.
365 @return The value written back to the PCI configuration register.
370 PciCf8BitFieldAndThenOr8 (
379 Reads a 16-bit PCI configuration register.
381 Reads and returns the 16-bit PCI configuration register specified by Address.
382 This function must guarantee that all PCI read and write operations are
385 If Address > 0x0FFFFFFF, then ASSERT().
386 If Address is not aligned on a 16-bit boundary, then ASSERT().
387 If the register specified by Address >= 0x100, then ASSERT().
389 @param Address Address that encodes the PCI Bus, Device, Function and
392 @return The read value from the PCI configuration register.
402 Writes a 16-bit PCI configuration register.
404 Writes the 16-bit PCI configuration register specified by Address with the
405 value specified by Value. Value is returned. This function must guarantee
406 that all PCI read and write operations are serialized.
408 If Address > 0x0FFFFFFF, then ASSERT().
409 If Address is not aligned on a 16-bit boundary, then ASSERT().
410 If the register specified by Address >= 0x100, then ASSERT().
412 @param Address Address that encodes the PCI Bus, Device, Function and
414 @param Value The value to write.
416 @return The value written to the PCI configuration register.
427 Performs a bitwise OR of a 16-bit PCI configuration register with
430 Reads the 16-bit PCI configuration register specified by Address, performs a
431 bitwise OR between the read result and the value specified by
432 OrData, and writes the result to the 16-bit PCI configuration register
433 specified by Address. The value written to the PCI configuration register is
434 returned. This function must guarantee that all PCI read and write operations
437 If Address > 0x0FFFFFFF, then ASSERT().
438 If Address is not aligned on a 16-bit boundary, then ASSERT().
439 If the register specified by Address >= 0x100, then ASSERT().
441 @param Address Address that encodes the PCI Bus, Device, Function and
443 @param OrData The value to OR with the PCI configuration register.
445 @return The value written back to the PCI configuration register.
456 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
459 Reads the 16-bit PCI configuration register specified by Address, performs a
460 bitwise AND between the read result and the value specified by AndData, and
461 writes the result to the 16-bit PCI configuration register specified by
462 Address. The value written to the PCI configuration register is returned.
463 This function must guarantee that all PCI read and write operations are
466 If Address > 0x0FFFFFFF, then ASSERT().
467 If Address is not aligned on a 16-bit boundary, then ASSERT().
468 If the register specified by Address >= 0x100, then ASSERT().
470 @param Address Address that encodes the PCI Bus, Device, Function and
472 @param AndData The value to AND with the PCI configuration register.
474 @return The value written back to the PCI configuration register.
485 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
486 value, followed a bitwise OR with another 16-bit value.
488 Reads the 16-bit PCI configuration register specified by Address, performs a
489 bitwise AND between the read result and the value specified by AndData,
490 performs a bitwise OR between the result of the AND operation and
491 the value specified by OrData, and writes the result to the 16-bit PCI
492 configuration register specified by Address. The value written to the PCI
493 configuration register is returned. This function must guarantee that all PCI
494 read and write operations are serialized.
496 If Address > 0x0FFFFFFF, then ASSERT().
497 If Address is not aligned on a 16-bit boundary, then ASSERT().
498 If the register specified by Address >= 0x100, then ASSERT().
500 @param Address Address that encodes the PCI Bus, Device, Function and
502 @param AndData The value to AND with the PCI configuration register.
503 @param OrData The value to OR with the result of the AND operation.
505 @return The value written back to the PCI configuration register.
517 Reads a bit field of a PCI configuration register.
519 Reads the bit field in a 16-bit PCI configuration register. The bit field is
520 specified by the StartBit and the EndBit. The value of the bit field is
523 If Address > 0x0FFFFFFF, then ASSERT().
524 If Address is not aligned on a 16-bit boundary, then ASSERT().
525 If the register specified by Address >= 0x100, then ASSERT().
526 If StartBit is greater than 15, then ASSERT().
527 If EndBit is greater than 15, then ASSERT().
528 If EndBit is less than StartBit, then ASSERT().
530 @param Address PCI configuration register to read.
531 @param StartBit The ordinal of the least significant bit in the bit field.
533 @param EndBit The ordinal of the most significant bit in the bit field.
536 @return The value of the bit field read from the PCI configuration register.
541 PciCf8BitFieldRead16 (
548 Writes a bit field to a PCI configuration register.
550 Writes Value to the bit field of the PCI configuration register. The bit
551 field is specified by the StartBit and the EndBit. All other bits in the
552 destination PCI configuration register are preserved. The new value of the
553 16-bit register is returned.
555 If Address > 0x0FFFFFFF, then ASSERT().
556 If Address is not aligned on a 16-bit boundary, then ASSERT().
557 If the register specified by Address >= 0x100, then ASSERT().
558 If StartBit is greater than 15, then ASSERT().
559 If EndBit is greater than 15, then ASSERT().
560 If EndBit is less than StartBit, then ASSERT().
562 @param Address PCI configuration register to write.
563 @param StartBit The ordinal of the least significant bit in the bit field.
565 @param EndBit The ordinal of the most significant bit in the bit field.
567 @param Value New value of the bit field.
569 @return The value written back to the PCI configuration register.
574 PciCf8BitFieldWrite16 (
582 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
583 writes the result back to the bit field in the 16-bit port.
585 Reads the 16-bit PCI configuration register specified by Address, performs a
586 bitwise OR between the read result and the value specified by
587 OrData, and writes the result to the 16-bit PCI configuration register
588 specified by Address. The value written to the PCI configuration register is
589 returned. This function must guarantee that all PCI read and write operations
590 are serialized. Extra left bits in OrData are stripped.
592 If Address > 0x0FFFFFFF, then ASSERT().
593 If Address is not aligned on a 16-bit boundary, then ASSERT().
594 If the register specified by Address >= 0x100, then ASSERT().
595 If StartBit is greater than 15, then ASSERT().
596 If EndBit is greater than 15, then ASSERT().
597 If EndBit is less than StartBit, then ASSERT().
599 @param Address PCI configuration register to write.
600 @param StartBit The ordinal of the least significant bit in the bit field.
602 @param EndBit The ordinal of the most significant bit in the bit field.
604 @param OrData The value to OR with the PCI configuration register.
606 @return The value written back to the PCI configuration register.
619 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
620 AND, and writes the result back to the bit field in the 16-bit register.
622 Reads the 16-bit PCI configuration register specified by Address, performs a
623 bitwise AND between the read result and the value specified by AndData, and
624 writes the result to the 16-bit PCI configuration register specified by
625 Address. The value written to the PCI configuration register is returned.
626 This function must guarantee that all PCI read and write operations are
627 serialized. Extra left bits in AndData are stripped.
629 If Address > 0x0FFFFFFF, then ASSERT().
630 If Address is not aligned on a 16-bit boundary, then ASSERT().
631 If the register specified by Address >= 0x100, then ASSERT().
632 If StartBit is greater than 15, then ASSERT().
633 If EndBit is greater than 15, then ASSERT().
634 If EndBit is less than StartBit, then ASSERT().
636 @param Address PCI configuration register to write.
637 @param StartBit The ordinal of the least significant bit in the bit field.
639 @param EndBit The ordinal of the most significant bit in the bit field.
641 @param AndData The value to AND with the PCI configuration register.
643 @return The value written back to the PCI configuration register.
648 PciCf8BitFieldAnd16 (
656 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
657 bitwise OR, and writes the result back to the bit field in the
660 Reads the 16-bit PCI configuration register specified by Address, performs a
661 bitwise AND followed by a bitwise OR between the read result and
662 the value specified by AndData, and writes the result to the 16-bit PCI
663 configuration register specified by Address. The value written to the PCI
664 configuration register is returned. This function must guarantee that all PCI
665 read and write operations are serialized. Extra left bits in both AndData and
668 If Address > 0x0FFFFFFF, then ASSERT().
669 If Address is not aligned on a 16-bit boundary, then ASSERT().
670 If the register specified by Address >= 0x100, then ASSERT().
671 If StartBit is greater than 15, then ASSERT().
672 If EndBit is greater than 15, then ASSERT().
673 If EndBit is less than StartBit, then ASSERT().
675 @param Address PCI configuration register to write.
676 @param StartBit The ordinal of the least significant bit in the bit field.
678 @param EndBit The ordinal of the most significant bit in the bit field.
680 @param AndData The value to AND with the PCI configuration register.
681 @param OrData The value to OR with the result of the AND operation.
683 @return The value written back to the PCI configuration register.
688 PciCf8BitFieldAndThenOr16 (
697 Reads a 32-bit PCI configuration register.
699 Reads and returns the 32-bit PCI configuration register specified by Address.
700 This function must guarantee that all PCI read and write operations are
703 If Address > 0x0FFFFFFF, then ASSERT().
704 If Address is not aligned on a 32-bit boundary, then ASSERT().
705 If the register specified by Address >= 0x100, then ASSERT().
707 @param Address Address that encodes the PCI Bus, Device, Function and
710 @return The read value from the PCI configuration register.
720 Writes a 32-bit PCI configuration register.
722 Writes the 32-bit PCI configuration register specified by Address with the
723 value specified by Value. Value is returned. This function must guarantee
724 that all PCI read and write operations are serialized.
726 If Address > 0x0FFFFFFF, then ASSERT().
727 If Address is not aligned on a 32-bit boundary, then ASSERT().
728 If the register specified by Address >= 0x100, then ASSERT().
730 @param Address Address that encodes the PCI Bus, Device, Function and
732 @param Value The value to write.
734 @return The value written to the PCI configuration register.
745 Performs a bitwise OR of a 32-bit PCI configuration register with
748 Reads the 32-bit PCI configuration register specified by Address, performs a
749 bitwise OR between the read result and the value specified by
750 OrData, and writes the result to the 32-bit PCI configuration register
751 specified by Address. The value written to the PCI configuration register is
752 returned. This function must guarantee that all PCI read and write operations
755 If Address > 0x0FFFFFFF, then ASSERT().
756 If Address is not aligned on a 32-bit boundary, then ASSERT().
757 If the register specified by Address >= 0x100, then ASSERT().
759 @param Address Address that encodes the PCI Bus, Device, Function and
761 @param OrData The value to OR with the PCI configuration register.
763 @return The value written back to the PCI configuration register.
774 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
777 Reads the 32-bit PCI configuration register specified by Address, performs a
778 bitwise AND between the read result and the value specified by AndData, and
779 writes the result to the 32-bit PCI configuration register specified by
780 Address. The value written to the PCI configuration register is returned.
781 This function must guarantee that all PCI read and write operations are
784 If Address > 0x0FFFFFFF, then ASSERT().
785 If Address is not aligned on a 32-bit boundary, then ASSERT().
786 If the register specified by Address >= 0x100, then ASSERT().
788 @param Address Address that encodes the PCI Bus, Device, Function and
790 @param AndData The value to AND with the PCI configuration register.
792 @return The value written back to the PCI configuration register.
803 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
804 value, followed a bitwise OR with another 32-bit value.
806 Reads the 32-bit PCI configuration register specified by Address, performs a
807 bitwise AND between the read result and the value specified by AndData,
808 performs a bitwise OR between the result of the AND operation and
809 the value specified by OrData, and writes the result to the 32-bit PCI
810 configuration register specified by Address. The value written to the PCI
811 configuration register is returned. This function must guarantee that all PCI
812 read and write operations are serialized.
814 If Address > 0x0FFFFFFF, then ASSERT().
815 If Address is not aligned on a 32-bit boundary, then ASSERT().
816 If the register specified by Address >= 0x100, then ASSERT().
818 @param Address Address that encodes the PCI Bus, Device, Function and
820 @param AndData The value to AND with the PCI configuration register.
821 @param OrData The value to OR with the result of the AND operation.
823 @return The value written back to the PCI configuration register.
835 Reads a bit field of a PCI configuration register.
837 Reads the bit field in a 32-bit PCI configuration register. The bit field is
838 specified by the StartBit and the EndBit. The value of the bit field is
841 If Address > 0x0FFFFFFF, then ASSERT().
842 If Address is not aligned on a 32-bit boundary, then ASSERT().
843 If the register specified by Address >= 0x100, then ASSERT().
844 If StartBit is greater than 31, then ASSERT().
845 If EndBit is greater than 31, then ASSERT().
846 If EndBit is less than StartBit, then ASSERT().
848 @param Address PCI configuration register to read.
849 @param StartBit The ordinal of the least significant bit in the bit field.
851 @param EndBit The ordinal of the most significant bit in the bit field.
854 @return The value of the bit field read from the PCI configuration register.
859 PciCf8BitFieldRead32 (
866 Writes a bit field to a PCI configuration register.
868 Writes Value to the bit field of the PCI configuration register. The bit
869 field is specified by the StartBit and the EndBit. All other bits in the
870 destination PCI configuration register are preserved. The new value of the
871 32-bit register is returned.
873 If Address > 0x0FFFFFFF, then ASSERT().
874 If Address is not aligned on a 32-bit boundary, then ASSERT().
875 If the register specified by Address >= 0x100, then ASSERT().
876 If StartBit is greater than 31, then ASSERT().
877 If EndBit is greater than 31, then ASSERT().
878 If EndBit is less than StartBit, then ASSERT().
880 @param Address PCI configuration register to write.
881 @param StartBit The ordinal of the least significant bit in the bit field.
883 @param EndBit The ordinal of the most significant bit in the bit field.
885 @param Value New value of the bit field.
887 @return The value written back to the PCI configuration register.
892 PciCf8BitFieldWrite32 (
900 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
901 writes the result back to the bit field in the 32-bit port.
903 Reads the 32-bit PCI configuration register specified by Address, performs a
904 bitwise OR between the read result and the value specified by
905 OrData, and writes the result to the 32-bit PCI configuration register
906 specified by Address. The value written to the PCI configuration register is
907 returned. This function must guarantee that all PCI read and write operations
908 are serialized. Extra left bits in OrData are stripped.
910 If Address > 0x0FFFFFFF, then ASSERT().
911 If Address is not aligned on a 32-bit boundary, then ASSERT().
912 If the register specified by Address >= 0x100, then ASSERT().
913 If StartBit is greater than 31, then ASSERT().
914 If EndBit is greater than 31, then ASSERT().
915 If EndBit is less than StartBit, then ASSERT().
917 @param Address PCI configuration register to write.
918 @param StartBit The ordinal of the least significant bit in the bit field.
920 @param EndBit The ordinal of the most significant bit in the bit field.
922 @param OrData The value to OR with the PCI configuration register.
924 @return The value written back to the PCI configuration register.
937 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
938 AND, and writes the result back to the bit field in the 32-bit register.
940 Reads the 32-bit PCI configuration register specified by Address, performs a
941 bitwise AND between the read result and the value specified by AndData, and
942 writes the result to the 32-bit PCI configuration register specified by
943 Address. The value written to the PCI configuration register is returned.
944 This function must guarantee that all PCI read and write operations are
945 serialized. Extra left bits in AndData are stripped.
947 If Address > 0x0FFFFFFF, then ASSERT().
948 If Address is not aligned on a 32-bit boundary, then ASSERT().
949 If the register specified by Address >= 0x100, then ASSERT().
950 If StartBit is greater than 31, then ASSERT().
951 If EndBit is greater than 31, then ASSERT().
952 If EndBit is less than StartBit, then ASSERT().
954 @param Address PCI configuration register to write.
955 @param StartBit The ordinal of the least significant bit in the bit field.
957 @param EndBit The ordinal of the most significant bit in the bit field.
959 @param AndData The value to AND with the PCI configuration register.
961 @return The value written back to the PCI configuration register.
966 PciCf8BitFieldAnd32 (
974 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
975 bitwise OR, and writes the result back to the bit field in the
978 Reads the 32-bit PCI configuration register specified by Address, performs a
979 bitwise AND followed by a bitwise OR between the read result and
980 the value specified by AndData, and writes the result to the 32-bit PCI
981 configuration register specified by Address. The value written to the PCI
982 configuration register is returned. This function must guarantee that all PCI
983 read and write operations are serialized. Extra left bits in both AndData and
986 If Address > 0x0FFFFFFF, then ASSERT().
987 If Address is not aligned on a 32-bit boundary, then ASSERT().
988 If the register specified by Address >= 0x100, then ASSERT().
989 If StartBit is greater than 31, then ASSERT().
990 If EndBit is greater than 31, then ASSERT().
991 If EndBit is less than StartBit, then ASSERT().
993 @param Address PCI configuration register to write.
994 @param StartBit The ordinal of the least significant bit in the bit field.
996 @param EndBit The ordinal of the most significant bit in the bit field.
998 @param AndData The value to AND with the PCI configuration register.
999 @param OrData The value to OR with the result of the AND operation.
1001 @return The value written back to the PCI configuration register.
1006 PciCf8BitFieldAndThenOr32 (
1015 Reads a range of PCI configuration registers into a caller supplied buffer.
1017 Reads the range of PCI configuration registers specified by StartAddress and
1018 Size into the buffer specified by Buffer. This function only allows the PCI
1019 configuration registers from a single PCI function to be read. Size is
1020 returned. When possible 32-bit PCI configuration read cycles are used to read
1021 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1022 and 16-bit PCI configuration read cycles may be used at the beginning and the
1025 If StartAddress > 0x0FFFFFFF, then ASSERT().
1026 If the register specified by StartAddress >= 0x100, then ASSERT().
1027 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1028 If Size > 0 and Buffer is NULL, then ASSERT().
1030 @param StartAddress Starting address that encodes the PCI Bus, Device,
1031 Function and Register.
1032 @param Size Size in bytes of the transfer.
1033 @param Buffer Pointer to a buffer receiving the data read.
1035 @return Size read from StartAddress.
1041 IN UINTN StartAddress
,
1047 Copies the data in a caller supplied buffer to a specified range of PCI
1048 configuration space.
1050 Writes the range of PCI configuration registers specified by StartAddress and
1051 Size from the buffer specified by Buffer. This function only allows the PCI
1052 configuration registers from a single PCI function to be written. Size is
1053 returned. When possible 32-bit PCI configuration write cycles are used to
1054 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1055 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1056 and the end of the range.
1058 If StartAddress > 0x0FFFFFFF, then ASSERT().
1059 If the register specified by StartAddress >= 0x100, then ASSERT().
1060 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1061 If Size > 0 and Buffer is NULL, then ASSERT().
1063 @param StartAddress Starting address that encodes the PCI Bus, Device,
1064 Function and Register.
1065 @param Size Size in bytes of the transfer.
1066 @param Buffer Pointer to a buffer containing the data to write.
1068 @return Size written to StartAddress.
1074 IN UINTN StartAddress
,