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2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be though I/O ports 0xCF8 and 0xCFC. This library only allows
6 access to PCI Segment #0.
8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __PCI_CF8_LIB_H__
20 #define __PCI_CF8_LIB_H__
24 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
25 address that can be passed to the PCI Library functions.
27 Computes an address that is compatible with the PCI Library functions. The
28 unused upper bits of Bus, Device, Function and Register are stripped prior to
29 the generation of the address.
31 @param Bus PCI Bus number. Range 0..255.
32 @param Device PCI Device number. Range 0..31.
33 @param Function PCI Function number. Range 0..7.
34 @param Register PCI Register number. Range 0..255.
36 @return The encode PCI address.
39 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
40 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
43 Registers a PCI device so PCI configuration registers may be accessed after
44 SetVirtualAddressMap().
46 Registers the PCI device specified by Address so all the PCI configuration registers
47 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
49 If Address > 0x0FFFFFFF, then ASSERT().
51 @param Address Address that encodes the PCI Bus, Device, Function and
54 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
55 @retval RETURN_UNSUPPORTED An attempt was made to call this function
56 after ExitBootServices().
57 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
58 at runtime could not be mapped.
59 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
60 complete the registration.
65 PciCf8RegisterForRuntimeAccess (
70 Reads an 8-bit PCI configuration register.
72 Reads and returns the 8-bit PCI configuration register specified by Address.
73 This function must guarantee that all PCI read and write operations are
76 If Address > 0x0FFFFFFF, then ASSERT().
77 If the register specified by Address >= 0x100, then ASSERT().
79 @param Address Address that encodes the PCI Bus, Device, Function and
82 @return The read value from the PCI configuration register.
92 Writes an 8-bit PCI configuration register.
94 Writes the 8-bit PCI configuration register specified by Address with the
95 value specified by Value. Value is returned. This function must guarantee
96 that all PCI read and write operations are serialized.
98 If Address > 0x0FFFFFFF, then ASSERT().
99 If the register specified by Address >= 0x100, then ASSERT().
101 @param Address Address that encodes the PCI Bus, Device, Function and
103 @param Value The value to write.
105 @return The value written to the PCI configuration register.
116 Performs a bitwise OR of an 8-bit PCI configuration register with
119 Reads the 8-bit PCI configuration register specified by Address, performs a
120 bitwise OR between the read result and the value specified by
121 OrData, and writes the result to the 8-bit PCI configuration register
122 specified by Address. The value written to the PCI configuration register is
123 returned. This function must guarantee that all PCI read and write operations
126 If Address > 0x0FFFFFFF, then ASSERT().
127 If the register specified by Address >= 0x100, then ASSERT().
129 @param Address Address that encodes the PCI Bus, Device, Function and
131 @param OrData The value to OR with the PCI configuration register.
133 @return The value written back to the PCI configuration register.
144 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
147 Reads the 8-bit PCI configuration register specified by Address, performs a
148 bitwise AND between the read result and the value specified by AndData, and
149 writes the result to the 8-bit PCI configuration register specified by
150 Address. The value written to the PCI configuration register is returned.
151 This function must guarantee that all PCI read and write operations are
154 If Address > 0x0FFFFFFF, then ASSERT().
155 If the register specified by Address >= 0x100, then ASSERT().
157 @param Address Address that encodes the PCI Bus, Device, Function and
159 @param AndData The value to AND with the PCI configuration register.
161 @return The value written back to the PCI configuration register.
172 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
173 value, followed a bitwise OR with another 8-bit value.
175 Reads the 8-bit PCI configuration register specified by Address, performs a
176 bitwise AND between the read result and the value specified by AndData,
177 performs a bitwise OR between the result of the AND operation and
178 the value specified by OrData, and writes the result to the 8-bit PCI
179 configuration register specified by Address. The value written to the PCI
180 configuration register is returned. This function must guarantee that all PCI
181 read and write operations are serialized.
183 If Address > 0x0FFFFFFF, then ASSERT().
184 If the register specified by Address >= 0x100, then ASSERT().
186 @param Address Address that encodes the PCI Bus, Device, Function and
188 @param AndData The value to AND with the PCI configuration register.
189 @param OrData The value to OR with the result of the AND operation.
191 @return The value written back to the PCI configuration register.
203 Reads a bit field of a PCI configuration register.
205 Reads the bit field in an 8-bit PCI configuration register. The bit field is
206 specified by the StartBit and the EndBit. The value of the bit field is
209 If Address > 0x0FFFFFFF, then ASSERT().
210 If the register specified by Address >= 0x100, then ASSERT().
211 If StartBit is greater than 7, then ASSERT().
212 If EndBit is greater than 7, then ASSERT().
213 If EndBit is less than StartBit, then ASSERT().
215 @param Address PCI configuration register to read.
216 @param StartBit The ordinal of the least significant bit in the bit field.
218 @param EndBit The ordinal of the most significant bit in the bit field.
221 @return The value of the bit field read from the PCI configuration register.
226 PciCf8BitFieldRead8 (
233 Writes a bit field to a PCI configuration register.
235 Writes Value to the bit field of the PCI configuration register. The bit
236 field is specified by the StartBit and the EndBit. All other bits in the
237 destination PCI configuration register are preserved. The new value of the
238 8-bit register is returned.
240 If Address > 0x0FFFFFFF, then ASSERT().
241 If the register specified by Address >= 0x100, then ASSERT().
242 If StartBit is greater than 7, then ASSERT().
243 If EndBit is greater than 7, then ASSERT().
244 If EndBit is less than StartBit, then ASSERT().
246 @param Address PCI configuration register to write.
247 @param StartBit The ordinal of the least significant bit in the bit field.
249 @param EndBit The ordinal of the most significant bit in the bit field.
251 @param Value New value of the bit field.
253 @return The value written back to the PCI configuration register.
258 PciCf8BitFieldWrite8 (
266 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
267 writes the result back to the bit field in the 8-bit port.
269 Reads the 8-bit PCI configuration register specified by Address, performs a
270 bitwise OR between the read result and the value specified by
271 OrData, and writes the result to the 8-bit PCI configuration register
272 specified by Address. The value written to the PCI configuration register is
273 returned. This function must guarantee that all PCI read and write operations
274 are serialized. Extra left bits in OrData are stripped.
276 If Address > 0x0FFFFFFF, then ASSERT().
277 If the register specified by Address >= 0x100, then ASSERT().
278 If StartBit is greater than 7, then ASSERT().
279 If EndBit is greater than 7, then ASSERT().
280 If EndBit is less than StartBit, then ASSERT().
282 @param Address PCI configuration register to write.
283 @param StartBit The ordinal of the least significant bit in the bit field.
285 @param EndBit The ordinal of the most significant bit in the bit field.
287 @param OrData The value to OR with the PCI configuration register.
289 @return The value written back to the PCI configuration register.
302 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
303 AND, and writes the result back to the bit field in the 8-bit register.
305 Reads the 8-bit PCI configuration register specified by Address, performs a
306 bitwise AND between the read result and the value specified by AndData, and
307 writes the result to the 8-bit PCI configuration register specified by
308 Address. The value written to the PCI configuration register is returned.
309 This function must guarantee that all PCI read and write operations are
310 serialized. Extra left bits in AndData are stripped.
312 If Address > 0x0FFFFFFF, then ASSERT().
313 If the register specified by Address >= 0x100, then ASSERT().
314 If StartBit is greater than 7, then ASSERT().
315 If EndBit is greater than 7, then ASSERT().
316 If EndBit is less than StartBit, then ASSERT().
318 @param Address PCI configuration register to write.
319 @param StartBit The ordinal of the least significant bit in the bit field.
321 @param EndBit The ordinal of the most significant bit in the bit field.
323 @param AndData The value to AND with the PCI configuration register.
325 @return The value written back to the PCI configuration register.
338 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
339 bitwise OR, and writes the result back to the bit field in the
342 Reads the 8-bit PCI configuration register specified by Address, performs a
343 bitwise AND followed by a bitwise OR between the read result and
344 the value specified by AndData, and writes the result to the 8-bit PCI
345 configuration register specified by Address. The value written to the PCI
346 configuration register is returned. This function must guarantee that all PCI
347 read and write operations are serialized. Extra left bits in both AndData and
350 If Address > 0x0FFFFFFF, then ASSERT().
351 If the register specified by Address >= 0x100, then ASSERT().
352 If StartBit is greater than 7, then ASSERT().
353 If EndBit is greater than 7, then ASSERT().
354 If EndBit is less than StartBit, then ASSERT().
356 @param Address PCI configuration register to write.
357 @param StartBit The ordinal of the least significant bit in the bit field.
359 @param EndBit The ordinal of the most significant bit in the bit field.
361 @param AndData The value to AND with the PCI configuration register.
362 @param OrData The value to OR with the result of the AND operation.
364 @return The value written back to the PCI configuration register.
369 PciCf8BitFieldAndThenOr8 (
378 Reads a 16-bit PCI configuration register.
380 Reads and returns the 16-bit PCI configuration register specified by Address.
381 This function must guarantee that all PCI read and write operations are
384 If Address > 0x0FFFFFFF, then ASSERT().
385 If Address is not aligned on a 16-bit boundary, then ASSERT().
386 If the register specified by Address >= 0x100, then ASSERT().
388 @param Address Address that encodes the PCI Bus, Device, Function and
391 @return The read value from the PCI configuration register.
401 Writes a 16-bit PCI configuration register.
403 Writes the 16-bit PCI configuration register specified by Address with the
404 value specified by Value. Value is returned. This function must guarantee
405 that all PCI read and write operations are serialized.
407 If Address > 0x0FFFFFFF, then ASSERT().
408 If Address is not aligned on a 16-bit boundary, then ASSERT().
409 If the register specified by Address >= 0x100, then ASSERT().
411 @param Address Address that encodes the PCI Bus, Device, Function and
413 @param Value The value to write.
415 @return The value written to the PCI configuration register.
426 Performs a bitwise OR of a 16-bit PCI configuration register with
429 Reads the 16-bit PCI configuration register specified by Address, performs a
430 bitwise OR between the read result and the value specified by
431 OrData, and writes the result to the 16-bit PCI configuration register
432 specified by Address. The value written to the PCI configuration register is
433 returned. This function must guarantee that all PCI read and write operations
436 If Address > 0x0FFFFFFF, then ASSERT().
437 If Address is not aligned on a 16-bit boundary, then ASSERT().
438 If the register specified by Address >= 0x100, then ASSERT().
440 @param Address Address that encodes the PCI Bus, Device, Function and
442 @param OrData The value to OR with the PCI configuration register.
444 @return The value written back to the PCI configuration register.
455 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
458 Reads the 16-bit PCI configuration register specified by Address, performs a
459 bitwise AND between the read result and the value specified by AndData, and
460 writes the result to the 16-bit PCI configuration register specified by
461 Address. The value written to the PCI configuration register is returned.
462 This function must guarantee that all PCI read and write operations are
465 If Address > 0x0FFFFFFF, then ASSERT().
466 If Address is not aligned on a 16-bit boundary, then ASSERT().
467 If the register specified by Address >= 0x100, then ASSERT().
469 @param Address Address that encodes the PCI Bus, Device, Function and
471 @param AndData The value to AND with the PCI configuration register.
473 @return The value written back to the PCI configuration register.
484 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
485 value, followed a bitwise OR with another 16-bit value.
487 Reads the 16-bit PCI configuration register specified by Address, performs a
488 bitwise AND between the read result and the value specified by AndData,
489 performs a bitwise OR between the result of the AND operation and
490 the value specified by OrData, and writes the result to the 16-bit PCI
491 configuration register specified by Address. The value written to the PCI
492 configuration register is returned. This function must guarantee that all PCI
493 read and write operations are serialized.
495 If Address > 0x0FFFFFFF, then ASSERT().
496 If Address is not aligned on a 16-bit boundary, then ASSERT().
497 If the register specified by Address >= 0x100, then ASSERT().
499 @param Address Address that encodes the PCI Bus, Device, Function and
501 @param AndData The value to AND with the PCI configuration register.
502 @param OrData The value to OR with the result of the AND operation.
504 @return The value written back to the PCI configuration register.
516 Reads a bit field of a PCI configuration register.
518 Reads the bit field in a 16-bit PCI configuration register. The bit field is
519 specified by the StartBit and the EndBit. The value of the bit field is
522 If Address > 0x0FFFFFFF, then ASSERT().
523 If Address is not aligned on a 16-bit boundary, then ASSERT().
524 If the register specified by Address >= 0x100, then ASSERT().
525 If StartBit is greater than 15, then ASSERT().
526 If EndBit is greater than 15, then ASSERT().
527 If EndBit is less than StartBit, then ASSERT().
529 @param Address PCI configuration register to read.
530 @param StartBit The ordinal of the least significant bit in the bit field.
532 @param EndBit The ordinal of the most significant bit in the bit field.
535 @return The value of the bit field read from the PCI configuration register.
540 PciCf8BitFieldRead16 (
547 Writes a bit field to a PCI configuration register.
549 Writes Value to the bit field of the PCI configuration register. The bit
550 field is specified by the StartBit and the EndBit. All other bits in the
551 destination PCI configuration register are preserved. The new value of the
552 16-bit register is returned.
554 If Address > 0x0FFFFFFF, then ASSERT().
555 If Address is not aligned on a 16-bit boundary, then ASSERT().
556 If the register specified by Address >= 0x100, then ASSERT().
557 If StartBit is greater than 15, then ASSERT().
558 If EndBit is greater than 15, then ASSERT().
559 If EndBit is less than StartBit, then ASSERT().
561 @param Address PCI configuration register to write.
562 @param StartBit The ordinal of the least significant bit in the bit field.
564 @param EndBit The ordinal of the most significant bit in the bit field.
566 @param Value New value of the bit field.
568 @return The value written back to the PCI configuration register.
573 PciCf8BitFieldWrite16 (
581 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
582 writes the result back to the bit field in the 16-bit port.
584 Reads the 16-bit PCI configuration register specified by Address, performs a
585 bitwise OR between the read result and the value specified by
586 OrData, and writes the result to the 16-bit PCI configuration register
587 specified by Address. The value written to the PCI configuration register is
588 returned. This function must guarantee that all PCI read and write operations
589 are serialized. Extra left bits in OrData are stripped.
591 If Address > 0x0FFFFFFF, then ASSERT().
592 If Address is not aligned on a 16-bit boundary, then ASSERT().
593 If the register specified by Address >= 0x100, then ASSERT().
594 If StartBit is greater than 15, then ASSERT().
595 If EndBit is greater than 15, then ASSERT().
596 If EndBit is less than StartBit, then ASSERT().
598 @param Address PCI configuration register to write.
599 @param StartBit The ordinal of the least significant bit in the bit field.
601 @param EndBit The ordinal of the most significant bit in the bit field.
603 @param OrData The value to OR with the PCI configuration register.
605 @return The value written back to the PCI configuration register.
618 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
619 AND, and writes the result back to the bit field in the 16-bit register.
621 Reads the 16-bit PCI configuration register specified by Address, performs a
622 bitwise AND between the read result and the value specified by AndData, and
623 writes the result to the 16-bit PCI configuration register specified by
624 Address. The value written to the PCI configuration register is returned.
625 This function must guarantee that all PCI read and write operations are
626 serialized. Extra left bits in AndData are stripped.
628 If Address > 0x0FFFFFFF, then ASSERT().
629 If Address is not aligned on a 16-bit boundary, then ASSERT().
630 If the register specified by Address >= 0x100, then ASSERT().
631 If StartBit is greater than 15, then ASSERT().
632 If EndBit is greater than 15, then ASSERT().
633 If EndBit is less than StartBit, then ASSERT().
635 @param Address PCI configuration register to write.
636 @param StartBit The ordinal of the least significant bit in the bit field.
638 @param EndBit The ordinal of the most significant bit in the bit field.
640 @param AndData The value to AND with the PCI configuration register.
642 @return The value written back to the PCI configuration register.
647 PciCf8BitFieldAnd16 (
655 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
656 bitwise OR, and writes the result back to the bit field in the
659 Reads the 16-bit PCI configuration register specified by Address, performs a
660 bitwise AND followed by a bitwise OR between the read result and
661 the value specified by AndData, and writes the result to the 16-bit PCI
662 configuration register specified by Address. The value written to the PCI
663 configuration register is returned. This function must guarantee that all PCI
664 read and write operations are serialized. Extra left bits in both AndData and
667 If Address > 0x0FFFFFFF, then ASSERT().
668 If Address is not aligned on a 16-bit boundary, then ASSERT().
669 If the register specified by Address >= 0x100, then ASSERT().
670 If StartBit is greater than 15, then ASSERT().
671 If EndBit is greater than 15, then ASSERT().
672 If EndBit is less than StartBit, then ASSERT().
674 @param Address PCI configuration register to write.
675 @param StartBit The ordinal of the least significant bit in the bit field.
677 @param EndBit The ordinal of the most significant bit in the bit field.
679 @param AndData The value to AND with the PCI configuration register.
680 @param OrData The value to OR with the result of the AND operation.
682 @return The value written back to the PCI configuration register.
687 PciCf8BitFieldAndThenOr16 (
696 Reads a 32-bit PCI configuration register.
698 Reads and returns the 32-bit PCI configuration register specified by Address.
699 This function must guarantee that all PCI read and write operations are
702 If Address > 0x0FFFFFFF, then ASSERT().
703 If Address is not aligned on a 32-bit boundary, then ASSERT().
704 If the register specified by Address >= 0x100, then ASSERT().
706 @param Address Address that encodes the PCI Bus, Device, Function and
709 @return The read value from the PCI configuration register.
719 Writes a 32-bit PCI configuration register.
721 Writes the 32-bit PCI configuration register specified by Address with the
722 value specified by Value. Value is returned. This function must guarantee
723 that all PCI read and write operations are serialized.
725 If Address > 0x0FFFFFFF, then ASSERT().
726 If Address is not aligned on a 32-bit boundary, then ASSERT().
727 If the register specified by Address >= 0x100, then ASSERT().
729 @param Address Address that encodes the PCI Bus, Device, Function and
731 @param Value The value to write.
733 @return The value written to the PCI configuration register.
744 Performs a bitwise OR of a 32-bit PCI configuration register with
747 Reads the 32-bit PCI configuration register specified by Address, performs a
748 bitwise OR between the read result and the value specified by
749 OrData, and writes the result to the 32-bit PCI configuration register
750 specified by Address. The value written to the PCI configuration register is
751 returned. This function must guarantee that all PCI read and write operations
754 If Address > 0x0FFFFFFF, then ASSERT().
755 If Address is not aligned on a 32-bit boundary, then ASSERT().
756 If the register specified by Address >= 0x100, then ASSERT().
758 @param Address Address that encodes the PCI Bus, Device, Function and
760 @param OrData The value to OR with the PCI configuration register.
762 @return The value written back to the PCI configuration register.
773 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
776 Reads the 32-bit PCI configuration register specified by Address, performs a
777 bitwise AND between the read result and the value specified by AndData, and
778 writes the result to the 32-bit PCI configuration register specified by
779 Address. The value written to the PCI configuration register is returned.
780 This function must guarantee that all PCI read and write operations are
783 If Address > 0x0FFFFFFF, then ASSERT().
784 If Address is not aligned on a 32-bit boundary, then ASSERT().
785 If the register specified by Address >= 0x100, then ASSERT().
787 @param Address Address that encodes the PCI Bus, Device, Function and
789 @param AndData The value to AND with the PCI configuration register.
791 @return The value written back to the PCI configuration register.
802 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
803 value, followed a bitwise OR with another 32-bit value.
805 Reads the 32-bit PCI configuration register specified by Address, performs a
806 bitwise AND between the read result and the value specified by AndData,
807 performs a bitwise OR between the result of the AND operation and
808 the value specified by OrData, and writes the result to the 32-bit PCI
809 configuration register specified by Address. The value written to the PCI
810 configuration register is returned. This function must guarantee that all PCI
811 read and write operations are serialized.
813 If Address > 0x0FFFFFFF, then ASSERT().
814 If Address is not aligned on a 32-bit boundary, then ASSERT().
815 If the register specified by Address >= 0x100, then ASSERT().
817 @param Address Address that encodes the PCI Bus, Device, Function and
819 @param AndData The value to AND with the PCI configuration register.
820 @param OrData The value to OR with the result of the AND operation.
822 @return The value written back to the PCI configuration register.
834 Reads a bit field of a PCI configuration register.
836 Reads the bit field in a 32-bit PCI configuration register. The bit field is
837 specified by the StartBit and the EndBit. The value of the bit field is
840 If Address > 0x0FFFFFFF, then ASSERT().
841 If Address is not aligned on a 32-bit boundary, then ASSERT().
842 If the register specified by Address >= 0x100, then ASSERT().
843 If StartBit is greater than 31, then ASSERT().
844 If EndBit is greater than 31, then ASSERT().
845 If EndBit is less than StartBit, then ASSERT().
847 @param Address PCI configuration register to read.
848 @param StartBit The ordinal of the least significant bit in the bit field.
850 @param EndBit The ordinal of the most significant bit in the bit field.
853 @return The value of the bit field read from the PCI configuration register.
858 PciCf8BitFieldRead32 (
865 Writes a bit field to a PCI configuration register.
867 Writes Value to the bit field of the PCI configuration register. The bit
868 field is specified by the StartBit and the EndBit. All other bits in the
869 destination PCI configuration register are preserved. The new value of the
870 32-bit register is returned.
872 If Address > 0x0FFFFFFF, then ASSERT().
873 If Address is not aligned on a 32-bit boundary, then ASSERT().
874 If the register specified by Address >= 0x100, then ASSERT().
875 If StartBit is greater than 31, then ASSERT().
876 If EndBit is greater than 31, then ASSERT().
877 If EndBit is less than StartBit, then ASSERT().
879 @param Address PCI configuration register to write.
880 @param StartBit The ordinal of the least significant bit in the bit field.
882 @param EndBit The ordinal of the most significant bit in the bit field.
884 @param Value New value of the bit field.
886 @return The value written back to the PCI configuration register.
891 PciCf8BitFieldWrite32 (
899 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
900 writes the result back to the bit field in the 32-bit port.
902 Reads the 32-bit PCI configuration register specified by Address, performs a
903 bitwise OR between the read result and the value specified by
904 OrData, and writes the result to the 32-bit PCI configuration register
905 specified by Address. The value written to the PCI configuration register is
906 returned. This function must guarantee that all PCI read and write operations
907 are serialized. Extra left bits in OrData are stripped.
909 If Address > 0x0FFFFFFF, then ASSERT().
910 If Address is not aligned on a 32-bit boundary, then ASSERT().
911 If the register specified by Address >= 0x100, then ASSERT().
912 If StartBit is greater than 31, then ASSERT().
913 If EndBit is greater than 31, then ASSERT().
914 If EndBit is less than StartBit, then ASSERT().
916 @param Address PCI configuration register to write.
917 @param StartBit The ordinal of the least significant bit in the bit field.
919 @param EndBit The ordinal of the most significant bit in the bit field.
921 @param OrData The value to OR with the PCI configuration register.
923 @return The value written back to the PCI configuration register.
936 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
937 AND, and writes the result back to the bit field in the 32-bit register.
939 Reads the 32-bit PCI configuration register specified by Address, performs a
940 bitwise AND between the read result and the value specified by AndData, and
941 writes the result to the 32-bit PCI configuration register specified by
942 Address. The value written to the PCI configuration register is returned.
943 This function must guarantee that all PCI read and write operations are
944 serialized. Extra left bits in AndData are stripped.
946 If Address > 0x0FFFFFFF, then ASSERT().
947 If Address is not aligned on a 32-bit boundary, then ASSERT().
948 If the register specified by Address >= 0x100, then ASSERT().
949 If StartBit is greater than 31, then ASSERT().
950 If EndBit is greater than 31, then ASSERT().
951 If EndBit is less than StartBit, then ASSERT().
953 @param Address PCI configuration register to write.
954 @param StartBit The ordinal of the least significant bit in the bit field.
956 @param EndBit The ordinal of the most significant bit in the bit field.
958 @param AndData The value to AND with the PCI configuration register.
960 @return The value written back to the PCI configuration register.
965 PciCf8BitFieldAnd32 (
973 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
974 bitwise OR, and writes the result back to the bit field in the
977 Reads the 32-bit PCI configuration register specified by Address, performs a
978 bitwise AND followed by a bitwise OR between the read result and
979 the value specified by AndData, and writes the result to the 32-bit PCI
980 configuration register specified by Address. The value written to the PCI
981 configuration register is returned. This function must guarantee that all PCI
982 read and write operations are serialized. Extra left bits in both AndData and
985 If Address > 0x0FFFFFFF, then ASSERT().
986 If Address is not aligned on a 32-bit boundary, then ASSERT().
987 If the register specified by Address >= 0x100, then ASSERT().
988 If StartBit is greater than 31, then ASSERT().
989 If EndBit is greater than 31, then ASSERT().
990 If EndBit is less than StartBit, then ASSERT().
992 @param Address PCI configuration register to write.
993 @param StartBit The ordinal of the least significant bit in the bit field.
995 @param EndBit The ordinal of the most significant bit in the bit field.
997 @param AndData The value to AND with the PCI configuration register.
998 @param OrData The value to OR with the result of the AND operation.
1000 @return The value written back to the PCI configuration register.
1005 PciCf8BitFieldAndThenOr32 (
1014 Reads a range of PCI configuration registers into a caller supplied buffer.
1016 Reads the range of PCI configuration registers specified by StartAddress and
1017 Size into the buffer specified by Buffer. This function only allows the PCI
1018 configuration registers from a single PCI function to be read. Size is
1019 returned. When possible 32-bit PCI configuration read cycles are used to read
1020 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1021 and 16-bit PCI configuration read cycles may be used at the beginning and the
1024 If StartAddress > 0x0FFFFFFF, then ASSERT().
1025 If the register specified by StartAddress >= 0x100, then ASSERT().
1026 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1027 If Size > 0 and Buffer is NULL, then ASSERT().
1029 @param StartAddress Starting address that encodes the PCI Bus, Device,
1030 Function and Register.
1031 @param Size Size in bytes of the transfer.
1032 @param Buffer Pointer to a buffer receiving the data read.
1034 @return Size read from StartAddress.
1040 IN UINTN StartAddress
,
1046 Copies the data in a caller supplied buffer to a specified range of PCI
1047 configuration space.
1049 Writes the range of PCI configuration registers specified by StartAddress and
1050 Size from the buffer specified by Buffer. This function only allows the PCI
1051 configuration registers from a single PCI function to be written. Size is
1052 returned. When possible 32-bit PCI configuration write cycles are used to
1053 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1054 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1055 and the end of the range.
1057 If StartAddress > 0x0FFFFFFF, then ASSERT().
1058 If the register specified by StartAddress >= 0x100, then ASSERT().
1059 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1060 If Size > 0 and Buffer is NULL, then ASSERT().
1062 @param StartAddress Starting address that encodes the PCI Bus, Device,
1063 Function and Register.
1064 @param Size Size in bytes of the transfer.
1065 @param Buffer Pointer to a buffer containing the data to write.
1067 @return Size written to StartAddress.
1073 IN UINTN StartAddress
,