]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Library/PciCf8Lib.h
2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
4 Copyright (c) 2006 - 2008, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef __PCI_CF8_LIB_H__
16 #define __PCI_CF8_LIB_H__
20 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
21 address that can be passed to the PCI Library functions.
23 Computes an address that is compatible with the PCI Library functions. The
24 unused upper bits of Bus, Device, Function and Register are stripped prior to
25 the generation of the address.
27 @param Bus PCI Bus number. Range 0..255.
28 @param Device PCI Device number. Range 0..31.
29 @param Function PCI Function number. Range 0..7.
30 @param Register PCI Register number. Range 0..255.
32 @return The encode PCI address.
35 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
36 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
39 Reads an 8-bit PCI configuration register.
41 Reads and returns the 8-bit PCI configuration register specified by Address.
42 This function must guarantee that all PCI read and write operations are
45 If Address > 0x0FFFFFFF, then ASSERT().
46 If the register specified by Address >= 0x100, then ASSERT().
48 @param Address Address that encodes the PCI Bus, Device, Function and
51 @return The read value from the PCI configuration register.
61 Writes an 8-bit PCI configuration register.
63 Writes the 8-bit PCI configuration register specified by Address with the
64 value specified by Value. Value is returned. This function must guarantee
65 that all PCI read and write operations are serialized.
67 If Address > 0x0FFFFFFF, then ASSERT().
68 If the register specified by Address >= 0x100, then ASSERT().
70 @param Address Address that encodes the PCI Bus, Device, Function and
72 @param Value The value to write.
74 @return The value written to the PCI configuration register.
85 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
88 Reads the 8-bit PCI configuration register specified by Address, performs a
89 bitwise inclusive OR between the read result and the value specified by
90 OrData, and writes the result to the 8-bit PCI configuration register
91 specified by Address. The value written to the PCI configuration register is
92 returned. This function must guarantee that all PCI read and write operations
95 If Address > 0x0FFFFFFF, then ASSERT().
96 If the register specified by Address >= 0x100, then ASSERT().
98 @param Address Address that encodes the PCI Bus, Device, Function and
100 @param OrData The value to OR with the PCI configuration register.
102 @return The value written back to the PCI configuration register.
113 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
116 Reads the 8-bit PCI configuration register specified by Address, performs a
117 bitwise AND between the read result and the value specified by AndData, and
118 writes the result to the 8-bit PCI configuration register specified by
119 Address. The value written to the PCI configuration register is returned.
120 This function must guarantee that all PCI read and write operations are
123 If Address > 0x0FFFFFFF, then ASSERT().
124 If the register specified by Address >= 0x100, then ASSERT().
126 @param Address Address that encodes the PCI Bus, Device, Function and
128 @param AndData The value to AND with the PCI configuration register.
130 @return The value written back to the PCI configuration register.
141 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
142 value, followed a bitwise inclusive OR with another 8-bit value.
144 Reads the 8-bit PCI configuration register specified by Address, performs a
145 bitwise AND between the read result and the value specified by AndData,
146 performs a bitwise inclusive OR between the result of the AND operation and
147 the value specified by OrData, and writes the result to the 8-bit PCI
148 configuration register specified by Address. The value written to the PCI
149 configuration register is returned. This function must guarantee that all PCI
150 read and write operations are serialized.
152 If Address > 0x0FFFFFFF, then ASSERT().
153 If the register specified by Address >= 0x100, then ASSERT().
155 @param Address Address that encodes the PCI Bus, Device, Function and
157 @param AndData The value to AND with the PCI configuration register.
158 @param OrData The value to OR with the result of the AND operation.
160 @return The value written back to the PCI configuration register.
172 Reads a bit field of a PCI configuration register.
174 Reads the bit field in an 8-bit PCI configuration register. The bit field is
175 specified by the StartBit and the EndBit. The value of the bit field is
178 If Address > 0x0FFFFFFF, then ASSERT().
179 If the register specified by Address >= 0x100, then ASSERT().
180 If StartBit is greater than 7, then ASSERT().
181 If EndBit is greater than 7, then ASSERT().
182 If EndBit is less than StartBit, then ASSERT().
184 @param Address PCI configuration register to read.
185 @param StartBit The ordinal of the least significant bit in the bit field.
187 @param EndBit The ordinal of the most significant bit in the bit field.
190 @return The value of the bit field read from the PCI configuration register.
195 PciCf8BitFieldRead8 (
202 Writes a bit field to a PCI configuration register.
204 Writes Value to the bit field of the PCI configuration register. The bit
205 field is specified by the StartBit and the EndBit. All other bits in the
206 destination PCI configuration register are preserved. The new value of the
207 8-bit register is returned.
209 If Address > 0x0FFFFFFF, then ASSERT().
210 If the register specified by Address >= 0x100, then ASSERT().
211 If StartBit is greater than 7, then ASSERT().
212 If EndBit is greater than 7, then ASSERT().
213 If EndBit is less than StartBit, then ASSERT().
215 @param Address PCI configuration register to write.
216 @param StartBit The ordinal of the least significant bit in the bit field.
218 @param EndBit The ordinal of the most significant bit in the bit field.
220 @param Value New value of the bit field.
222 @return The value written back to the PCI configuration register.
227 PciCf8BitFieldWrite8 (
235 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
236 writes the result back to the bit field in the 8-bit port.
238 Reads the 8-bit PCI configuration register specified by Address, performs a
239 bitwise inclusive OR between the read result and the value specified by
240 OrData, and writes the result to the 8-bit PCI configuration register
241 specified by Address. The value written to the PCI configuration register is
242 returned. This function must guarantee that all PCI read and write operations
243 are serialized. Extra left bits in OrData are stripped.
245 If Address > 0x0FFFFFFF, then ASSERT().
246 If the register specified by Address >= 0x100, then ASSERT().
247 If StartBit is greater than 7, then ASSERT().
248 If EndBit is greater than 7, then ASSERT().
249 If EndBit is less than StartBit, then ASSERT().
251 @param Address PCI configuration register to write.
252 @param StartBit The ordinal of the least significant bit in the bit field.
254 @param EndBit The ordinal of the most significant bit in the bit field.
256 @param OrData The value to OR with the PCI configuration register.
258 @return The value written back to the PCI configuration register.
271 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
272 AND, and writes the result back to the bit field in the 8-bit register.
274 Reads the 8-bit PCI configuration register specified by Address, performs a
275 bitwise AND between the read result and the value specified by AndData, and
276 writes the result to the 8-bit PCI configuration register specified by
277 Address. The value written to the PCI configuration register is returned.
278 This function must guarantee that all PCI read and write operations are
279 serialized. Extra left bits in AndData are stripped.
281 If Address > 0x0FFFFFFF, then ASSERT().
282 If the register specified by Address >= 0x100, then ASSERT().
283 If StartBit is greater than 7, then ASSERT().
284 If EndBit is greater than 7, then ASSERT().
285 If EndBit is less than StartBit, then ASSERT().
287 @param Address PCI configuration register to write.
288 @param StartBit The ordinal of the least significant bit in the bit field.
290 @param EndBit The ordinal of the most significant bit in the bit field.
292 @param AndData The value to AND with the PCI configuration register.
294 @return The value written back to the PCI configuration register.
307 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
308 bitwise inclusive OR, and writes the result back to the bit field in the
311 Reads the 8-bit PCI configuration register specified by Address, performs a
312 bitwise AND followed by a bitwise inclusive OR between the read result and
313 the value specified by AndData, and writes the result to the 8-bit PCI
314 configuration register specified by Address. The value written to the PCI
315 configuration register is returned. This function must guarantee that all PCI
316 read and write operations are serialized. Extra left bits in both AndData and
319 If Address > 0x0FFFFFFF, then ASSERT().
320 If the register specified by Address >= 0x100, then ASSERT().
321 If StartBit is greater than 7, then ASSERT().
322 If EndBit is greater than 7, then ASSERT().
323 If EndBit is less than StartBit, then ASSERT().
325 @param Address PCI configuration register to write.
326 @param StartBit The ordinal of the least significant bit in the bit field.
328 @param EndBit The ordinal of the most significant bit in the bit field.
330 @param AndData The value to AND with the PCI configuration register.
331 @param OrData The value to OR with the result of the AND operation.
333 @return The value written back to the PCI configuration register.
338 PciCf8BitFieldAndThenOr8 (
347 Reads a 16-bit PCI configuration register.
349 Reads and returns the 16-bit PCI configuration register specified by Address.
350 This function must guarantee that all PCI read and write operations are
353 If Address > 0x0FFFFFFF, then ASSERT().
354 If Address is not aligned on a 16-bit boundary, then ASSERT().
355 If the register specified by Address >= 0x100, then ASSERT().
357 @param Address Address that encodes the PCI Bus, Device, Function and
360 @return The read value from the PCI configuration register.
370 Writes a 16-bit PCI configuration register.
372 Writes the 16-bit PCI configuration register specified by Address with the
373 value specified by Value. Value is returned. This function must guarantee
374 that all PCI read and write operations are serialized.
376 If Address > 0x0FFFFFFF, then ASSERT().
377 If Address is not aligned on a 16-bit boundary, then ASSERT().
378 If the register specified by Address >= 0x100, then ASSERT().
380 @param Address Address that encodes the PCI Bus, Device, Function and
382 @param Value The value to write.
384 @return The value written to the PCI configuration register.
395 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
398 Reads the 16-bit PCI configuration register specified by Address, performs a
399 bitwise inclusive OR between the read result and the value specified by
400 OrData, and writes the result to the 16-bit PCI configuration register
401 specified by Address. The value written to the PCI configuration register is
402 returned. This function must guarantee that all PCI read and write operations
405 If Address > 0x0FFFFFFF, then ASSERT().
406 If Address is not aligned on a 16-bit boundary, then ASSERT().
407 If the register specified by Address >= 0x100, then ASSERT().
409 @param Address Address that encodes the PCI Bus, Device, Function and
411 @param OrData The value to OR with the PCI configuration register.
413 @return The value written back to the PCI configuration register.
424 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
427 Reads the 16-bit PCI configuration register specified by Address, performs a
428 bitwise AND between the read result and the value specified by AndData, and
429 writes the result to the 16-bit PCI configuration register specified by
430 Address. The value written to the PCI configuration register is returned.
431 This function must guarantee that all PCI read and write operations are
434 If Address > 0x0FFFFFFF, then ASSERT().
435 If Address is not aligned on a 16-bit boundary, then ASSERT().
436 If the register specified by Address >= 0x100, then ASSERT().
438 @param Address Address that encodes the PCI Bus, Device, Function and
440 @param AndData The value to AND with the PCI configuration register.
442 @return The value written back to the PCI configuration register.
453 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
454 value, followed a bitwise inclusive OR with another 16-bit value.
456 Reads the 16-bit PCI configuration register specified by Address, performs a
457 bitwise AND between the read result and the value specified by AndData,
458 performs a bitwise inclusive OR between the result of the AND operation and
459 the value specified by OrData, and writes the result to the 16-bit PCI
460 configuration register specified by Address. The value written to the PCI
461 configuration register is returned. This function must guarantee that all PCI
462 read and write operations are serialized.
464 If Address > 0x0FFFFFFF, then ASSERT().
465 If Address is not aligned on a 16-bit boundary, then ASSERT().
466 If the register specified by Address >= 0x100, then ASSERT().
468 @param Address Address that encodes the PCI Bus, Device, Function and
470 @param AndData The value to AND with the PCI configuration register.
471 @param OrData The value to OR with the result of the AND operation.
473 @return The value written back to the PCI configuration register.
485 Reads a bit field of a PCI configuration register.
487 Reads the bit field in a 16-bit PCI configuration register. The bit field is
488 specified by the StartBit and the EndBit. The value of the bit field is
491 If Address > 0x0FFFFFFF, then ASSERT().
492 If Address is not aligned on a 16-bit boundary, then ASSERT().
493 If the register specified by Address >= 0x100, then ASSERT().
494 If StartBit is greater than 15, then ASSERT().
495 If EndBit is greater than 15, then ASSERT().
496 If EndBit is less than StartBit, then ASSERT().
498 @param Address PCI configuration register to read.
499 @param StartBit The ordinal of the least significant bit in the bit field.
501 @param EndBit The ordinal of the most significant bit in the bit field.
504 @return The value of the bit field read from the PCI configuration register.
509 PciCf8BitFieldRead16 (
516 Writes a bit field to a PCI configuration register.
518 Writes Value to the bit field of the PCI configuration register. The bit
519 field is specified by the StartBit and the EndBit. All other bits in the
520 destination PCI configuration register are preserved. The new value of the
521 16-bit register is returned.
523 If Address > 0x0FFFFFFF, then ASSERT().
524 If Address is not aligned on a 16-bit boundary, then ASSERT().
525 If the register specified by Address >= 0x100, then ASSERT().
526 If StartBit is greater than 15, then ASSERT().
527 If EndBit is greater than 15, then ASSERT().
528 If EndBit is less than StartBit, then ASSERT().
530 @param Address PCI configuration register to write.
531 @param StartBit The ordinal of the least significant bit in the bit field.
533 @param EndBit The ordinal of the most significant bit in the bit field.
535 @param Value New value of the bit field.
537 @return The value written back to the PCI configuration register.
542 PciCf8BitFieldWrite16 (
550 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
551 writes the result back to the bit field in the 16-bit port.
553 Reads the 16-bit PCI configuration register specified by Address, performs a
554 bitwise inclusive OR between the read result and the value specified by
555 OrData, and writes the result to the 16-bit PCI configuration register
556 specified by Address. The value written to the PCI configuration register is
557 returned. This function must guarantee that all PCI read and write operations
558 are serialized. Extra left bits in OrData are stripped.
560 If Address > 0x0FFFFFFF, then ASSERT().
561 If Address is not aligned on a 16-bit boundary, then ASSERT().
562 If the register specified by Address >= 0x100, then ASSERT().
563 If StartBit is greater than 15, then ASSERT().
564 If EndBit is greater than 15, then ASSERT().
565 If EndBit is less than StartBit, then ASSERT().
567 @param Address PCI configuration register to write.
568 @param StartBit The ordinal of the least significant bit in the bit field.
570 @param EndBit The ordinal of the most significant bit in the bit field.
572 @param OrData The value to OR with the PCI configuration register.
574 @return The value written back to the PCI configuration register.
587 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
588 AND, and writes the result back to the bit field in the 16-bit register.
590 Reads the 16-bit PCI configuration register specified by Address, performs a
591 bitwise AND between the read result and the value specified by AndData, and
592 writes the result to the 16-bit PCI configuration register specified by
593 Address. The value written to the PCI configuration register is returned.
594 This function must guarantee that all PCI read and write operations are
595 serialized. Extra left bits in AndData are stripped.
597 If Address > 0x0FFFFFFF, then ASSERT().
598 If Address is not aligned on a 16-bit boundary, then ASSERT().
599 If the register specified by Address >= 0x100, then ASSERT().
600 If StartBit is greater than 15, then ASSERT().
601 If EndBit is greater than 15, then ASSERT().
602 If EndBit is less than StartBit, then ASSERT().
604 @param Address PCI configuration register to write.
605 @param StartBit The ordinal of the least significant bit in the bit field.
607 @param EndBit The ordinal of the most significant bit in the bit field.
609 @param AndData The value to AND with the PCI configuration register.
611 @return The value written back to the PCI configuration register.
616 PciCf8BitFieldAnd16 (
624 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
625 bitwise inclusive OR, and writes the result back to the bit field in the
628 Reads the 16-bit PCI configuration register specified by Address, performs a
629 bitwise AND followed by a bitwise inclusive OR between the read result and
630 the value specified by AndData, and writes the result to the 16-bit PCI
631 configuration register specified by Address. The value written to the PCI
632 configuration register is returned. This function must guarantee that all PCI
633 read and write operations are serialized. Extra left bits in both AndData and
636 If Address > 0x0FFFFFFF, then ASSERT().
637 If Address is not aligned on a 16-bit boundary, then ASSERT().
638 If the register specified by Address >= 0x100, then ASSERT().
639 If StartBit is greater than 15, then ASSERT().
640 If EndBit is greater than 15, then ASSERT().
641 If EndBit is less than StartBit, then ASSERT().
643 @param Address PCI configuration register to write.
644 @param StartBit The ordinal of the least significant bit in the bit field.
646 @param EndBit The ordinal of the most significant bit in the bit field.
648 @param AndData The value to AND with the PCI configuration register.
649 @param OrData The value to OR with the result of the AND operation.
651 @return The value written back to the PCI configuration register.
656 PciCf8BitFieldAndThenOr16 (
665 Reads a 32-bit PCI configuration register.
667 Reads and returns the 32-bit PCI configuration register specified by Address.
668 This function must guarantee that all PCI read and write operations are
671 If Address > 0x0FFFFFFF, then ASSERT().
672 If Address is not aligned on a 32-bit boundary, then ASSERT().
673 If the register specified by Address >= 0x100, then ASSERT().
675 @param Address Address that encodes the PCI Bus, Device, Function and
678 @return The read value from the PCI configuration register.
688 Writes a 32-bit PCI configuration register.
690 Writes the 32-bit PCI configuration register specified by Address with the
691 value specified by Value. Value is returned. This function must guarantee
692 that all PCI read and write operations are serialized.
694 If Address > 0x0FFFFFFF, then ASSERT().
695 If Address is not aligned on a 32-bit boundary, then ASSERT().
696 If the register specified by Address >= 0x100, then ASSERT().
698 @param Address Address that encodes the PCI Bus, Device, Function and
700 @param Value The value to write.
702 @return The value written to the PCI configuration register.
713 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
716 Reads the 32-bit PCI configuration register specified by Address, performs a
717 bitwise inclusive OR between the read result and the value specified by
718 OrData, and writes the result to the 32-bit PCI configuration register
719 specified by Address. The value written to the PCI configuration register is
720 returned. This function must guarantee that all PCI read and write operations
723 If Address > 0x0FFFFFFF, then ASSERT().
724 If Address is not aligned on a 32-bit boundary, then ASSERT().
725 If the register specified by Address >= 0x100, then ASSERT().
727 @param Address Address that encodes the PCI Bus, Device, Function and
729 @param OrData The value to OR with the PCI configuration register.
731 @return The value written back to the PCI configuration register.
742 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
745 Reads the 32-bit PCI configuration register specified by Address, performs a
746 bitwise AND between the read result and the value specified by AndData, and
747 writes the result to the 32-bit PCI configuration register specified by
748 Address. The value written to the PCI configuration register is returned.
749 This function must guarantee that all PCI read and write operations are
752 If Address > 0x0FFFFFFF, then ASSERT().
753 If Address is not aligned on a 32-bit boundary, then ASSERT().
754 If the register specified by Address >= 0x100, then ASSERT().
756 @param Address Address that encodes the PCI Bus, Device, Function and
758 @param AndData The value to AND with the PCI configuration register.
760 @return The value written back to the PCI configuration register.
771 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
772 value, followed a bitwise inclusive OR with another 32-bit value.
774 Reads the 32-bit PCI configuration register specified by Address, performs a
775 bitwise AND between the read result and the value specified by AndData,
776 performs a bitwise inclusive OR between the result of the AND operation and
777 the value specified by OrData, and writes the result to the 32-bit PCI
778 configuration register specified by Address. The value written to the PCI
779 configuration register is returned. This function must guarantee that all PCI
780 read and write operations are serialized.
782 If Address > 0x0FFFFFFF, then ASSERT().
783 If Address is not aligned on a 32-bit boundary, then ASSERT().
784 If the register specified by Address >= 0x100, then ASSERT().
786 @param Address Address that encodes the PCI Bus, Device, Function and
788 @param AndData The value to AND with the PCI configuration register.
789 @param OrData The value to OR with the result of the AND operation.
791 @return The value written back to the PCI configuration register.
803 Reads a bit field of a PCI configuration register.
805 Reads the bit field in a 32-bit PCI configuration register. The bit field is
806 specified by the StartBit and the EndBit. The value of the bit field is
809 If Address > 0x0FFFFFFF, then ASSERT().
810 If Address is not aligned on a 32-bit boundary, then ASSERT().
811 If the register specified by Address >= 0x100, then ASSERT().
812 If StartBit is greater than 31, then ASSERT().
813 If EndBit is greater than 31, then ASSERT().
814 If EndBit is less than StartBit, then ASSERT().
816 @param Address PCI configuration register to read.
817 @param StartBit The ordinal of the least significant bit in the bit field.
819 @param EndBit The ordinal of the most significant bit in the bit field.
822 @return The value of the bit field read from the PCI configuration register.
827 PciCf8BitFieldRead32 (
834 Writes a bit field to a PCI configuration register.
836 Writes Value to the bit field of the PCI configuration register. The bit
837 field is specified by the StartBit and the EndBit. All other bits in the
838 destination PCI configuration register are preserved. The new value of the
839 32-bit register is returned.
841 If Address > 0x0FFFFFFF, then ASSERT().
842 If Address is not aligned on a 32-bit boundary, then ASSERT().
843 If the register specified by Address >= 0x100, then ASSERT().
844 If StartBit is greater than 31, then ASSERT().
845 If EndBit is greater than 31, then ASSERT().
846 If EndBit is less than StartBit, then ASSERT().
848 @param Address PCI configuration register to write.
849 @param StartBit The ordinal of the least significant bit in the bit field.
851 @param EndBit The ordinal of the most significant bit in the bit field.
853 @param Value New value of the bit field.
855 @return The value written back to the PCI configuration register.
860 PciCf8BitFieldWrite32 (
868 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
869 writes the result back to the bit field in the 32-bit port.
871 Reads the 32-bit PCI configuration register specified by Address, performs a
872 bitwise inclusive OR between the read result and the value specified by
873 OrData, and writes the result to the 32-bit PCI configuration register
874 specified by Address. The value written to the PCI configuration register is
875 returned. This function must guarantee that all PCI read and write operations
876 are serialized. Extra left bits in OrData are stripped.
878 If Address > 0x0FFFFFFF, then ASSERT().
879 If Address is not aligned on a 32-bit boundary, then ASSERT().
880 If the register specified by Address >= 0x100, then ASSERT().
881 If StartBit is greater than 31, then ASSERT().
882 If EndBit is greater than 31, then ASSERT().
883 If EndBit is less than StartBit, then ASSERT().
885 @param Address PCI configuration register to write.
886 @param StartBit The ordinal of the least significant bit in the bit field.
888 @param EndBit The ordinal of the most significant bit in the bit field.
890 @param OrData The value to OR with the PCI configuration register.
892 @return The value written back to the PCI configuration register.
905 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
906 AND, and writes the result back to the bit field in the 32-bit register.
908 Reads the 32-bit PCI configuration register specified by Address, performs a
909 bitwise AND between the read result and the value specified by AndData, and
910 writes the result to the 32-bit PCI configuration register specified by
911 Address. The value written to the PCI configuration register is returned.
912 This function must guarantee that all PCI read and write operations are
913 serialized. Extra left bits in AndData are stripped.
915 If Address > 0x0FFFFFFF, then ASSERT().
916 If Address is not aligned on a 32-bit boundary, then ASSERT().
917 If the register specified by Address >= 0x100, then ASSERT().
918 If StartBit is greater than 31, then ASSERT().
919 If EndBit is greater than 31, then ASSERT().
920 If EndBit is less than StartBit, then ASSERT().
922 @param Address PCI configuration register to write.
923 @param StartBit The ordinal of the least significant bit in the bit field.
925 @param EndBit The ordinal of the most significant bit in the bit field.
927 @param AndData The value to AND with the PCI configuration register.
929 @return The value written back to the PCI configuration register.
934 PciCf8BitFieldAnd32 (
942 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
943 bitwise inclusive OR, and writes the result back to the bit field in the
946 Reads the 32-bit PCI configuration register specified by Address, performs a
947 bitwise AND followed by a bitwise inclusive OR between the read result and
948 the value specified by AndData, and writes the result to the 32-bit PCI
949 configuration register specified by Address. The value written to the PCI
950 configuration register is returned. This function must guarantee that all PCI
951 read and write operations are serialized. Extra left bits in both AndData and
954 If Address > 0x0FFFFFFF, then ASSERT().
955 If Address is not aligned on a 32-bit boundary, then ASSERT().
956 If the register specified by Address >= 0x100, then ASSERT().
957 If StartBit is greater than 31, then ASSERT().
958 If EndBit is greater than 31, then ASSERT().
959 If EndBit is less than StartBit, then ASSERT().
961 @param Address PCI configuration register to write.
962 @param StartBit The ordinal of the least significant bit in the bit field.
964 @param EndBit The ordinal of the most significant bit in the bit field.
966 @param AndData The value to AND with the PCI configuration register.
967 @param OrData The value to OR with the result of the AND operation.
969 @return The value written back to the PCI configuration register.
974 PciCf8BitFieldAndThenOr32 (
983 Reads a range of PCI configuration registers into a caller supplied buffer.
985 Reads the range of PCI configuration registers specified by StartAddress and
986 Size into the buffer specified by Buffer. This function only allows the PCI
987 configuration registers from a single PCI function to be read. Size is
988 returned. When possible 32-bit PCI configuration read cycles are used to read
989 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
990 and 16-bit PCI configuration read cycles may be used at the beginning and the
993 If StartAddress > 0x0FFFFFFF, then ASSERT().
994 If the register specified by StartAddress >= 0x100, then ASSERT().
995 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
996 If Size > 0 and Buffer is NULL, then ASSERT().
998 @param StartAddress Starting address that encodes the PCI Bus, Device,
999 Function and Register.
1000 @param Size Size in bytes of the transfer.
1001 @param Buffer Pointer to a buffer receiving the data read.
1003 @return Size read from StartAddress.
1009 IN UINTN StartAddress
,
1015 Copies the data in a caller supplied buffer to a specified range of PCI
1016 configuration space.
1018 Writes the range of PCI configuration registers specified by StartAddress and
1019 Size from the buffer specified by Buffer. This function only allows the PCI
1020 configuration registers from a single PCI function to be written. Size is
1021 returned. When possible 32-bit PCI configuration write cycles are used to
1022 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1023 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1024 and the end of the range.
1026 If StartAddress > 0x0FFFFFFF, then ASSERT().
1027 If the register specified by StartAddress >= 0x100, then ASSERT().
1028 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1029 If Size > 0 and Buffer is NULL, then ASSERT().
1031 @param StartAddress Starting address that encodes the PCI Bus, Device,
1032 Function and Register.
1033 @param Size Size in bytes of the transfer.
1034 @param Buffer Pointer to a buffer containing the data to write.
1036 @return Size written to StartAddress.
1042 IN UINTN StartAddress
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