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2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be though the 256 MB PCI Express MMIO window whose base address
6 is defined by PcdPciExpressBaseAddress.
8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __PCI_EXPRESS_LIB_H__
20 #define __PCI_EXPRESS_LIB_H__
23 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
24 address that can be passed to the PCI Library functions.
26 Computes an address that is compatible with the PCI Library functions. The
27 unused upper bits of Bus, Device, Function and Register are stripped prior to
28 the generation of the address.
30 @param Bus PCI Bus number. Range 0..255.
31 @param Device PCI Device number. Range 0..31.
32 @param Function PCI Function number. Range 0..7.
33 @param Register PCI Register number. Range 0..4095.
35 @return The encode PCI address.
38 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
39 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
42 Register a PCI device so PCI configuration registers may be accessed after
43 SetVirtualAddressMap().
45 If Address > 0x0FFFFFFF, then ASSERT().
47 @param Address Address that encodes the PCI Bus, Device, Function and
50 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
51 @retval RETURN_UNSUPPORTED An attempt was made to call this function
52 after ExitBootServices().
53 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
54 at runtime could not be mapped.
55 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
56 complete the registration.
61 PciExpressRegisterForRuntimeAccess (
66 Reads an 8-bit PCI configuration register.
68 Reads and returns the 8-bit PCI configuration register specified by Address.
69 This function must guarantee that all PCI read and write operations are
72 If Address > 0x0FFFFFFF, then ASSERT().
74 @param Address Address that encodes the PCI Bus, Device, Function and
77 @return The read value from the PCI configuration register.
87 Writes an 8-bit PCI configuration register.
89 Writes the 8-bit PCI configuration register specified by Address with the
90 value specified by Value. Value is returned. This function must guarantee
91 that all PCI read and write operations are serialized.
93 If Address > 0x0FFFFFFF, then ASSERT().
95 @param Address Address that encodes the PCI Bus, Device, Function and
97 @param Value The value to write.
99 @return The value written to the PCI configuration register.
110 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
113 Reads the 8-bit PCI configuration register specified by Address, performs a
114 bitwise inclusive OR between the read result and the value specified by
115 OrData, and writes the result to the 8-bit PCI configuration register
116 specified by Address. The value written to the PCI configuration register is
117 returned. This function must guarantee that all PCI read and write operations
120 If Address > 0x0FFFFFFF, then ASSERT().
122 @param Address Address that encodes the PCI Bus, Device, Function and
124 @param OrData The value to OR with the PCI configuration register.
126 @return The value written back to the PCI configuration register.
137 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
140 Reads the 8-bit PCI configuration register specified by Address, performs a
141 bitwise AND between the read result and the value specified by AndData, and
142 writes the result to the 8-bit PCI configuration register specified by
143 Address. The value written to the PCI configuration register is returned.
144 This function must guarantee that all PCI read and write operations are
147 If Address > 0x0FFFFFFF, then ASSERT().
149 @param Address Address that encodes the PCI Bus, Device, Function and
151 @param AndData The value to AND with the PCI configuration register.
153 @return The value written back to the PCI configuration register.
164 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
165 value, followed a bitwise inclusive OR with another 8-bit value.
167 Reads the 8-bit PCI configuration register specified by Address, performs a
168 bitwise AND between the read result and the value specified by AndData,
169 performs a bitwise inclusive OR between the result of the AND operation and
170 the value specified by OrData, and writes the result to the 8-bit PCI
171 configuration register specified by Address. The value written to the PCI
172 configuration register is returned. This function must guarantee that all PCI
173 read and write operations are serialized.
175 If Address > 0x0FFFFFFF, then ASSERT().
177 @param Address Address that encodes the PCI Bus, Device, Function and
179 @param AndData The value to AND with the PCI configuration register.
180 @param OrData The value to OR with the result of the AND operation.
182 @return The value written back to the PCI configuration register.
187 PciExpressAndThenOr8 (
194 Reads a bit field of a PCI configuration register.
196 Reads the bit field in an 8-bit PCI configuration register. The bit field is
197 specified by the StartBit and the EndBit. The value of the bit field is
200 If Address > 0x0FFFFFFF, then ASSERT().
201 If StartBit is greater than 7, then ASSERT().
202 If EndBit is greater than 7, then ASSERT().
203 If EndBit is less than StartBit, then ASSERT().
205 @param Address PCI configuration register to read.
206 @param StartBit The ordinal of the least significant bit in the bit field.
208 @param EndBit The ordinal of the most significant bit in the bit field.
211 @return The value of the bit field read from the PCI configuration register.
216 PciExpressBitFieldRead8 (
223 Writes a bit field to a PCI configuration register.
225 Writes Value to the bit field of the PCI configuration register. The bit
226 field is specified by the StartBit and the EndBit. All other bits in the
227 destination PCI configuration register are preserved. The new value of the
228 8-bit register is returned.
230 If Address > 0x0FFFFFFF, then ASSERT().
231 If StartBit is greater than 7, then ASSERT().
232 If EndBit is greater than 7, then ASSERT().
233 If EndBit is less than StartBit, then ASSERT().
235 @param Address PCI configuration register to write.
236 @param StartBit The ordinal of the least significant bit in the bit field.
238 @param EndBit The ordinal of the most significant bit in the bit field.
240 @param Value New value of the bit field.
242 @return The value written back to the PCI configuration register.
247 PciExpressBitFieldWrite8 (
255 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
256 writes the result back to the bit field in the 8-bit port.
258 Reads the 8-bit PCI configuration register specified by Address, performs a
259 bitwise inclusive OR between the read result and the value specified by
260 OrData, and writes the result to the 8-bit PCI configuration register
261 specified by Address. The value written to the PCI configuration register is
262 returned. This function must guarantee that all PCI read and write operations
263 are serialized. Extra left bits in OrData are stripped.
265 If Address > 0x0FFFFFFF, then ASSERT().
266 If StartBit is greater than 7, then ASSERT().
267 If EndBit is greater than 7, then ASSERT().
268 If EndBit is less than StartBit, then ASSERT().
270 @param Address PCI configuration register to write.
271 @param StartBit The ordinal of the least significant bit in the bit field.
273 @param EndBit The ordinal of the most significant bit in the bit field.
275 @param OrData The value to OR with the PCI configuration register.
277 @return The value written back to the PCI configuration register.
282 PciExpressBitFieldOr8 (
290 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
291 AND, and writes the result back to the bit field in the 8-bit register.
293 Reads the 8-bit PCI configuration register specified by Address, performs a
294 bitwise AND between the read result and the value specified by AndData, and
295 writes the result to the 8-bit PCI configuration register specified by
296 Address. The value written to the PCI configuration register is returned.
297 This function must guarantee that all PCI read and write operations are
298 serialized. Extra left bits in AndData are stripped.
300 If Address > 0x0FFFFFFF, then ASSERT().
301 If StartBit is greater than 7, then ASSERT().
302 If EndBit is greater than 7, then ASSERT().
303 If EndBit is less than StartBit, then ASSERT().
305 @param Address PCI configuration register to write.
306 @param StartBit The ordinal of the least significant bit in the bit field.
308 @param EndBit The ordinal of the most significant bit in the bit field.
310 @param AndData The value to AND with the PCI configuration register.
312 @return The value written back to the PCI configuration register.
317 PciExpressBitFieldAnd8 (
325 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
326 bitwise inclusive OR, and writes the result back to the bit field in the
329 Reads the 8-bit PCI configuration register specified by Address, performs a
330 bitwise AND followed by a bitwise inclusive OR between the read result and
331 the value specified by AndData, and writes the result to the 8-bit PCI
332 configuration register specified by Address. The value written to the PCI
333 configuration register is returned. This function must guarantee that all PCI
334 read and write operations are serialized. Extra left bits in both AndData and
337 If Address > 0x0FFFFFFF, then ASSERT().
338 If StartBit is greater than 7, then ASSERT().
339 If EndBit is greater than 7, then ASSERT().
340 If EndBit is less than StartBit, then ASSERT().
342 @param Address PCI configuration register to write.
343 @param StartBit The ordinal of the least significant bit in the bit field.
345 @param EndBit The ordinal of the most significant bit in the bit field.
347 @param AndData The value to AND with the PCI configuration register.
348 @param OrData The value to OR with the result of the AND operation.
350 @return The value written back to the PCI configuration register.
355 PciExpressBitFieldAndThenOr8 (
364 Reads a 16-bit PCI configuration register.
366 Reads and returns the 16-bit PCI configuration register specified by Address.
367 This function must guarantee that all PCI read and write operations are
370 If Address > 0x0FFFFFFF, then ASSERT().
371 If Address is not aligned on a 16-bit boundary, then ASSERT().
373 @param Address Address that encodes the PCI Bus, Device, Function and
376 @return The read value from the PCI configuration register.
386 Writes a 16-bit PCI configuration register.
388 Writes the 16-bit PCI configuration register specified by Address with the
389 value specified by Value. Value is returned. This function must guarantee
390 that all PCI read and write operations are serialized.
392 If Address > 0x0FFFFFFF, then ASSERT().
393 If Address is not aligned on a 16-bit boundary, then ASSERT().
395 @param Address Address that encodes the PCI Bus, Device, Function and
397 @param Value The value to write.
399 @return The value written to the PCI configuration register.
410 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
413 Reads the 16-bit PCI configuration register specified by Address, performs a
414 bitwise inclusive OR between the read result and the value specified by
415 OrData, and writes the result to the 16-bit PCI configuration register
416 specified by Address. The value written to the PCI configuration register is
417 returned. This function must guarantee that all PCI read and write operations
420 If Address > 0x0FFFFFFF, then ASSERT().
421 If Address is not aligned on a 16-bit boundary, then ASSERT().
423 @param Address Address that encodes the PCI Bus, Device, Function and
425 @param OrData The value to OR with the PCI configuration register.
427 @return The value written back to the PCI configuration register.
438 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
441 Reads the 16-bit PCI configuration register specified by Address, performs a
442 bitwise AND between the read result and the value specified by AndData, and
443 writes the result to the 16-bit PCI configuration register specified by
444 Address. The value written to the PCI configuration register is returned.
445 This function must guarantee that all PCI read and write operations are
448 If Address > 0x0FFFFFFF, then ASSERT().
449 If Address is not aligned on a 16-bit boundary, then ASSERT().
451 @param Address Address that encodes the PCI Bus, Device, Function and
453 @param AndData The value to AND with the PCI configuration register.
455 @return The value written back to the PCI configuration register.
466 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
467 value, followed a bitwise inclusive OR with another 16-bit value.
469 Reads the 16-bit PCI configuration register specified by Address, performs a
470 bitwise AND between the read result and the value specified by AndData,
471 performs a bitwise inclusive OR between the result of the AND operation and
472 the value specified by OrData, and writes the result to the 16-bit PCI
473 configuration register specified by Address. The value written to the PCI
474 configuration register is returned. This function must guarantee that all PCI
475 read and write operations are serialized.
477 If Address > 0x0FFFFFFF, then ASSERT().
478 If Address is not aligned on a 16-bit boundary, then ASSERT().
480 @param Address Address that encodes the PCI Bus, Device, Function and
482 @param AndData The value to AND with the PCI configuration register.
483 @param OrData The value to OR with the result of the AND operation.
485 @return The value written back to the PCI configuration register.
490 PciExpressAndThenOr16 (
497 Reads a bit field of a PCI configuration register.
499 Reads the bit field in a 16-bit PCI configuration register. The bit field is
500 specified by the StartBit and the EndBit. The value of the bit field is
503 If Address > 0x0FFFFFFF, then ASSERT().
504 If Address is not aligned on a 16-bit boundary, then ASSERT().
505 If StartBit is greater than 15, then ASSERT().
506 If EndBit is greater than 15, then ASSERT().
507 If EndBit is less than StartBit, then ASSERT().
509 @param Address PCI configuration register to read.
510 @param StartBit The ordinal of the least significant bit in the bit field.
512 @param EndBit The ordinal of the most significant bit in the bit field.
515 @return The value of the bit field read from the PCI configuration register.
520 PciExpressBitFieldRead16 (
527 Writes a bit field to a PCI configuration register.
529 Writes Value to the bit field of the PCI configuration register. The bit
530 field is specified by the StartBit and the EndBit. All other bits in the
531 destination PCI configuration register are preserved. The new value of the
532 16-bit register is returned.
534 If Address > 0x0FFFFFFF, then ASSERT().
535 If Address is not aligned on a 16-bit boundary, then ASSERT().
536 If StartBit is greater than 15, then ASSERT().
537 If EndBit is greater than 15, then ASSERT().
538 If EndBit is less than StartBit, then ASSERT().
540 @param Address PCI configuration register to write.
541 @param StartBit The ordinal of the least significant bit in the bit field.
543 @param EndBit The ordinal of the most significant bit in the bit field.
545 @param Value New value of the bit field.
547 @return The value written back to the PCI configuration register.
552 PciExpressBitFieldWrite16 (
560 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
561 writes the result back to the bit field in the 16-bit port.
563 Reads the 16-bit PCI configuration register specified by Address, performs a
564 bitwise inclusive OR between the read result and the value specified by
565 OrData, and writes the result to the 16-bit PCI configuration register
566 specified by Address. The value written to the PCI configuration register is
567 returned. This function must guarantee that all PCI read and write operations
568 are serialized. Extra left bits in OrData are stripped.
570 If Address > 0x0FFFFFFF, then ASSERT().
571 If Address is not aligned on a 16-bit boundary, then ASSERT().
572 If StartBit is greater than 15, then ASSERT().
573 If EndBit is greater than 15, then ASSERT().
574 If EndBit is less than StartBit, then ASSERT().
576 @param Address PCI configuration register to write.
577 @param StartBit The ordinal of the least significant bit in the bit field.
579 @param EndBit The ordinal of the most significant bit in the bit field.
581 @param OrData The value to OR with the PCI configuration register.
583 @return The value written back to the PCI configuration register.
588 PciExpressBitFieldOr16 (
596 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
597 AND, and writes the result back to the bit field in the 16-bit register.
599 Reads the 16-bit PCI configuration register specified by Address, performs a
600 bitwise AND between the read result and the value specified by AndData, and
601 writes the result to the 16-bit PCI configuration register specified by
602 Address. The value written to the PCI configuration register is returned.
603 This function must guarantee that all PCI read and write operations are
604 serialized. Extra left bits in AndData are stripped.
606 If Address > 0x0FFFFFFF, then ASSERT().
607 If Address is not aligned on a 16-bit boundary, then ASSERT().
608 If StartBit is greater than 15, then ASSERT().
609 If EndBit is greater than 15, then ASSERT().
610 If EndBit is less than StartBit, then ASSERT().
612 @param Address PCI configuration register to write.
613 @param StartBit The ordinal of the least significant bit in the bit field.
615 @param EndBit The ordinal of the most significant bit in the bit field.
617 @param AndData The value to AND with the PCI configuration register.
619 @return The value written back to the PCI configuration register.
624 PciExpressBitFieldAnd16 (
632 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
633 bitwise inclusive OR, and writes the result back to the bit field in the
636 Reads the 16-bit PCI configuration register specified by Address, performs a
637 bitwise AND followed by a bitwise inclusive OR between the read result and
638 the value specified by AndData, and writes the result to the 16-bit PCI
639 configuration register specified by Address. The value written to the PCI
640 configuration register is returned. This function must guarantee that all PCI
641 read and write operations are serialized. Extra left bits in both AndData and
644 If Address > 0x0FFFFFFF, then ASSERT().
645 If Address is not aligned on a 16-bit boundary, then ASSERT().
646 If StartBit is greater than 15, then ASSERT().
647 If EndBit is greater than 15, then ASSERT().
648 If EndBit is less than StartBit, then ASSERT().
650 @param Address PCI configuration register to write.
651 @param StartBit The ordinal of the least significant bit in the bit field.
653 @param EndBit The ordinal of the most significant bit in the bit field.
655 @param AndData The value to AND with the PCI configuration register.
656 @param OrData The value to OR with the result of the AND operation.
658 @return The value written back to the PCI configuration register.
663 PciExpressBitFieldAndThenOr16 (
672 Reads a 32-bit PCI configuration register.
674 Reads and returns the 32-bit PCI configuration register specified by Address.
675 This function must guarantee that all PCI read and write operations are
678 If Address > 0x0FFFFFFF, then ASSERT().
679 If Address is not aligned on a 32-bit boundary, then ASSERT().
681 @param Address Address that encodes the PCI Bus, Device, Function and
684 @return The read value from the PCI configuration register.
694 Writes a 32-bit PCI configuration register.
696 Writes the 32-bit PCI configuration register specified by Address with the
697 value specified by Value. Value is returned. This function must guarantee
698 that all PCI read and write operations are serialized.
700 If Address > 0x0FFFFFFF, then ASSERT().
701 If Address is not aligned on a 32-bit boundary, then ASSERT().
703 @param Address Address that encodes the PCI Bus, Device, Function and
705 @param Value The value to write.
707 @return The value written to the PCI configuration register.
718 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
721 Reads the 32-bit PCI configuration register specified by Address, performs a
722 bitwise inclusive OR between the read result and the value specified by
723 OrData, and writes the result to the 32-bit PCI configuration register
724 specified by Address. The value written to the PCI configuration register is
725 returned. This function must guarantee that all PCI read and write operations
728 If Address > 0x0FFFFFFF, then ASSERT().
729 If Address is not aligned on a 32-bit boundary, then ASSERT().
731 @param Address Address that encodes the PCI Bus, Device, Function and
733 @param OrData The value to OR with the PCI configuration register.
735 @return The value written back to the PCI configuration register.
746 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
749 Reads the 32-bit PCI configuration register specified by Address, performs a
750 bitwise AND between the read result and the value specified by AndData, and
751 writes the result to the 32-bit PCI configuration register specified by
752 Address. The value written to the PCI configuration register is returned.
753 This function must guarantee that all PCI read and write operations are
756 If Address > 0x0FFFFFFF, then ASSERT().
757 If Address is not aligned on a 32-bit boundary, then ASSERT().
759 @param Address Address that encodes the PCI Bus, Device, Function and
761 @param AndData The value to AND with the PCI configuration register.
763 @return The value written back to the PCI configuration register.
774 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
775 value, followed a bitwise inclusive OR with another 32-bit value.
777 Reads the 32-bit PCI configuration register specified by Address, performs a
778 bitwise AND between the read result and the value specified by AndData,
779 performs a bitwise inclusive OR between the result of the AND operation and
780 the value specified by OrData, and writes the result to the 32-bit PCI
781 configuration register specified by Address. The value written to the PCI
782 configuration register is returned. This function must guarantee that all PCI
783 read and write operations are serialized.
785 If Address > 0x0FFFFFFF, then ASSERT().
786 If Address is not aligned on a 32-bit boundary, then ASSERT().
788 @param Address Address that encodes the PCI Bus, Device, Function and
790 @param AndData The value to AND with the PCI configuration register.
791 @param OrData The value to OR with the result of the AND operation.
793 @return The value written back to the PCI configuration register.
798 PciExpressAndThenOr32 (
805 Reads a bit field of a PCI configuration register.
807 Reads the bit field in a 32-bit PCI configuration register. The bit field is
808 specified by the StartBit and the EndBit. The value of the bit field is
811 If Address > 0x0FFFFFFF, then ASSERT().
812 If Address is not aligned on a 32-bit boundary, then ASSERT().
813 If StartBit is greater than 31, then ASSERT().
814 If EndBit is greater than 31, then ASSERT().
815 If EndBit is less than StartBit, then ASSERT().
817 @param Address PCI configuration register to read.
818 @param StartBit The ordinal of the least significant bit in the bit field.
820 @param EndBit The ordinal of the most significant bit in the bit field.
823 @return The value of the bit field read from the PCI configuration register.
828 PciExpressBitFieldRead32 (
835 Writes a bit field to a PCI configuration register.
837 Writes Value to the bit field of the PCI configuration register. The bit
838 field is specified by the StartBit and the EndBit. All other bits in the
839 destination PCI configuration register are preserved. The new value of the
840 32-bit register is returned.
842 If Address > 0x0FFFFFFF, then ASSERT().
843 If Address is not aligned on a 32-bit boundary, then ASSERT().
844 If StartBit is greater than 31, then ASSERT().
845 If EndBit is greater than 31, then ASSERT().
846 If EndBit is less than StartBit, then ASSERT().
848 @param Address PCI configuration register to write.
849 @param StartBit The ordinal of the least significant bit in the bit field.
851 @param EndBit The ordinal of the most significant bit in the bit field.
853 @param Value New value of the bit field.
855 @return The value written back to the PCI configuration register.
860 PciExpressBitFieldWrite32 (
868 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
869 writes the result back to the bit field in the 32-bit port.
871 Reads the 32-bit PCI configuration register specified by Address, performs a
872 bitwise inclusive OR between the read result and the value specified by
873 OrData, and writes the result to the 32-bit PCI configuration register
874 specified by Address. The value written to the PCI configuration register is
875 returned. This function must guarantee that all PCI read and write operations
876 are serialized. Extra left bits in OrData are stripped.
878 If Address > 0x0FFFFFFF, then ASSERT().
879 If Address is not aligned on a 32-bit boundary, then ASSERT().
880 If StartBit is greater than 31, then ASSERT().
881 If EndBit is greater than 31, then ASSERT().
882 If EndBit is less than StartBit, then ASSERT().
884 @param Address PCI configuration register to write.
885 @param StartBit The ordinal of the least significant bit in the bit field.
887 @param EndBit The ordinal of the most significant bit in the bit field.
889 @param OrData The value to OR with the PCI configuration register.
891 @return The value written back to the PCI configuration register.
896 PciExpressBitFieldOr32 (
904 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
905 AND, and writes the result back to the bit field in the 32-bit register.
907 Reads the 32-bit PCI configuration register specified by Address, performs a
908 bitwise AND between the read result and the value specified by AndData, and
909 writes the result to the 32-bit PCI configuration register specified by
910 Address. The value written to the PCI configuration register is returned.
911 This function must guarantee that all PCI read and write operations are
912 serialized. Extra left bits in AndData are stripped.
914 If Address > 0x0FFFFFFF, then ASSERT().
915 If Address is not aligned on a 32-bit boundary, then ASSERT().
916 If StartBit is greater than 31, then ASSERT().
917 If EndBit is greater than 31, then ASSERT().
918 If EndBit is less than StartBit, then ASSERT().
920 @param Address PCI configuration register to write.
921 @param StartBit The ordinal of the least significant bit in the bit field.
923 @param EndBit The ordinal of the most significant bit in the bit field.
925 @param AndData The value to AND with the PCI configuration register.
927 @return The value written back to the PCI configuration register.
932 PciExpressBitFieldAnd32 (
940 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
941 bitwise inclusive OR, and writes the result back to the bit field in the
944 Reads the 32-bit PCI configuration register specified by Address, performs a
945 bitwise AND followed by a bitwise inclusive OR between the read result and
946 the value specified by AndData, and writes the result to the 32-bit PCI
947 configuration register specified by Address. The value written to the PCI
948 configuration register is returned. This function must guarantee that all PCI
949 read and write operations are serialized. Extra left bits in both AndData and
952 If Address > 0x0FFFFFFF, then ASSERT().
953 If Address is not aligned on a 32-bit boundary, then ASSERT().
954 If StartBit is greater than 31, then ASSERT().
955 If EndBit is greater than 31, then ASSERT().
956 If EndBit is less than StartBit, then ASSERT().
958 @param Address PCI configuration register to write.
959 @param StartBit The ordinal of the least significant bit in the bit field.
961 @param EndBit The ordinal of the most significant bit in the bit field.
963 @param AndData The value to AND with the PCI configuration register.
964 @param OrData The value to OR with the result of the AND operation.
966 @return The value written back to the PCI configuration register.
971 PciExpressBitFieldAndThenOr32 (
980 Reads a range of PCI configuration registers into a caller supplied buffer.
982 Reads the range of PCI configuration registers specified by StartAddress and
983 Size into the buffer specified by Buffer. This function only allows the PCI
984 configuration registers from a single PCI function to be read. Size is
985 returned. When possible 32-bit PCI configuration read cycles are used to read
986 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
987 and 16-bit PCI configuration read cycles may be used at the beginning and the
990 If StartAddress > 0x0FFFFFFF, then ASSERT().
991 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
992 If Size > 0 and Buffer is NULL, then ASSERT().
994 @param StartAddress Starting address that encodes the PCI Bus, Device,
995 Function and Register.
996 @param Size Size in bytes of the transfer.
997 @param Buffer Pointer to a buffer receiving the data read.
999 @return Size read data from StartAddress.
1004 PciExpressReadBuffer (
1005 IN UINTN StartAddress
,
1011 Copies the data in a caller supplied buffer to a specified range of PCI
1012 configuration space.
1014 Writes the range of PCI configuration registers specified by StartAddress and
1015 Size from the buffer specified by Buffer. This function only allows the PCI
1016 configuration registers from a single PCI function to be written. Size is
1017 returned. When possible 32-bit PCI configuration write cycles are used to
1018 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1019 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1020 and the end of the range.
1022 If StartAddress > 0x0FFFFFFF, then ASSERT().
1023 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1024 If Size > 0 and Buffer is NULL, then ASSERT().
1026 @param StartAddress Starting address that encodes the PCI Bus, Device,
1027 Function and Register.
1028 @param Size Size in bytes of the transfer.
1029 @param Buffer Pointer to a buffer containing the data to write.
1031 @return Size written to StartAddress.
1036 PciExpressWriteBuffer (
1037 IN UINTN StartAddress
,