]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Library/PciExpressLib.h
2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be though the 256 MB PCI Express MMIO window whose base address
6 is defined by PcdPciExpressBaseAddress.
8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __PCI_EXPRESS_LIB_H__
20 #define __PCI_EXPRESS_LIB_H__
23 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
24 address that can be passed to the PCI Library functions.
26 Computes an address that is compatible with the PCI Library functions. The
27 unused upper bits of Bus, Device, Function and Register are stripped prior to
28 the generation of the address.
30 @param Bus PCI Bus number. Range 0..255.
31 @param Device PCI Device number. Range 0..31.
32 @param Function PCI Function number. Range 0..7.
33 @param Register PCI Register number. Range 0..4095.
35 @return The encode PCI address.
38 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
39 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
42 Registers a PCI device so PCI configuration registers may be accessed after
43 SetVirtualAddressMap().
45 Registers the PCI device specified by Address so all the PCI configuration
46 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
49 If Address > 0x0FFFFFFF, then ASSERT().
51 @param Address Address that encodes the PCI Bus, Device, Function and
54 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
55 @retval RETURN_UNSUPPORTED An attempt was made to call this function
56 after ExitBootServices().
57 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
58 at runtime could not be mapped.
59 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
60 complete the registration.
65 PciExpressRegisterForRuntimeAccess (
70 Reads an 8-bit PCI configuration register.
72 Reads and returns the 8-bit PCI configuration register specified by Address.
73 This function must guarantee that all PCI read and write operations are
76 If Address > 0x0FFFFFFF, then ASSERT().
78 @param Address Address that encodes the PCI Bus, Device, Function and
81 @return The read value from the PCI configuration register.
91 Writes an 8-bit PCI configuration register.
93 Writes the 8-bit PCI configuration register specified by Address with the
94 value specified by Value. Value is returned. This function must guarantee
95 that all PCI read and write operations are serialized.
97 If Address > 0x0FFFFFFF, then ASSERT().
99 @param Address Address that encodes the PCI Bus, Device, Function and
101 @param Value The value to write.
103 @return The value written to the PCI configuration register.
114 Performs a bitwise OR of an 8-bit PCI configuration register with
117 Reads the 8-bit PCI configuration register specified by Address, performs a
118 bitwise OR between the read result and the value specified by
119 OrData, and writes the result to the 8-bit PCI configuration register
120 specified by Address. The value written to the PCI configuration register is
121 returned. This function must guarantee that all PCI read and write operations
124 If Address > 0x0FFFFFFF, then ASSERT().
126 @param Address Address that encodes the PCI Bus, Device, Function and
128 @param OrData The value to OR with the PCI configuration register.
130 @return The value written back to the PCI configuration register.
141 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
144 Reads the 8-bit PCI configuration register specified by Address, performs a
145 bitwise AND between the read result and the value specified by AndData, and
146 writes the result to the 8-bit PCI configuration register specified by
147 Address. The value written to the PCI configuration register is returned.
148 This function must guarantee that all PCI read and write operations are
151 If Address > 0x0FFFFFFF, then ASSERT().
153 @param Address Address that encodes the PCI Bus, Device, Function and
155 @param AndData The value to AND with the PCI configuration register.
157 @return The value written back to the PCI configuration register.
168 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
169 value, followed a bitwise OR with another 8-bit value.
171 Reads the 8-bit PCI configuration register specified by Address, performs a
172 bitwise AND between the read result and the value specified by AndData,
173 performs a bitwise OR between the result of the AND operation and
174 the value specified by OrData, and writes the result to the 8-bit PCI
175 configuration register specified by Address. The value written to the PCI
176 configuration register is returned. This function must guarantee that all PCI
177 read and write operations are serialized.
179 If Address > 0x0FFFFFFF, then ASSERT().
181 @param Address Address that encodes the PCI Bus, Device, Function and
183 @param AndData The value to AND with the PCI configuration register.
184 @param OrData The value to OR with the result of the AND operation.
186 @return The value written back to the PCI configuration register.
191 PciExpressAndThenOr8 (
198 Reads a bit field of a PCI configuration register.
200 Reads the bit field in an 8-bit PCI configuration register. The bit field is
201 specified by the StartBit and the EndBit. The value of the bit field is
204 If Address > 0x0FFFFFFF, then ASSERT().
205 If StartBit is greater than 7, then ASSERT().
206 If EndBit is greater than 7, then ASSERT().
207 If EndBit is less than StartBit, then ASSERT().
209 @param Address PCI configuration register to read.
210 @param StartBit The ordinal of the least significant bit in the bit field.
212 @param EndBit The ordinal of the most significant bit in the bit field.
215 @return The value of the bit field read from the PCI configuration register.
220 PciExpressBitFieldRead8 (
227 Writes a bit field to a PCI configuration register.
229 Writes Value to the bit field of the PCI configuration register. The bit
230 field is specified by the StartBit and the EndBit. All other bits in the
231 destination PCI configuration register are preserved. The new value of the
232 8-bit register is returned.
234 If Address > 0x0FFFFFFF, then ASSERT().
235 If StartBit is greater than 7, then ASSERT().
236 If EndBit is greater than 7, then ASSERT().
237 If EndBit is less than StartBit, then ASSERT().
239 @param Address PCI configuration register to write.
240 @param StartBit The ordinal of the least significant bit in the bit field.
242 @param EndBit The ordinal of the most significant bit in the bit field.
244 @param Value New value of the bit field.
246 @return The value written back to the PCI configuration register.
251 PciExpressBitFieldWrite8 (
259 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
260 writes the result back to the bit field in the 8-bit port.
262 Reads the 8-bit PCI configuration register specified by Address, performs a
263 bitwise OR between the read result and the value specified by
264 OrData, and writes the result to the 8-bit PCI configuration register
265 specified by Address. The value written to the PCI configuration register is
266 returned. This function must guarantee that all PCI read and write operations
267 are serialized. Extra left bits in OrData are stripped.
269 If Address > 0x0FFFFFFF, then ASSERT().
270 If StartBit is greater than 7, then ASSERT().
271 If EndBit is greater than 7, then ASSERT().
272 If EndBit is less than StartBit, then ASSERT().
274 @param Address PCI configuration register to write.
275 @param StartBit The ordinal of the least significant bit in the bit field.
277 @param EndBit The ordinal of the most significant bit in the bit field.
279 @param OrData The value to OR with the PCI configuration register.
281 @return The value written back to the PCI configuration register.
286 PciExpressBitFieldOr8 (
294 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
295 AND, and writes the result back to the bit field in the 8-bit register.
297 Reads the 8-bit PCI configuration register specified by Address, performs a
298 bitwise AND between the read result and the value specified by AndData, and
299 writes the result to the 8-bit PCI configuration register specified by
300 Address. The value written to the PCI configuration register is returned.
301 This function must guarantee that all PCI read and write operations are
302 serialized. Extra left bits in AndData are stripped.
304 If Address > 0x0FFFFFFF, then ASSERT().
305 If StartBit is greater than 7, then ASSERT().
306 If EndBit is greater than 7, then ASSERT().
307 If EndBit is less than StartBit, then ASSERT().
309 @param Address PCI configuration register to write.
310 @param StartBit The ordinal of the least significant bit in the bit field.
312 @param EndBit The ordinal of the most significant bit in the bit field.
314 @param AndData The value to AND with the PCI configuration register.
316 @return The value written back to the PCI configuration register.
321 PciExpressBitFieldAnd8 (
329 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
330 bitwise OR, and writes the result back to the bit field in the
333 Reads the 8-bit PCI configuration register specified by Address, performs a
334 bitwise AND followed by a bitwise OR between the read result and
335 the value specified by AndData, and writes the result to the 8-bit PCI
336 configuration register specified by Address. The value written to the PCI
337 configuration register is returned. This function must guarantee that all PCI
338 read and write operations are serialized. Extra left bits in both AndData and
341 If Address > 0x0FFFFFFF, then ASSERT().
342 If StartBit is greater than 7, then ASSERT().
343 If EndBit is greater than 7, then ASSERT().
344 If EndBit is less than StartBit, then ASSERT().
346 @param Address PCI configuration register to write.
347 @param StartBit The ordinal of the least significant bit in the bit field.
349 @param EndBit The ordinal of the most significant bit in the bit field.
351 @param AndData The value to AND with the PCI configuration register.
352 @param OrData The value to OR with the result of the AND operation.
354 @return The value written back to the PCI configuration register.
359 PciExpressBitFieldAndThenOr8 (
368 Reads a 16-bit PCI configuration register.
370 Reads and returns the 16-bit PCI configuration register specified by Address.
371 This function must guarantee that all PCI read and write operations are
374 If Address > 0x0FFFFFFF, then ASSERT().
375 If Address is not aligned on a 16-bit boundary, then ASSERT().
377 @param Address Address that encodes the PCI Bus, Device, Function and
380 @return The read value from the PCI configuration register.
390 Writes a 16-bit PCI configuration register.
392 Writes the 16-bit PCI configuration register specified by Address with the
393 value specified by Value. Value is returned. This function must guarantee
394 that all PCI read and write operations are serialized.
396 If Address > 0x0FFFFFFF, then ASSERT().
397 If Address is not aligned on a 16-bit boundary, then ASSERT().
399 @param Address Address that encodes the PCI Bus, Device, Function and
401 @param Value The value to write.
403 @return The value written to the PCI configuration register.
414 Performs a bitwise OR of a 16-bit PCI configuration register with
417 Reads the 16-bit PCI configuration register specified by Address, performs a
418 bitwise OR between the read result and the value specified by
419 OrData, and writes the result to the 16-bit PCI configuration register
420 specified by Address. The value written to the PCI configuration register is
421 returned. This function must guarantee that all PCI read and write operations
424 If Address > 0x0FFFFFFF, then ASSERT().
425 If Address is not aligned on a 16-bit boundary, then ASSERT().
427 @param Address Address that encodes the PCI Bus, Device, Function and
429 @param OrData The value to OR with the PCI configuration register.
431 @return The value written back to the PCI configuration register.
442 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
445 Reads the 16-bit PCI configuration register specified by Address, performs a
446 bitwise AND between the read result and the value specified by AndData, and
447 writes the result to the 16-bit PCI configuration register specified by
448 Address. The value written to the PCI configuration register is returned.
449 This function must guarantee that all PCI read and write operations are
452 If Address > 0x0FFFFFFF, then ASSERT().
453 If Address is not aligned on a 16-bit boundary, then ASSERT().
455 @param Address Address that encodes the PCI Bus, Device, Function and
457 @param AndData The value to AND with the PCI configuration register.
459 @return The value written back to the PCI configuration register.
470 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
471 value, followed a bitwise OR with another 16-bit value.
473 Reads the 16-bit PCI configuration register specified by Address, performs a
474 bitwise AND between the read result and the value specified by AndData,
475 performs a bitwise OR between the result of the AND operation and
476 the value specified by OrData, and writes the result to the 16-bit PCI
477 configuration register specified by Address. The value written to the PCI
478 configuration register is returned. This function must guarantee that all PCI
479 read and write operations are serialized.
481 If Address > 0x0FFFFFFF, then ASSERT().
482 If Address is not aligned on a 16-bit boundary, then ASSERT().
484 @param Address Address that encodes the PCI Bus, Device, Function and
486 @param AndData The value to AND with the PCI configuration register.
487 @param OrData The value to OR with the result of the AND operation.
489 @return The value written back to the PCI configuration register.
494 PciExpressAndThenOr16 (
501 Reads a bit field of a PCI configuration register.
503 Reads the bit field in a 16-bit PCI configuration register. The bit field is
504 specified by the StartBit and the EndBit. The value of the bit field is
507 If Address > 0x0FFFFFFF, then ASSERT().
508 If Address is not aligned on a 16-bit boundary, then ASSERT().
509 If StartBit is greater than 15, then ASSERT().
510 If EndBit is greater than 15, then ASSERT().
511 If EndBit is less than StartBit, then ASSERT().
513 @param Address PCI configuration register to read.
514 @param StartBit The ordinal of the least significant bit in the bit field.
516 @param EndBit The ordinal of the most significant bit in the bit field.
519 @return The value of the bit field read from the PCI configuration register.
524 PciExpressBitFieldRead16 (
531 Writes a bit field to a PCI configuration register.
533 Writes Value to the bit field of the PCI configuration register. The bit
534 field is specified by the StartBit and the EndBit. All other bits in the
535 destination PCI configuration register are preserved. The new value of the
536 16-bit register is returned.
538 If Address > 0x0FFFFFFF, then ASSERT().
539 If Address is not aligned on a 16-bit boundary, then ASSERT().
540 If StartBit is greater than 15, then ASSERT().
541 If EndBit is greater than 15, then ASSERT().
542 If EndBit is less than StartBit, then ASSERT().
544 @param Address PCI configuration register to write.
545 @param StartBit The ordinal of the least significant bit in the bit field.
547 @param EndBit The ordinal of the most significant bit in the bit field.
549 @param Value New value of the bit field.
551 @return The value written back to the PCI configuration register.
556 PciExpressBitFieldWrite16 (
564 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
565 writes the result back to the bit field in the 16-bit port.
567 Reads the 16-bit PCI configuration register specified by Address, performs a
568 bitwise OR between the read result and the value specified by
569 OrData, and writes the result to the 16-bit PCI configuration register
570 specified by Address. The value written to the PCI configuration register is
571 returned. This function must guarantee that all PCI read and write operations
572 are serialized. Extra left bits in OrData are stripped.
574 If Address > 0x0FFFFFFF, then ASSERT().
575 If Address is not aligned on a 16-bit boundary, then ASSERT().
576 If StartBit is greater than 15, then ASSERT().
577 If EndBit is greater than 15, then ASSERT().
578 If EndBit is less than StartBit, then ASSERT().
580 @param Address PCI configuration register to write.
581 @param StartBit The ordinal of the least significant bit in the bit field.
583 @param EndBit The ordinal of the most significant bit in the bit field.
585 @param OrData The value to OR with the PCI configuration register.
587 @return The value written back to the PCI configuration register.
592 PciExpressBitFieldOr16 (
600 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
601 AND, and writes the result back to the bit field in the 16-bit register.
603 Reads the 16-bit PCI configuration register specified by Address, performs a
604 bitwise AND between the read result and the value specified by AndData, and
605 writes the result to the 16-bit PCI configuration register specified by
606 Address. The value written to the PCI configuration register is returned.
607 This function must guarantee that all PCI read and write operations are
608 serialized. Extra left bits in AndData are stripped.
610 If Address > 0x0FFFFFFF, then ASSERT().
611 If Address is not aligned on a 16-bit boundary, then ASSERT().
612 If StartBit is greater than 15, then ASSERT().
613 If EndBit is greater than 15, then ASSERT().
614 If EndBit is less than StartBit, then ASSERT().
616 @param Address PCI configuration register to write.
617 @param StartBit The ordinal of the least significant bit in the bit field.
619 @param EndBit The ordinal of the most significant bit in the bit field.
621 @param AndData The value to AND with the PCI configuration register.
623 @return The value written back to the PCI configuration register.
628 PciExpressBitFieldAnd16 (
636 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
637 bitwise OR, and writes the result back to the bit field in the
640 Reads the 16-bit PCI configuration register specified by Address, performs a
641 bitwise AND followed by a bitwise OR between the read result and
642 the value specified by AndData, and writes the result to the 16-bit PCI
643 configuration register specified by Address. The value written to the PCI
644 configuration register is returned. This function must guarantee that all PCI
645 read and write operations are serialized. Extra left bits in both AndData and
648 If Address > 0x0FFFFFFF, then ASSERT().
649 If Address is not aligned on a 16-bit boundary, then ASSERT().
650 If StartBit is greater than 15, then ASSERT().
651 If EndBit is greater than 15, then ASSERT().
652 If EndBit is less than StartBit, then ASSERT().
654 @param Address PCI configuration register to write.
655 @param StartBit The ordinal of the least significant bit in the bit field.
657 @param EndBit The ordinal of the most significant bit in the bit field.
659 @param AndData The value to AND with the PCI configuration register.
660 @param OrData The value to OR with the result of the AND operation.
662 @return The value written back to the PCI configuration register.
667 PciExpressBitFieldAndThenOr16 (
676 Reads a 32-bit PCI configuration register.
678 Reads and returns the 32-bit PCI configuration register specified by Address.
679 This function must guarantee that all PCI read and write operations are
682 If Address > 0x0FFFFFFF, then ASSERT().
683 If Address is not aligned on a 32-bit boundary, then ASSERT().
685 @param Address Address that encodes the PCI Bus, Device, Function and
688 @return The read value from the PCI configuration register.
698 Writes a 32-bit PCI configuration register.
700 Writes the 32-bit PCI configuration register specified by Address with the
701 value specified by Value. Value is returned. This function must guarantee
702 that all PCI read and write operations are serialized.
704 If Address > 0x0FFFFFFF, then ASSERT().
705 If Address is not aligned on a 32-bit boundary, then ASSERT().
707 @param Address Address that encodes the PCI Bus, Device, Function and
709 @param Value The value to write.
711 @return The value written to the PCI configuration register.
722 Performs a bitwise OR of a 32-bit PCI configuration register with
725 Reads the 32-bit PCI configuration register specified by Address, performs a
726 bitwise OR between the read result and the value specified by
727 OrData, and writes the result to the 32-bit PCI configuration register
728 specified by Address. The value written to the PCI configuration register is
729 returned. This function must guarantee that all PCI read and write operations
732 If Address > 0x0FFFFFFF, then ASSERT().
733 If Address is not aligned on a 32-bit boundary, then ASSERT().
735 @param Address Address that encodes the PCI Bus, Device, Function and
737 @param OrData The value to OR with the PCI configuration register.
739 @return The value written back to the PCI configuration register.
750 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
753 Reads the 32-bit PCI configuration register specified by Address, performs a
754 bitwise AND between the read result and the value specified by AndData, and
755 writes the result to the 32-bit PCI configuration register specified by
756 Address. The value written to the PCI configuration register is returned.
757 This function must guarantee that all PCI read and write operations are
760 If Address > 0x0FFFFFFF, then ASSERT().
761 If Address is not aligned on a 32-bit boundary, then ASSERT().
763 @param Address Address that encodes the PCI Bus, Device, Function and
765 @param AndData The value to AND with the PCI configuration register.
767 @return The value written back to the PCI configuration register.
778 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
779 value, followed a bitwise OR with another 32-bit value.
781 Reads the 32-bit PCI configuration register specified by Address, performs a
782 bitwise AND between the read result and the value specified by AndData,
783 performs a bitwise OR between the result of the AND operation and
784 the value specified by OrData, and writes the result to the 32-bit PCI
785 configuration register specified by Address. The value written to the PCI
786 configuration register is returned. This function must guarantee that all PCI
787 read and write operations are serialized.
789 If Address > 0x0FFFFFFF, then ASSERT().
790 If Address is not aligned on a 32-bit boundary, then ASSERT().
792 @param Address Address that encodes the PCI Bus, Device, Function and
794 @param AndData The value to AND with the PCI configuration register.
795 @param OrData The value to OR with the result of the AND operation.
797 @return The value written back to the PCI configuration register.
802 PciExpressAndThenOr32 (
809 Reads a bit field of a PCI configuration register.
811 Reads the bit field in a 32-bit PCI configuration register. The bit field is
812 specified by the StartBit and the EndBit. The value of the bit field is
815 If Address > 0x0FFFFFFF, then ASSERT().
816 If Address is not aligned on a 32-bit boundary, then ASSERT().
817 If StartBit is greater than 31, then ASSERT().
818 If EndBit is greater than 31, then ASSERT().
819 If EndBit is less than StartBit, then ASSERT().
821 @param Address PCI configuration register to read.
822 @param StartBit The ordinal of the least significant bit in the bit field.
824 @param EndBit The ordinal of the most significant bit in the bit field.
827 @return The value of the bit field read from the PCI configuration register.
832 PciExpressBitFieldRead32 (
839 Writes a bit field to a PCI configuration register.
841 Writes Value to the bit field of the PCI configuration register. The bit
842 field is specified by the StartBit and the EndBit. All other bits in the
843 destination PCI configuration register are preserved. The new value of the
844 32-bit register is returned.
846 If Address > 0x0FFFFFFF, then ASSERT().
847 If Address is not aligned on a 32-bit boundary, then ASSERT().
848 If StartBit is greater than 31, then ASSERT().
849 If EndBit is greater than 31, then ASSERT().
850 If EndBit is less than StartBit, then ASSERT().
852 @param Address PCI configuration register to write.
853 @param StartBit The ordinal of the least significant bit in the bit field.
855 @param EndBit The ordinal of the most significant bit in the bit field.
857 @param Value New value of the bit field.
859 @return The value written back to the PCI configuration register.
864 PciExpressBitFieldWrite32 (
872 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
873 writes the result back to the bit field in the 32-bit port.
875 Reads the 32-bit PCI configuration register specified by Address, performs a
876 bitwise OR between the read result and the value specified by
877 OrData, and writes the result to the 32-bit PCI configuration register
878 specified by Address. The value written to the PCI configuration register is
879 returned. This function must guarantee that all PCI read and write operations
880 are serialized. Extra left bits in OrData are stripped.
882 If Address > 0x0FFFFFFF, then ASSERT().
883 If Address is not aligned on a 32-bit boundary, then ASSERT().
884 If StartBit is greater than 31, then ASSERT().
885 If EndBit is greater than 31, then ASSERT().
886 If EndBit is less than StartBit, then ASSERT().
888 @param Address PCI configuration register to write.
889 @param StartBit The ordinal of the least significant bit in the bit field.
891 @param EndBit The ordinal of the most significant bit in the bit field.
893 @param OrData The value to OR with the PCI configuration register.
895 @return The value written back to the PCI configuration register.
900 PciExpressBitFieldOr32 (
908 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
909 AND, and writes the result back to the bit field in the 32-bit register.
911 Reads the 32-bit PCI configuration register specified by Address, performs a
912 bitwise AND between the read result and the value specified by AndData, and
913 writes the result to the 32-bit PCI configuration register specified by
914 Address. The value written to the PCI configuration register is returned.
915 This function must guarantee that all PCI read and write operations are
916 serialized. Extra left bits in AndData are stripped.
918 If Address > 0x0FFFFFFF, then ASSERT().
919 If Address is not aligned on a 32-bit boundary, then ASSERT().
920 If StartBit is greater than 31, then ASSERT().
921 If EndBit is greater than 31, then ASSERT().
922 If EndBit is less than StartBit, then ASSERT().
924 @param Address PCI configuration register to write.
925 @param StartBit The ordinal of the least significant bit in the bit field.
927 @param EndBit The ordinal of the most significant bit in the bit field.
929 @param AndData The value to AND with the PCI configuration register.
931 @return The value written back to the PCI configuration register.
936 PciExpressBitFieldAnd32 (
944 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
945 bitwise OR, and writes the result back to the bit field in the
948 Reads the 32-bit PCI configuration register specified by Address, performs a
949 bitwise AND followed by a bitwise OR between the read result and
950 the value specified by AndData, and writes the result to the 32-bit PCI
951 configuration register specified by Address. The value written to the PCI
952 configuration register is returned. This function must guarantee that all PCI
953 read and write operations are serialized. Extra left bits in both AndData and
956 If Address > 0x0FFFFFFF, then ASSERT().
957 If Address is not aligned on a 32-bit boundary, then ASSERT().
958 If StartBit is greater than 31, then ASSERT().
959 If EndBit is greater than 31, then ASSERT().
960 If EndBit is less than StartBit, then ASSERT().
962 @param Address PCI configuration register to write.
963 @param StartBit The ordinal of the least significant bit in the bit field.
965 @param EndBit The ordinal of the most significant bit in the bit field.
967 @param AndData The value to AND with the PCI configuration register.
968 @param OrData The value to OR with the result of the AND operation.
970 @return The value written back to the PCI configuration register.
975 PciExpressBitFieldAndThenOr32 (
984 Reads a range of PCI configuration registers into a caller supplied buffer.
986 Reads the range of PCI configuration registers specified by StartAddress and
987 Size into the buffer specified by Buffer. This function only allows the PCI
988 configuration registers from a single PCI function to be read. Size is
989 returned. When possible 32-bit PCI configuration read cycles are used to read
990 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
991 and 16-bit PCI configuration read cycles may be used at the beginning and the
994 If StartAddress > 0x0FFFFFFF, then ASSERT().
995 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
996 If Size > 0 and Buffer is NULL, then ASSERT().
998 @param StartAddress Starting address that encodes the PCI Bus, Device,
999 Function and Register.
1000 @param Size Size in bytes of the transfer.
1001 @param Buffer Pointer to a buffer receiving the data read.
1003 @return Size read data from StartAddress.
1008 PciExpressReadBuffer (
1009 IN UINTN StartAddress
,
1015 Copies the data in a caller supplied buffer to a specified range of PCI
1016 configuration space.
1018 Writes the range of PCI configuration registers specified by StartAddress and
1019 Size from the buffer specified by Buffer. This function only allows the PCI
1020 configuration registers from a single PCI function to be written. Size is
1021 returned. When possible 32-bit PCI configuration write cycles are used to
1022 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1023 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1024 and the end of the range.
1026 If StartAddress > 0x0FFFFFFF, then ASSERT().
1027 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1028 If Size > 0 and Buffer is NULL, then ASSERT().
1030 @param StartAddress Starting address that encodes the PCI Bus, Device,
1031 Function and Register.
1032 @param Size Size in bytes of the transfer.
1033 @param Buffer Pointer to a buffer containing the data to write.
1035 @return Size written to StartAddress.
1040 PciExpressWriteBuffer (
1041 IN UINTN StartAddress
,