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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Library/PciExpressLib.h
2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
4 Copyright (c) 2006 - 2008, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef __PCI_EXPRESS_LIB_H__
16 #define __PCI_EXPRESS_LIB_H__
19 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
20 address that can be passed to the PCI Library functions.
22 Computes an address that is compatible with the PCI Library functions. The
23 unused upper bits of Bus, Device, Function and Register are stripped prior to
24 the generation of the address.
26 @param Bus PCI Bus number. Range 0..255.
27 @param Device PCI Device number. Range 0..31.
28 @param Function PCI Function number. Range 0..7.
29 @param Register PCI Register number. Range 0..4095.
31 @return The encode PCI address.
34 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
35 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
38 Reads an 8-bit PCI configuration register.
40 Reads and returns the 8-bit PCI configuration register specified by Address.
41 This function must guarantee that all PCI read and write operations are
44 If Address > 0x0FFFFFFF, then ASSERT().
46 @param Address Address that encodes the PCI Bus, Device, Function and
49 @return The read value from the PCI configuration register.
59 Writes an 8-bit PCI configuration register.
61 Writes the 8-bit PCI configuration register specified by Address with the
62 value specified by Value. Value is returned. This function must guarantee
63 that all PCI read and write operations are serialized.
65 If Address > 0x0FFFFFFF, then ASSERT().
67 @param Address Address that encodes the PCI Bus, Device, Function and
69 @param Value The value to write.
71 @return The value written to the PCI configuration register.
82 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
85 Reads the 8-bit PCI configuration register specified by Address, performs a
86 bitwise inclusive OR between the read result and the value specified by
87 OrData, and writes the result to the 8-bit PCI configuration register
88 specified by Address. The value written to the PCI configuration register is
89 returned. This function must guarantee that all PCI read and write operations
92 If Address > 0x0FFFFFFF, then ASSERT().
94 @param Address Address that encodes the PCI Bus, Device, Function and
96 @param OrData The value to OR with the PCI configuration register.
98 @return The value written back to the PCI configuration register.
109 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
112 Reads the 8-bit PCI configuration register specified by Address, performs a
113 bitwise AND between the read result and the value specified by AndData, and
114 writes the result to the 8-bit PCI configuration register specified by
115 Address. The value written to the PCI configuration register is returned.
116 This function must guarantee that all PCI read and write operations are
119 If Address > 0x0FFFFFFF, then ASSERT().
121 @param Address Address that encodes the PCI Bus, Device, Function and
123 @param AndData The value to AND with the PCI configuration register.
125 @return The value written back to the PCI configuration register.
136 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
137 value, followed a bitwise inclusive OR with another 8-bit value.
139 Reads the 8-bit PCI configuration register specified by Address, performs a
140 bitwise AND between the read result and the value specified by AndData,
141 performs a bitwise inclusive OR between the result of the AND operation and
142 the value specified by OrData, and writes the result to the 8-bit PCI
143 configuration register specified by Address. The value written to the PCI
144 configuration register is returned. This function must guarantee that all PCI
145 read and write operations are serialized.
147 If Address > 0x0FFFFFFF, then ASSERT().
149 @param Address Address that encodes the PCI Bus, Device, Function and
151 @param AndData The value to AND with the PCI configuration register.
152 @param OrData The value to OR with the result of the AND operation.
154 @return The value written back to the PCI configuration register.
159 PciExpressAndThenOr8 (
166 Reads a bit field of a PCI configuration register.
168 Reads the bit field in an 8-bit PCI configuration register. The bit field is
169 specified by the StartBit and the EndBit. The value of the bit field is
172 If Address > 0x0FFFFFFF, then ASSERT().
173 If StartBit is greater than 7, then ASSERT().
174 If EndBit is greater than 7, then ASSERT().
175 If EndBit is less than StartBit, then ASSERT().
177 @param Address PCI configuration register to read.
178 @param StartBit The ordinal of the least significant bit in the bit field.
180 @param EndBit The ordinal of the most significant bit in the bit field.
183 @return The value of the bit field read from the PCI configuration register.
188 PciExpressBitFieldRead8 (
195 Writes a bit field to a PCI configuration register.
197 Writes Value to the bit field of the PCI configuration register. The bit
198 field is specified by the StartBit and the EndBit. All other bits in the
199 destination PCI configuration register are preserved. The new value of the
200 8-bit register is returned.
202 If Address > 0x0FFFFFFF, then ASSERT().
203 If StartBit is greater than 7, then ASSERT().
204 If EndBit is greater than 7, then ASSERT().
205 If EndBit is less than StartBit, then ASSERT().
207 @param Address PCI configuration register to write.
208 @param StartBit The ordinal of the least significant bit in the bit field.
210 @param EndBit The ordinal of the most significant bit in the bit field.
212 @param Value New value of the bit field.
214 @return The value written back to the PCI configuration register.
219 PciExpressBitFieldWrite8 (
227 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
228 writes the result back to the bit field in the 8-bit port.
230 Reads the 8-bit PCI configuration register specified by Address, performs a
231 bitwise inclusive OR between the read result and the value specified by
232 OrData, and writes the result to the 8-bit PCI configuration register
233 specified by Address. The value written to the PCI configuration register is
234 returned. This function must guarantee that all PCI read and write operations
235 are serialized. Extra left bits in OrData are stripped.
237 If Address > 0x0FFFFFFF, then ASSERT().
238 If StartBit is greater than 7, then ASSERT().
239 If EndBit is greater than 7, then ASSERT().
240 If EndBit is less than StartBit, then ASSERT().
242 @param Address PCI configuration register to write.
243 @param StartBit The ordinal of the least significant bit in the bit field.
245 @param EndBit The ordinal of the most significant bit in the bit field.
247 @param OrData The value to OR with the PCI configuration register.
249 @return The value written back to the PCI configuration register.
254 PciExpressBitFieldOr8 (
262 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
263 AND, and writes the result back to the bit field in the 8-bit register.
265 Reads the 8-bit PCI configuration register specified by Address, performs a
266 bitwise AND between the read result and the value specified by AndData, and
267 writes the result to the 8-bit PCI configuration register specified by
268 Address. The value written to the PCI configuration register is returned.
269 This function must guarantee that all PCI read and write operations are
270 serialized. Extra left bits in AndData are stripped.
272 If Address > 0x0FFFFFFF, then ASSERT().
273 If StartBit is greater than 7, then ASSERT().
274 If EndBit is greater than 7, then ASSERT().
275 If EndBit is less than StartBit, then ASSERT().
277 @param Address PCI configuration register to write.
278 @param StartBit The ordinal of the least significant bit in the bit field.
280 @param EndBit The ordinal of the most significant bit in the bit field.
282 @param AndData The value to AND with the PCI configuration register.
284 @return The value written back to the PCI configuration register.
289 PciExpressBitFieldAnd8 (
297 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
298 bitwise inclusive OR, and writes the result back to the bit field in the
301 Reads the 8-bit PCI configuration register specified by Address, performs a
302 bitwise AND followed by a bitwise inclusive OR between the read result and
303 the value specified by AndData, and writes the result to the 8-bit PCI
304 configuration register specified by Address. The value written to the PCI
305 configuration register is returned. This function must guarantee that all PCI
306 read and write operations are serialized. Extra left bits in both AndData and
309 If Address > 0x0FFFFFFF, then ASSERT().
310 If StartBit is greater than 7, then ASSERT().
311 If EndBit is greater than 7, then ASSERT().
312 If EndBit is less than StartBit, then ASSERT().
314 @param Address PCI configuration register to write.
315 @param StartBit The ordinal of the least significant bit in the bit field.
317 @param EndBit The ordinal of the most significant bit in the bit field.
319 @param AndData The value to AND with the PCI configuration register.
320 @param OrData The value to OR with the result of the AND operation.
322 @return The value written back to the PCI configuration register.
327 PciExpressBitFieldAndThenOr8 (
336 Reads a 16-bit PCI configuration register.
338 Reads and returns the 16-bit PCI configuration register specified by Address.
339 This function must guarantee that all PCI read and write operations are
342 If Address > 0x0FFFFFFF, then ASSERT().
343 If Address is not aligned on a 16-bit boundary, then ASSERT().
345 @param Address Address that encodes the PCI Bus, Device, Function and
348 @return The read value from the PCI configuration register.
358 Writes a 16-bit PCI configuration register.
360 Writes the 16-bit PCI configuration register specified by Address with the
361 value specified by Value. Value is returned. This function must guarantee
362 that all PCI read and write operations are serialized.
364 If Address > 0x0FFFFFFF, then ASSERT().
365 If Address is not aligned on a 16-bit boundary, then ASSERT().
367 @param Address Address that encodes the PCI Bus, Device, Function and
369 @param Value The value to write.
371 @return The value written to the PCI configuration register.
382 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
385 Reads the 16-bit PCI configuration register specified by Address, performs a
386 bitwise inclusive OR between the read result and the value specified by
387 OrData, and writes the result to the 16-bit PCI configuration register
388 specified by Address. The value written to the PCI configuration register is
389 returned. This function must guarantee that all PCI read and write operations
392 If Address > 0x0FFFFFFF, then ASSERT().
393 If Address is not aligned on a 16-bit boundary, then ASSERT().
395 @param Address Address that encodes the PCI Bus, Device, Function and
397 @param OrData The value to OR with the PCI configuration register.
399 @return The value written back to the PCI configuration register.
410 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
413 Reads the 16-bit PCI configuration register specified by Address, performs a
414 bitwise AND between the read result and the value specified by AndData, and
415 writes the result to the 16-bit PCI configuration register specified by
416 Address. The value written to the PCI configuration register is returned.
417 This function must guarantee that all PCI read and write operations are
420 If Address > 0x0FFFFFFF, then ASSERT().
421 If Address is not aligned on a 16-bit boundary, then ASSERT().
423 @param Address Address that encodes the PCI Bus, Device, Function and
425 @param AndData The value to AND with the PCI configuration register.
427 @return The value written back to the PCI configuration register.
438 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
439 value, followed a bitwise inclusive OR with another 16-bit value.
441 Reads the 16-bit PCI configuration register specified by Address, performs a
442 bitwise AND between the read result and the value specified by AndData,
443 performs a bitwise inclusive OR between the result of the AND operation and
444 the value specified by OrData, and writes the result to the 16-bit PCI
445 configuration register specified by Address. The value written to the PCI
446 configuration register is returned. This function must guarantee that all PCI
447 read and write operations are serialized.
449 If Address > 0x0FFFFFFF, then ASSERT().
450 If Address is not aligned on a 16-bit boundary, then ASSERT().
452 @param Address Address that encodes the PCI Bus, Device, Function and
454 @param AndData The value to AND with the PCI configuration register.
455 @param OrData The value to OR with the result of the AND operation.
457 @return The value written back to the PCI configuration register.
462 PciExpressAndThenOr16 (
469 Reads a bit field of a PCI configuration register.
471 Reads the bit field in a 16-bit PCI configuration register. The bit field is
472 specified by the StartBit and the EndBit. The value of the bit field is
475 If Address > 0x0FFFFFFF, then ASSERT().
476 If Address is not aligned on a 16-bit boundary, then ASSERT().
477 If StartBit is greater than 15, then ASSERT().
478 If EndBit is greater than 15, then ASSERT().
479 If EndBit is less than StartBit, then ASSERT().
481 @param Address PCI configuration register to read.
482 @param StartBit The ordinal of the least significant bit in the bit field.
484 @param EndBit The ordinal of the most significant bit in the bit field.
487 @return The value of the bit field read from the PCI configuration register.
492 PciExpressBitFieldRead16 (
499 Writes a bit field to a PCI configuration register.
501 Writes Value to the bit field of the PCI configuration register. The bit
502 field is specified by the StartBit and the EndBit. All other bits in the
503 destination PCI configuration register are preserved. The new value of the
504 16-bit register is returned.
506 If Address > 0x0FFFFFFF, then ASSERT().
507 If Address is not aligned on a 16-bit boundary, then ASSERT().
508 If StartBit is greater than 15, then ASSERT().
509 If EndBit is greater than 15, then ASSERT().
510 If EndBit is less than StartBit, then ASSERT().
512 @param Address PCI configuration register to write.
513 @param StartBit The ordinal of the least significant bit in the bit field.
515 @param EndBit The ordinal of the most significant bit in the bit field.
517 @param Value New value of the bit field.
519 @return The value written back to the PCI configuration register.
524 PciExpressBitFieldWrite16 (
532 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
533 writes the result back to the bit field in the 16-bit port.
535 Reads the 16-bit PCI configuration register specified by Address, performs a
536 bitwise inclusive OR between the read result and the value specified by
537 OrData, and writes the result to the 16-bit PCI configuration register
538 specified by Address. The value written to the PCI configuration register is
539 returned. This function must guarantee that all PCI read and write operations
540 are serialized. Extra left bits in OrData are stripped.
542 If Address > 0x0FFFFFFF, then ASSERT().
543 If Address is not aligned on a 16-bit boundary, then ASSERT().
544 If StartBit is greater than 15, then ASSERT().
545 If EndBit is greater than 15, then ASSERT().
546 If EndBit is less than StartBit, then ASSERT().
548 @param Address PCI configuration register to write.
549 @param StartBit The ordinal of the least significant bit in the bit field.
551 @param EndBit The ordinal of the most significant bit in the bit field.
553 @param OrData The value to OR with the PCI configuration register.
555 @return The value written back to the PCI configuration register.
560 PciExpressBitFieldOr16 (
568 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
569 AND, and writes the result back to the bit field in the 16-bit register.
571 Reads the 16-bit PCI configuration register specified by Address, performs a
572 bitwise AND between the read result and the value specified by AndData, and
573 writes the result to the 16-bit PCI configuration register specified by
574 Address. The value written to the PCI configuration register is returned.
575 This function must guarantee that all PCI read and write operations are
576 serialized. Extra left bits in AndData are stripped.
578 If Address > 0x0FFFFFFF, then ASSERT().
579 If Address is not aligned on a 16-bit boundary, then ASSERT().
580 If StartBit is greater than 15, then ASSERT().
581 If EndBit is greater than 15, then ASSERT().
582 If EndBit is less than StartBit, then ASSERT().
584 @param Address PCI configuration register to write.
585 @param StartBit The ordinal of the least significant bit in the bit field.
587 @param EndBit The ordinal of the most significant bit in the bit field.
589 @param AndData The value to AND with the PCI configuration register.
591 @return The value written back to the PCI configuration register.
596 PciExpressBitFieldAnd16 (
604 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
605 bitwise inclusive OR, and writes the result back to the bit field in the
608 Reads the 16-bit PCI configuration register specified by Address, performs a
609 bitwise AND followed by a bitwise inclusive OR between the read result and
610 the value specified by AndData, and writes the result to the 16-bit PCI
611 configuration register specified by Address. The value written to the PCI
612 configuration register is returned. This function must guarantee that all PCI
613 read and write operations are serialized. Extra left bits in both AndData and
616 If Address > 0x0FFFFFFF, then ASSERT().
617 If Address is not aligned on a 16-bit boundary, then ASSERT().
618 If StartBit is greater than 15, then ASSERT().
619 If EndBit is greater than 15, then ASSERT().
620 If EndBit is less than StartBit, then ASSERT().
622 @param Address PCI configuration register to write.
623 @param StartBit The ordinal of the least significant bit in the bit field.
625 @param EndBit The ordinal of the most significant bit in the bit field.
627 @param AndData The value to AND with the PCI configuration register.
628 @param OrData The value to OR with the result of the AND operation.
630 @return The value written back to the PCI configuration register.
635 PciExpressBitFieldAndThenOr16 (
644 Reads a 32-bit PCI configuration register.
646 Reads and returns the 32-bit PCI configuration register specified by Address.
647 This function must guarantee that all PCI read and write operations are
650 If Address > 0x0FFFFFFF, then ASSERT().
651 If Address is not aligned on a 32-bit boundary, then ASSERT().
653 @param Address Address that encodes the PCI Bus, Device, Function and
656 @return The read value from the PCI configuration register.
666 Writes a 32-bit PCI configuration register.
668 Writes the 32-bit PCI configuration register specified by Address with the
669 value specified by Value. Value is returned. This function must guarantee
670 that all PCI read and write operations are serialized.
672 If Address > 0x0FFFFFFF, then ASSERT().
673 If Address is not aligned on a 32-bit boundary, then ASSERT().
675 @param Address Address that encodes the PCI Bus, Device, Function and
677 @param Value The value to write.
679 @return The value written to the PCI configuration register.
690 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
693 Reads the 32-bit PCI configuration register specified by Address, performs a
694 bitwise inclusive OR between the read result and the value specified by
695 OrData, and writes the result to the 32-bit PCI configuration register
696 specified by Address. The value written to the PCI configuration register is
697 returned. This function must guarantee that all PCI read and write operations
700 If Address > 0x0FFFFFFF, then ASSERT().
701 If Address is not aligned on a 32-bit boundary, then ASSERT().
703 @param Address Address that encodes the PCI Bus, Device, Function and
705 @param OrData The value to OR with the PCI configuration register.
707 @return The value written back to the PCI configuration register.
718 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
721 Reads the 32-bit PCI configuration register specified by Address, performs a
722 bitwise AND between the read result and the value specified by AndData, and
723 writes the result to the 32-bit PCI configuration register specified by
724 Address. The value written to the PCI configuration register is returned.
725 This function must guarantee that all PCI read and write operations are
728 If Address > 0x0FFFFFFF, then ASSERT().
729 If Address is not aligned on a 32-bit boundary, then ASSERT().
731 @param Address Address that encodes the PCI Bus, Device, Function and
733 @param AndData The value to AND with the PCI configuration register.
735 @return The value written back to the PCI configuration register.
746 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
747 value, followed a bitwise inclusive OR with another 32-bit value.
749 Reads the 32-bit PCI configuration register specified by Address, performs a
750 bitwise AND between the read result and the value specified by AndData,
751 performs a bitwise inclusive OR between the result of the AND operation and
752 the value specified by OrData, and writes the result to the 32-bit PCI
753 configuration register specified by Address. The value written to the PCI
754 configuration register is returned. This function must guarantee that all PCI
755 read and write operations are serialized.
757 If Address > 0x0FFFFFFF, then ASSERT().
758 If Address is not aligned on a 32-bit boundary, then ASSERT().
760 @param Address Address that encodes the PCI Bus, Device, Function and
762 @param AndData The value to AND with the PCI configuration register.
763 @param OrData The value to OR with the result of the AND operation.
765 @return The value written back to the PCI configuration register.
770 PciExpressAndThenOr32 (
777 Reads a bit field of a PCI configuration register.
779 Reads the bit field in a 32-bit PCI configuration register. The bit field is
780 specified by the StartBit and the EndBit. The value of the bit field is
783 If Address > 0x0FFFFFFF, then ASSERT().
784 If Address is not aligned on a 32-bit boundary, then ASSERT().
785 If StartBit is greater than 31, then ASSERT().
786 If EndBit is greater than 31, then ASSERT().
787 If EndBit is less than StartBit, then ASSERT().
789 @param Address PCI configuration register to read.
790 @param StartBit The ordinal of the least significant bit in the bit field.
792 @param EndBit The ordinal of the most significant bit in the bit field.
795 @return The value of the bit field read from the PCI configuration register.
800 PciExpressBitFieldRead32 (
807 Writes a bit field to a PCI configuration register.
809 Writes Value to the bit field of the PCI configuration register. The bit
810 field is specified by the StartBit and the EndBit. All other bits in the
811 destination PCI configuration register are preserved. The new value of the
812 32-bit register is returned.
814 If Address > 0x0FFFFFFF, then ASSERT().
815 If Address is not aligned on a 32-bit boundary, then ASSERT().
816 If StartBit is greater than 31, then ASSERT().
817 If EndBit is greater than 31, then ASSERT().
818 If EndBit is less than StartBit, then ASSERT().
820 @param Address PCI configuration register to write.
821 @param StartBit The ordinal of the least significant bit in the bit field.
823 @param EndBit The ordinal of the most significant bit in the bit field.
825 @param Value New value of the bit field.
827 @return The value written back to the PCI configuration register.
832 PciExpressBitFieldWrite32 (
840 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
841 writes the result back to the bit field in the 32-bit port.
843 Reads the 32-bit PCI configuration register specified by Address, performs a
844 bitwise inclusive OR between the read result and the value specified by
845 OrData, and writes the result to the 32-bit PCI configuration register
846 specified by Address. The value written to the PCI configuration register is
847 returned. This function must guarantee that all PCI read and write operations
848 are serialized. Extra left bits in OrData are stripped.
850 If Address > 0x0FFFFFFF, then ASSERT().
851 If Address is not aligned on a 32-bit boundary, then ASSERT().
852 If StartBit is greater than 31, then ASSERT().
853 If EndBit is greater than 31, then ASSERT().
854 If EndBit is less than StartBit, then ASSERT().
856 @param Address PCI configuration register to write.
857 @param StartBit The ordinal of the least significant bit in the bit field.
859 @param EndBit The ordinal of the most significant bit in the bit field.
861 @param OrData The value to OR with the PCI configuration register.
863 @return The value written back to the PCI configuration register.
868 PciExpressBitFieldOr32 (
876 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
877 AND, and writes the result back to the bit field in the 32-bit register.
879 Reads the 32-bit PCI configuration register specified by Address, performs a
880 bitwise AND between the read result and the value specified by AndData, and
881 writes the result to the 32-bit PCI configuration register specified by
882 Address. The value written to the PCI configuration register is returned.
883 This function must guarantee that all PCI read and write operations are
884 serialized. Extra left bits in AndData are stripped.
886 If Address > 0x0FFFFFFF, then ASSERT().
887 If Address is not aligned on a 32-bit boundary, then ASSERT().
888 If StartBit is greater than 31, then ASSERT().
889 If EndBit is greater than 31, then ASSERT().
890 If EndBit is less than StartBit, then ASSERT().
892 @param Address PCI configuration register to write.
893 @param StartBit The ordinal of the least significant bit in the bit field.
895 @param EndBit The ordinal of the most significant bit in the bit field.
897 @param AndData The value to AND with the PCI configuration register.
899 @return The value written back to the PCI configuration register.
904 PciExpressBitFieldAnd32 (
912 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
913 bitwise inclusive OR, and writes the result back to the bit field in the
916 Reads the 32-bit PCI configuration register specified by Address, performs a
917 bitwise AND followed by a bitwise inclusive OR between the read result and
918 the value specified by AndData, and writes the result to the 32-bit PCI
919 configuration register specified by Address. The value written to the PCI
920 configuration register is returned. This function must guarantee that all PCI
921 read and write operations are serialized. Extra left bits in both AndData and
924 If Address > 0x0FFFFFFF, then ASSERT().
925 If Address is not aligned on a 32-bit boundary, then ASSERT().
926 If StartBit is greater than 31, then ASSERT().
927 If EndBit is greater than 31, then ASSERT().
928 If EndBit is less than StartBit, then ASSERT().
930 @param Address PCI configuration register to write.
931 @param StartBit The ordinal of the least significant bit in the bit field.
933 @param EndBit The ordinal of the most significant bit in the bit field.
935 @param AndData The value to AND with the PCI configuration register.
936 @param OrData The value to OR with the result of the AND operation.
938 @return The value written back to the PCI configuration register.
943 PciExpressBitFieldAndThenOr32 (
952 Reads a range of PCI configuration registers into a caller supplied buffer.
954 Reads the range of PCI configuration registers specified by StartAddress and
955 Size into the buffer specified by Buffer. This function only allows the PCI
956 configuration registers from a single PCI function to be read. Size is
957 returned. When possible 32-bit PCI configuration read cycles are used to read
958 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
959 and 16-bit PCI configuration read cycles may be used at the beginning and the
962 If StartAddress > 0x0FFFFFFF, then ASSERT().
963 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
964 If Size > 0 and Buffer is NULL, then ASSERT().
966 @param StartAddress Starting address that encodes the PCI Bus, Device,
967 Function and Register.
968 @param Size Size in bytes of the transfer.
969 @param Buffer Pointer to a buffer receiving the data read.
971 @return Size read daata from StartAddress.
976 PciExpressReadBuffer (
977 IN UINTN StartAddress
,
983 Copies the data in a caller supplied buffer to a specified range of PCI
986 Writes the range of PCI configuration registers specified by StartAddress and
987 Size from the buffer specified by Buffer. This function only allows the PCI
988 configuration registers from a single PCI function to be written. Size is
989 returned. When possible 32-bit PCI configuration write cycles are used to
990 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
991 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
992 and the end of the range.
994 If StartAddress > 0x0FFFFFFF, then ASSERT().
995 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
996 If Size > 0 and Buffer is NULL, then ASSERT().
998 @param StartAddress Starting address that encodes the PCI Bus, Device,
999 Function and Register.
1000 @param Size Size in bytes of the transfer.
1001 @param Buffer Pointer to a buffer containing the data to write.
1003 @return Size written to StartAddress.
1008 PciExpressWriteBuffer (
1009 IN UINTN StartAddress
,