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2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
6 is defined by PcdPciExpressBaseAddress.
8 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #ifndef __PCI_EXPRESS_LIB_H__
14 #define __PCI_EXPRESS_LIB_H__
16 #include <IndustryStandard/PciExpress21.h>
19 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
20 address that can be passed to the PCI Library functions.
22 Computes an address that is compatible with the PCI Library functions. The
23 unused upper bits of Bus, Device, Function and Register are stripped prior to
24 the generation of the address.
26 @param Bus PCI Bus number. Range 0..255.
27 @param Device PCI Device number. Range 0..31.
28 @param Function PCI Function number. Range 0..7.
29 @param Register PCI Register number. Range 0..4095.
31 @return The encode PCI address.
34 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
37 Registers a PCI device so PCI configuration registers may be accessed after
38 SetVirtualAddressMap().
40 Registers the PCI device specified by Address so all the PCI configuration
41 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
44 If Address > 0x0FFFFFFF, then ASSERT().
46 @param Address Address that encodes the PCI Bus, Device, Function and
49 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
50 @retval RETURN_UNSUPPORTED An attempt was made to call this function
51 after ExitBootServices().
52 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
53 at runtime could not be mapped.
54 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
55 complete the registration.
60 PciExpressRegisterForRuntimeAccess (
65 Reads an 8-bit PCI configuration register.
67 Reads and returns the 8-bit PCI configuration register specified by Address.
68 This function must guarantee that all PCI read and write operations are
71 If Address > 0x0FFFFFFF, then ASSERT().
73 @param Address Address that encodes the PCI Bus, Device, Function and
76 @return The read value from the PCI configuration register.
86 Writes an 8-bit PCI configuration register.
88 Writes the 8-bit PCI configuration register specified by Address with the
89 value specified by Value. Value is returned. This function must guarantee
90 that all PCI read and write operations are serialized.
92 If Address > 0x0FFFFFFF, then ASSERT().
94 @param Address Address that encodes the PCI Bus, Device, Function and
96 @param Value The value to write.
98 @return The value written to the PCI configuration register.
109 Performs a bitwise OR of an 8-bit PCI configuration register with
112 Reads the 8-bit PCI configuration register specified by Address, performs a
113 bitwise OR between the read result and the value specified by
114 OrData, and writes the result to the 8-bit PCI configuration register
115 specified by Address. The value written to the PCI configuration register is
116 returned. This function must guarantee that all PCI read and write operations
119 If Address > 0x0FFFFFFF, then ASSERT().
121 @param Address Address that encodes the PCI Bus, Device, Function and
123 @param OrData The value to OR with the PCI configuration register.
125 @return The value written back to the PCI configuration register.
136 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
139 Reads the 8-bit PCI configuration register specified by Address, performs a
140 bitwise AND between the read result and the value specified by AndData, and
141 writes the result to the 8-bit PCI configuration register specified by
142 Address. The value written to the PCI configuration register is returned.
143 This function must guarantee that all PCI read and write operations are
146 If Address > 0x0FFFFFFF, then ASSERT().
148 @param Address Address that encodes the PCI Bus, Device, Function and
150 @param AndData The value to AND with the PCI configuration register.
152 @return The value written back to the PCI configuration register.
163 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
164 value, followed a bitwise OR with another 8-bit value.
166 Reads the 8-bit PCI configuration register specified by Address, performs a
167 bitwise AND between the read result and the value specified by AndData,
168 performs a bitwise OR between the result of the AND operation and
169 the value specified by OrData, and writes the result to the 8-bit PCI
170 configuration register specified by Address. The value written to the PCI
171 configuration register is returned. This function must guarantee that all PCI
172 read and write operations are serialized.
174 If Address > 0x0FFFFFFF, then ASSERT().
176 @param Address Address that encodes the PCI Bus, Device, Function and
178 @param AndData The value to AND with the PCI configuration register.
179 @param OrData The value to OR with the result of the AND operation.
181 @return The value written back to the PCI configuration register.
186 PciExpressAndThenOr8 (
193 Reads a bit field of a PCI configuration register.
195 Reads the bit field in an 8-bit PCI configuration register. The bit field is
196 specified by the StartBit and the EndBit. The value of the bit field is
199 If Address > 0x0FFFFFFF, then ASSERT().
200 If StartBit is greater than 7, then ASSERT().
201 If EndBit is greater than 7, then ASSERT().
202 If EndBit is less than StartBit, then ASSERT().
204 @param Address PCI configuration register to read.
205 @param StartBit The ordinal of the least significant bit in the bit field.
207 @param EndBit The ordinal of the most significant bit in the bit field.
210 @return The value of the bit field read from the PCI configuration register.
215 PciExpressBitFieldRead8 (
222 Writes a bit field to a PCI configuration register.
224 Writes Value to the bit field of the PCI configuration register. The bit
225 field is specified by the StartBit and the EndBit. All other bits in the
226 destination PCI configuration register are preserved. The new value of the
227 8-bit register is returned.
229 If Address > 0x0FFFFFFF, then ASSERT().
230 If StartBit is greater than 7, then ASSERT().
231 If EndBit is greater than 7, then ASSERT().
232 If EndBit is less than StartBit, then ASSERT().
233 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
235 @param Address PCI configuration register to write.
236 @param StartBit The ordinal of the least significant bit in the bit field.
238 @param EndBit The ordinal of the most significant bit in the bit field.
240 @param Value New value of the bit field.
242 @return The value written back to the PCI configuration register.
247 PciExpressBitFieldWrite8 (
255 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
256 writes the result back to the bit field in the 8-bit port.
258 Reads the 8-bit PCI configuration register specified by Address, performs a
259 bitwise OR between the read result and the value specified by
260 OrData, and writes the result to the 8-bit PCI configuration register
261 specified by Address. The value written to the PCI configuration register is
262 returned. This function must guarantee that all PCI read and write operations
263 are serialized. Extra left bits in OrData are stripped.
265 If Address > 0x0FFFFFFF, then ASSERT().
266 If StartBit is greater than 7, then ASSERT().
267 If EndBit is greater than 7, then ASSERT().
268 If EndBit is less than StartBit, then ASSERT().
269 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
271 @param Address PCI configuration register to write.
272 @param StartBit The ordinal of the least significant bit in the bit field.
274 @param EndBit The ordinal of the most significant bit in the bit field.
276 @param OrData The value to OR with the PCI configuration register.
278 @return The value written back to the PCI configuration register.
283 PciExpressBitFieldOr8 (
291 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
292 AND, and writes the result back to the bit field in the 8-bit register.
294 Reads the 8-bit PCI configuration register specified by Address, performs a
295 bitwise AND between the read result and the value specified by AndData, and
296 writes the result to the 8-bit PCI configuration register specified by
297 Address. The value written to the PCI configuration register is returned.
298 This function must guarantee that all PCI read and write operations are
299 serialized. Extra left bits in AndData are stripped.
301 If Address > 0x0FFFFFFF, then ASSERT().
302 If StartBit is greater than 7, then ASSERT().
303 If EndBit is greater than 7, then ASSERT().
304 If EndBit is less than StartBit, then ASSERT().
305 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
307 @param Address PCI configuration register to write.
308 @param StartBit The ordinal of the least significant bit in the bit field.
310 @param EndBit The ordinal of the most significant bit in the bit field.
312 @param AndData The value to AND with the PCI configuration register.
314 @return The value written back to the PCI configuration register.
319 PciExpressBitFieldAnd8 (
327 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
328 bitwise OR, and writes the result back to the bit field in the
331 Reads the 8-bit PCI configuration register specified by Address, performs a
332 bitwise AND followed by a bitwise OR between the read result and
333 the value specified by AndData, and writes the result to the 8-bit PCI
334 configuration register specified by Address. The value written to the PCI
335 configuration register is returned. This function must guarantee that all PCI
336 read and write operations are serialized. Extra left bits in both AndData and
339 If Address > 0x0FFFFFFF, then ASSERT().
340 If StartBit is greater than 7, then ASSERT().
341 If EndBit is greater than 7, then ASSERT().
342 If EndBit is less than StartBit, then ASSERT().
343 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
344 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
346 @param Address PCI configuration register to write.
347 @param StartBit The ordinal of the least significant bit in the bit field.
349 @param EndBit The ordinal of the most significant bit in the bit field.
351 @param AndData The value to AND with the PCI configuration register.
352 @param OrData The value to OR with the result of the AND operation.
354 @return The value written back to the PCI configuration register.
359 PciExpressBitFieldAndThenOr8 (
368 Reads a 16-bit PCI configuration register.
370 Reads and returns the 16-bit PCI configuration register specified by Address.
371 This function must guarantee that all PCI read and write operations are
374 If Address > 0x0FFFFFFF, then ASSERT().
375 If Address is not aligned on a 16-bit boundary, then ASSERT().
377 @param Address Address that encodes the PCI Bus, Device, Function and
380 @return The read value from the PCI configuration register.
390 Writes a 16-bit PCI configuration register.
392 Writes the 16-bit PCI configuration register specified by Address with the
393 value specified by Value. Value is returned. This function must guarantee
394 that all PCI read and write operations are serialized.
396 If Address > 0x0FFFFFFF, then ASSERT().
397 If Address is not aligned on a 16-bit boundary, then ASSERT().
399 @param Address Address that encodes the PCI Bus, Device, Function and
401 @param Value The value to write.
403 @return The value written to the PCI configuration register.
414 Performs a bitwise OR of a 16-bit PCI configuration register with
417 Reads the 16-bit PCI configuration register specified by Address, performs a
418 bitwise OR between the read result and the value specified by
419 OrData, and writes the result to the 16-bit PCI configuration register
420 specified by Address. The value written to the PCI configuration register is
421 returned. This function must guarantee that all PCI read and write operations
424 If Address > 0x0FFFFFFF, then ASSERT().
425 If Address is not aligned on a 16-bit boundary, then ASSERT().
427 @param Address Address that encodes the PCI Bus, Device, Function and
429 @param OrData The value to OR with the PCI configuration register.
431 @return The value written back to the PCI configuration register.
442 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
445 Reads the 16-bit PCI configuration register specified by Address, performs a
446 bitwise AND between the read result and the value specified by AndData, and
447 writes the result to the 16-bit PCI configuration register specified by
448 Address. The value written to the PCI configuration register is returned.
449 This function must guarantee that all PCI read and write operations are
452 If Address > 0x0FFFFFFF, then ASSERT().
453 If Address is not aligned on a 16-bit boundary, then ASSERT().
455 @param Address Address that encodes the PCI Bus, Device, Function and
457 @param AndData The value to AND with the PCI configuration register.
459 @return The value written back to the PCI configuration register.
470 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
471 value, followed a bitwise OR with another 16-bit value.
473 Reads the 16-bit PCI configuration register specified by Address, performs a
474 bitwise AND between the read result and the value specified by AndData,
475 performs a bitwise OR between the result of the AND operation and
476 the value specified by OrData, and writes the result to the 16-bit PCI
477 configuration register specified by Address. The value written to the PCI
478 configuration register is returned. This function must guarantee that all PCI
479 read and write operations are serialized.
481 If Address > 0x0FFFFFFF, then ASSERT().
482 If Address is not aligned on a 16-bit boundary, then ASSERT().
484 @param Address Address that encodes the PCI Bus, Device, Function and
486 @param AndData The value to AND with the PCI configuration register.
487 @param OrData The value to OR with the result of the AND operation.
489 @return The value written back to the PCI configuration register.
494 PciExpressAndThenOr16 (
501 Reads a bit field of a PCI configuration register.
503 Reads the bit field in a 16-bit PCI configuration register. The bit field is
504 specified by the StartBit and the EndBit. The value of the bit field is
507 If Address > 0x0FFFFFFF, then ASSERT().
508 If Address is not aligned on a 16-bit boundary, then ASSERT().
509 If StartBit is greater than 15, then ASSERT().
510 If EndBit is greater than 15, then ASSERT().
511 If EndBit is less than StartBit, then ASSERT().
513 @param Address PCI configuration register to read.
514 @param StartBit The ordinal of the least significant bit in the bit field.
516 @param EndBit The ordinal of the most significant bit in the bit field.
519 @return The value of the bit field read from the PCI configuration register.
524 PciExpressBitFieldRead16 (
531 Writes a bit field to a PCI configuration register.
533 Writes Value to the bit field of the PCI configuration register. The bit
534 field is specified by the StartBit and the EndBit. All other bits in the
535 destination PCI configuration register are preserved. The new value of the
536 16-bit register is returned.
538 If Address > 0x0FFFFFFF, then ASSERT().
539 If Address is not aligned on a 16-bit boundary, then ASSERT().
540 If StartBit is greater than 15, then ASSERT().
541 If EndBit is greater than 15, then ASSERT().
542 If EndBit is less than StartBit, then ASSERT().
543 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
545 @param Address PCI configuration register to write.
546 @param StartBit The ordinal of the least significant bit in the bit field.
548 @param EndBit The ordinal of the most significant bit in the bit field.
550 @param Value New value of the bit field.
552 @return The value written back to the PCI configuration register.
557 PciExpressBitFieldWrite16 (
565 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
566 writes the result back to the bit field in the 16-bit port.
568 Reads the 16-bit PCI configuration register specified by Address, performs a
569 bitwise OR between the read result and the value specified by
570 OrData, and writes the result to the 16-bit PCI configuration register
571 specified by Address. The value written to the PCI configuration register is
572 returned. This function must guarantee that all PCI read and write operations
573 are serialized. Extra left bits in OrData are stripped.
575 If Address > 0x0FFFFFFF, then ASSERT().
576 If Address is not aligned on a 16-bit boundary, then ASSERT().
577 If StartBit is greater than 15, then ASSERT().
578 If EndBit is greater than 15, then ASSERT().
579 If EndBit is less than StartBit, then ASSERT().
580 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
582 @param Address PCI configuration register to write.
583 @param StartBit The ordinal of the least significant bit in the bit field.
585 @param EndBit The ordinal of the most significant bit in the bit field.
587 @param OrData The value to OR with the PCI configuration register.
589 @return The value written back to the PCI configuration register.
594 PciExpressBitFieldOr16 (
602 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
603 AND, and writes the result back to the bit field in the 16-bit register.
605 Reads the 16-bit PCI configuration register specified by Address, performs a
606 bitwise AND between the read result and the value specified by AndData, and
607 writes the result to the 16-bit PCI configuration register specified by
608 Address. The value written to the PCI configuration register is returned.
609 This function must guarantee that all PCI read and write operations are
610 serialized. Extra left bits in AndData are stripped.
612 If Address > 0x0FFFFFFF, then ASSERT().
613 If Address is not aligned on a 16-bit boundary, then ASSERT().
614 If StartBit is greater than 15, then ASSERT().
615 If EndBit is greater than 15, then ASSERT().
616 If EndBit is less than StartBit, then ASSERT().
617 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
619 @param Address PCI configuration register to write.
620 @param StartBit The ordinal of the least significant bit in the bit field.
622 @param EndBit The ordinal of the most significant bit in the bit field.
624 @param AndData The value to AND with the PCI configuration register.
626 @return The value written back to the PCI configuration register.
631 PciExpressBitFieldAnd16 (
639 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
640 bitwise OR, and writes the result back to the bit field in the
643 Reads the 16-bit PCI configuration register specified by Address, performs a
644 bitwise AND followed by a bitwise OR between the read result and
645 the value specified by AndData, and writes the result to the 16-bit PCI
646 configuration register specified by Address. The value written to the PCI
647 configuration register is returned. This function must guarantee that all PCI
648 read and write operations are serialized. Extra left bits in both AndData and
651 If Address > 0x0FFFFFFF, then ASSERT().
652 If Address is not aligned on a 16-bit boundary, then ASSERT().
653 If StartBit is greater than 15, then ASSERT().
654 If EndBit is greater than 15, then ASSERT().
655 If EndBit is less than StartBit, then ASSERT().
656 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
657 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
659 @param Address PCI configuration register to write.
660 @param StartBit The ordinal of the least significant bit in the bit field.
662 @param EndBit The ordinal of the most significant bit in the bit field.
664 @param AndData The value to AND with the PCI configuration register.
665 @param OrData The value to OR with the result of the AND operation.
667 @return The value written back to the PCI configuration register.
672 PciExpressBitFieldAndThenOr16 (
681 Reads a 32-bit PCI configuration register.
683 Reads and returns the 32-bit PCI configuration register specified by Address.
684 This function must guarantee that all PCI read and write operations are
687 If Address > 0x0FFFFFFF, then ASSERT().
688 If Address is not aligned on a 32-bit boundary, then ASSERT().
690 @param Address Address that encodes the PCI Bus, Device, Function and
693 @return The read value from the PCI configuration register.
703 Writes a 32-bit PCI configuration register.
705 Writes the 32-bit PCI configuration register specified by Address with the
706 value specified by Value. Value is returned. This function must guarantee
707 that all PCI read and write operations are serialized.
709 If Address > 0x0FFFFFFF, then ASSERT().
710 If Address is not aligned on a 32-bit boundary, then ASSERT().
712 @param Address Address that encodes the PCI Bus, Device, Function and
714 @param Value The value to write.
716 @return The value written to the PCI configuration register.
727 Performs a bitwise OR of a 32-bit PCI configuration register with
730 Reads the 32-bit PCI configuration register specified by Address, performs a
731 bitwise OR between the read result and the value specified by
732 OrData, and writes the result to the 32-bit PCI configuration register
733 specified by Address. The value written to the PCI configuration register is
734 returned. This function must guarantee that all PCI read and write operations
737 If Address > 0x0FFFFFFF, then ASSERT().
738 If Address is not aligned on a 32-bit boundary, then ASSERT().
740 @param Address Address that encodes the PCI Bus, Device, Function and
742 @param OrData The value to OR with the PCI configuration register.
744 @return The value written back to the PCI configuration register.
755 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
758 Reads the 32-bit PCI configuration register specified by Address, performs a
759 bitwise AND between the read result and the value specified by AndData, and
760 writes the result to the 32-bit PCI configuration register specified by
761 Address. The value written to the PCI configuration register is returned.
762 This function must guarantee that all PCI read and write operations are
765 If Address > 0x0FFFFFFF, then ASSERT().
766 If Address is not aligned on a 32-bit boundary, then ASSERT().
768 @param Address Address that encodes the PCI Bus, Device, Function and
770 @param AndData The value to AND with the PCI configuration register.
772 @return The value written back to the PCI configuration register.
783 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
784 value, followed a bitwise OR with another 32-bit value.
786 Reads the 32-bit PCI configuration register specified by Address, performs a
787 bitwise AND between the read result and the value specified by AndData,
788 performs a bitwise OR between the result of the AND operation and
789 the value specified by OrData, and writes the result to the 32-bit PCI
790 configuration register specified by Address. The value written to the PCI
791 configuration register is returned. This function must guarantee that all PCI
792 read and write operations are serialized.
794 If Address > 0x0FFFFFFF, then ASSERT().
795 If Address is not aligned on a 32-bit boundary, then ASSERT().
797 @param Address Address that encodes the PCI Bus, Device, Function and
799 @param AndData The value to AND with the PCI configuration register.
800 @param OrData The value to OR with the result of the AND operation.
802 @return The value written back to the PCI configuration register.
807 PciExpressAndThenOr32 (
814 Reads a bit field of a PCI configuration register.
816 Reads the bit field in a 32-bit PCI configuration register. The bit field is
817 specified by the StartBit and the EndBit. The value of the bit field is
820 If Address > 0x0FFFFFFF, then ASSERT().
821 If Address is not aligned on a 32-bit boundary, then ASSERT().
822 If StartBit is greater than 31, then ASSERT().
823 If EndBit is greater than 31, then ASSERT().
824 If EndBit is less than StartBit, then ASSERT().
826 @param Address PCI configuration register to read.
827 @param StartBit The ordinal of the least significant bit in the bit field.
829 @param EndBit The ordinal of the most significant bit in the bit field.
832 @return The value of the bit field read from the PCI configuration register.
837 PciExpressBitFieldRead32 (
844 Writes a bit field to a PCI configuration register.
846 Writes Value to the bit field of the PCI configuration register. The bit
847 field is specified by the StartBit and the EndBit. All other bits in the
848 destination PCI configuration register are preserved. The new value of the
849 32-bit register is returned.
851 If Address > 0x0FFFFFFF, then ASSERT().
852 If Address is not aligned on a 32-bit boundary, then ASSERT().
853 If StartBit is greater than 31, then ASSERT().
854 If EndBit is greater than 31, then ASSERT().
855 If EndBit is less than StartBit, then ASSERT().
856 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
858 @param Address PCI configuration register to write.
859 @param StartBit The ordinal of the least significant bit in the bit field.
861 @param EndBit The ordinal of the most significant bit in the bit field.
863 @param Value New value of the bit field.
865 @return The value written back to the PCI configuration register.
870 PciExpressBitFieldWrite32 (
878 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
879 writes the result back to the bit field in the 32-bit port.
881 Reads the 32-bit PCI configuration register specified by Address, performs a
882 bitwise OR between the read result and the value specified by
883 OrData, and writes the result to the 32-bit PCI configuration register
884 specified by Address. The value written to the PCI configuration register is
885 returned. This function must guarantee that all PCI read and write operations
886 are serialized. Extra left bits in OrData are stripped.
888 If Address > 0x0FFFFFFF, then ASSERT().
889 If Address is not aligned on a 32-bit boundary, then ASSERT().
890 If StartBit is greater than 31, then ASSERT().
891 If EndBit is greater than 31, then ASSERT().
892 If EndBit is less than StartBit, then ASSERT().
893 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
895 @param Address PCI configuration register to write.
896 @param StartBit The ordinal of the least significant bit in the bit field.
898 @param EndBit The ordinal of the most significant bit in the bit field.
900 @param OrData The value to OR with the PCI configuration register.
902 @return The value written back to the PCI configuration register.
907 PciExpressBitFieldOr32 (
915 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
916 AND, and writes the result back to the bit field in the 32-bit register.
918 Reads the 32-bit PCI configuration register specified by Address, performs a
919 bitwise AND between the read result and the value specified by AndData, and
920 writes the result to the 32-bit PCI configuration register specified by
921 Address. The value written to the PCI configuration register is returned.
922 This function must guarantee that all PCI read and write operations are
923 serialized. Extra left bits in AndData are stripped.
925 If Address > 0x0FFFFFFF, then ASSERT().
926 If Address is not aligned on a 32-bit boundary, then ASSERT().
927 If StartBit is greater than 31, then ASSERT().
928 If EndBit is greater than 31, then ASSERT().
929 If EndBit is less than StartBit, then ASSERT().
930 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
932 @param Address PCI configuration register to write.
933 @param StartBit The ordinal of the least significant bit in the bit field.
935 @param EndBit The ordinal of the most significant bit in the bit field.
937 @param AndData The value to AND with the PCI configuration register.
939 @return The value written back to the PCI configuration register.
944 PciExpressBitFieldAnd32 (
952 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
953 bitwise OR, and writes the result back to the bit field in the
956 Reads the 32-bit PCI configuration register specified by Address, performs a
957 bitwise AND followed by a bitwise OR between the read result and
958 the value specified by AndData, and writes the result to the 32-bit PCI
959 configuration register specified by Address. The value written to the PCI
960 configuration register is returned. This function must guarantee that all PCI
961 read and write operations are serialized. Extra left bits in both AndData and
964 If Address > 0x0FFFFFFF, then ASSERT().
965 If Address is not aligned on a 32-bit boundary, then ASSERT().
966 If StartBit is greater than 31, then ASSERT().
967 If EndBit is greater than 31, then ASSERT().
968 If EndBit is less than StartBit, then ASSERT().
969 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
970 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
972 @param Address PCI configuration register to write.
973 @param StartBit The ordinal of the least significant bit in the bit field.
975 @param EndBit The ordinal of the most significant bit in the bit field.
977 @param AndData The value to AND with the PCI configuration register.
978 @param OrData The value to OR with the result of the AND operation.
980 @return The value written back to the PCI configuration register.
985 PciExpressBitFieldAndThenOr32 (
994 Reads a range of PCI configuration registers into a caller supplied buffer.
996 Reads the range of PCI configuration registers specified by StartAddress and
997 Size into the buffer specified by Buffer. This function only allows the PCI
998 configuration registers from a single PCI function to be read. Size is
999 returned. When possible 32-bit PCI configuration read cycles are used to read
1000 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1001 and 16-bit PCI configuration read cycles may be used at the beginning and the
1004 If StartAddress > 0x0FFFFFFF, then ASSERT().
1005 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1006 If Size > 0 and Buffer is NULL, then ASSERT().
1008 @param StartAddress Starting address that encodes the PCI Bus, Device,
1009 Function and Register.
1010 @param Size Size in bytes of the transfer.
1011 @param Buffer Pointer to a buffer receiving the data read.
1013 @return Size read data from StartAddress.
1018 PciExpressReadBuffer (
1019 IN UINTN StartAddress
,
1025 Copies the data in a caller supplied buffer to a specified range of PCI
1026 configuration space.
1028 Writes the range of PCI configuration registers specified by StartAddress and
1029 Size from the buffer specified by Buffer. This function only allows the PCI
1030 configuration registers from a single PCI function to be written. Size is
1031 returned. When possible 32-bit PCI configuration write cycles are used to
1032 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1033 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1034 and the end of the range.
1036 If StartAddress > 0x0FFFFFFF, then ASSERT().
1037 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1038 If Size > 0 and Buffer is NULL, then ASSERT().
1040 @param StartAddress Starting address that encodes the PCI Bus, Device,
1041 Function and Register.
1042 @param Size Size in bytes of the transfer.
1043 @param Buffer Pointer to a buffer containing the data to write.
1045 @return Size written to StartAddress.
1050 PciExpressWriteBuffer (
1051 IN UINTN StartAddress
,