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2 Pci Express Library Services for PCI Segment #0
4 Copyright (c) 2006 - 2008, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef __PCI_EXPRESS_LIB_H__
16 #define __PCI_EXPRESS_LIB_H__
18 #include <Library/PciLib.h>
21 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
22 address that can be passed to the PCI Library functions.
24 Computes an address that is compatible with the PCI Library functions. The
25 unused upper bits of Bus, Device, Function and Register are stripped prior to
26 the generation of the address.
28 @param Bus PCI Bus number. Range 0..255.
29 @param Device PCI Device number. Range 0..31.
30 @param Function PCI Function number. Range 0..7.
31 @param Register PCI Register number. Range 0..4095.
33 @return The encode PCI address.
36 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
37 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
40 Reads an 8-bit PCI configuration register.
42 Reads and returns the 8-bit PCI configuration register specified by Address.
43 This function must guarantee that all PCI read and write operations are
46 If Address > 0x0FFFFFFF, then ASSERT().
48 @param Address Address that encodes the PCI Bus, Device, Function and
51 @return The read value from the PCI configuration register.
61 Writes an 8-bit PCI configuration register.
63 Writes the 8-bit PCI configuration register specified by Address with the
64 value specified by Value. Value is returned. This function must guarantee
65 that all PCI read and write operations are serialized.
67 If Address > 0x0FFFFFFF, then ASSERT().
69 @param Address Address that encodes the PCI Bus, Device, Function and
71 @param Value The value to write.
73 @return The value written to the PCI configuration register.
84 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
87 Reads the 8-bit PCI configuration register specified by Address, performs a
88 bitwise inclusive OR between the read result and the value specified by
89 OrData, and writes the result to the 8-bit PCI configuration register
90 specified by Address. The value written to the PCI configuration register is
91 returned. This function must guarantee that all PCI read and write operations
94 If Address > 0x0FFFFFFF, then ASSERT().
96 @param Address Address that encodes the PCI Bus, Device, Function and
98 @param OrData The value to OR with the PCI configuration register.
100 @return The value written back to the PCI configuration register.
111 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
114 Reads the 8-bit PCI configuration register specified by Address, performs a
115 bitwise AND between the read result and the value specified by AndData, and
116 writes the result to the 8-bit PCI configuration register specified by
117 Address. The value written to the PCI configuration register is returned.
118 This function must guarantee that all PCI read and write operations are
121 If Address > 0x0FFFFFFF, then ASSERT().
123 @param Address Address that encodes the PCI Bus, Device, Function and
125 @param AndData The value to AND with the PCI configuration register.
127 @return The value written back to the PCI configuration register.
138 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
139 value, followed a bitwise inclusive OR with another 8-bit value.
141 Reads the 8-bit PCI configuration register specified by Address, performs a
142 bitwise AND between the read result and the value specified by AndData,
143 performs a bitwise inclusive OR between the result of the AND operation and
144 the value specified by OrData, and writes the result to the 8-bit PCI
145 configuration register specified by Address. The value written to the PCI
146 configuration register is returned. This function must guarantee that all PCI
147 read and write operations are serialized.
149 If Address > 0x0FFFFFFF, then ASSERT().
151 @param Address Address that encodes the PCI Bus, Device, Function and
153 @param AndData The value to AND with the PCI configuration register.
154 @param OrData The value to OR with the result of the AND operation.
156 @return The value written back to the PCI configuration register.
161 PciExpressAndThenOr8 (
168 Reads a bit field of a PCI configuration register.
170 Reads the bit field in an 8-bit PCI configuration register. The bit field is
171 specified by the StartBit and the EndBit. The value of the bit field is
174 If Address > 0x0FFFFFFF, then ASSERT().
175 If StartBit is greater than 7, then ASSERT().
176 If EndBit is greater than 7, then ASSERT().
177 If EndBit is less than StartBit, then ASSERT().
179 @param Address PCI configuration register to read.
180 @param StartBit The ordinal of the least significant bit in the bit field.
182 @param EndBit The ordinal of the most significant bit in the bit field.
185 @return The value of the bit field read from the PCI configuration register.
190 PciExpressBitFieldRead8 (
197 Writes a bit field to a PCI configuration register.
199 Writes Value to the bit field of the PCI configuration register. The bit
200 field is specified by the StartBit and the EndBit. All other bits in the
201 destination PCI configuration register are preserved. The new value of the
202 8-bit register is returned.
204 If Address > 0x0FFFFFFF, then ASSERT().
205 If StartBit is greater than 7, then ASSERT().
206 If EndBit is greater than 7, then ASSERT().
207 If EndBit is less than StartBit, then ASSERT().
209 @param Address PCI configuration register to write.
210 @param StartBit The ordinal of the least significant bit in the bit field.
212 @param EndBit The ordinal of the most significant bit in the bit field.
214 @param Value New value of the bit field.
216 @return The value written back to the PCI configuration register.
221 PciExpressBitFieldWrite8 (
229 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
230 writes the result back to the bit field in the 8-bit port.
232 Reads the 8-bit PCI configuration register specified by Address, performs a
233 bitwise inclusive OR between the read result and the value specified by
234 OrData, and writes the result to the 8-bit PCI configuration register
235 specified by Address. The value written to the PCI configuration register is
236 returned. This function must guarantee that all PCI read and write operations
237 are serialized. Extra left bits in OrData are stripped.
239 If Address > 0x0FFFFFFF, then ASSERT().
240 If StartBit is greater than 7, then ASSERT().
241 If EndBit is greater than 7, then ASSERT().
242 If EndBit is less than StartBit, then ASSERT().
244 @param Address PCI configuration register to write.
245 @param StartBit The ordinal of the least significant bit in the bit field.
247 @param EndBit The ordinal of the most significant bit in the bit field.
249 @param OrData The value to OR with the PCI configuration register.
251 @return The value written back to the PCI configuration register.
256 PciExpressBitFieldOr8 (
264 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
265 AND, and writes the result back to the bit field in the 8-bit register.
267 Reads the 8-bit PCI configuration register specified by Address, performs a
268 bitwise AND between the read result and the value specified by AndData, and
269 writes the result to the 8-bit PCI configuration register specified by
270 Address. The value written to the PCI configuration register is returned.
271 This function must guarantee that all PCI read and write operations are
272 serialized. Extra left bits in AndData are stripped.
274 If Address > 0x0FFFFFFF, then ASSERT().
275 If StartBit is greater than 7, then ASSERT().
276 If EndBit is greater than 7, then ASSERT().
277 If EndBit is less than StartBit, then ASSERT().
279 @param Address PCI configuration register to write.
280 @param StartBit The ordinal of the least significant bit in the bit field.
282 @param EndBit The ordinal of the most significant bit in the bit field.
284 @param AndData The value to AND with the PCI configuration register.
286 @return The value written back to the PCI configuration register.
291 PciExpressBitFieldAnd8 (
299 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
300 bitwise inclusive OR, and writes the result back to the bit field in the
303 Reads the 8-bit PCI configuration register specified by Address, performs a
304 bitwise AND followed by a bitwise inclusive OR between the read result and
305 the value specified by AndData, and writes the result to the 8-bit PCI
306 configuration register specified by Address. The value written to the PCI
307 configuration register is returned. This function must guarantee that all PCI
308 read and write operations are serialized. Extra left bits in both AndData and
311 If Address > 0x0FFFFFFF, then ASSERT().
312 If StartBit is greater than 7, then ASSERT().
313 If EndBit is greater than 7, then ASSERT().
314 If EndBit is less than StartBit, then ASSERT().
316 @param Address PCI configuration register to write.
317 @param StartBit The ordinal of the least significant bit in the bit field.
319 @param EndBit The ordinal of the most significant bit in the bit field.
321 @param AndData The value to AND with the PCI configuration register.
322 @param OrData The value to OR with the result of the AND operation.
324 @return The value written back to the PCI configuration register.
329 PciExpressBitFieldAndThenOr8 (
338 Reads a 16-bit PCI configuration register.
340 Reads and returns the 16-bit PCI configuration register specified by Address.
341 This function must guarantee that all PCI read and write operations are
344 If Address > 0x0FFFFFFF, then ASSERT().
345 If Address is not aligned on a 16-bit boundary, then ASSERT().
347 @param Address Address that encodes the PCI Bus, Device, Function and
350 @return The read value from the PCI configuration register.
360 Writes a 16-bit PCI configuration register.
362 Writes the 16-bit PCI configuration register specified by Address with the
363 value specified by Value. Value is returned. This function must guarantee
364 that all PCI read and write operations are serialized.
366 If Address > 0x0FFFFFFF, then ASSERT().
367 If Address is not aligned on a 16-bit boundary, then ASSERT().
369 @param Address Address that encodes the PCI Bus, Device, Function and
371 @param Value The value to write.
373 @return The value written to the PCI configuration register.
384 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
387 Reads the 16-bit PCI configuration register specified by Address, performs a
388 bitwise inclusive OR between the read result and the value specified by
389 OrData, and writes the result to the 16-bit PCI configuration register
390 specified by Address. The value written to the PCI configuration register is
391 returned. This function must guarantee that all PCI read and write operations
394 If Address > 0x0FFFFFFF, then ASSERT().
395 If Address is not aligned on a 16-bit boundary, then ASSERT().
397 @param Address Address that encodes the PCI Bus, Device, Function and
399 @param OrData The value to OR with the PCI configuration register.
401 @return The value written back to the PCI configuration register.
412 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
415 Reads the 16-bit PCI configuration register specified by Address, performs a
416 bitwise AND between the read result and the value specified by AndData, and
417 writes the result to the 16-bit PCI configuration register specified by
418 Address. The value written to the PCI configuration register is returned.
419 This function must guarantee that all PCI read and write operations are
422 If Address > 0x0FFFFFFF, then ASSERT().
423 If Address is not aligned on a 16-bit boundary, then ASSERT().
425 @param Address Address that encodes the PCI Bus, Device, Function and
427 @param AndData The value to AND with the PCI configuration register.
429 @return The value written back to the PCI configuration register.
440 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
441 value, followed a bitwise inclusive OR with another 16-bit value.
443 Reads the 16-bit PCI configuration register specified by Address, performs a
444 bitwise AND between the read result and the value specified by AndData,
445 performs a bitwise inclusive OR between the result of the AND operation and
446 the value specified by OrData, and writes the result to the 16-bit PCI
447 configuration register specified by Address. The value written to the PCI
448 configuration register is returned. This function must guarantee that all PCI
449 read and write operations are serialized.
451 If Address > 0x0FFFFFFF, then ASSERT().
452 If Address is not aligned on a 16-bit boundary, then ASSERT().
454 @param Address Address that encodes the PCI Bus, Device, Function and
456 @param AndData The value to AND with the PCI configuration register.
457 @param OrData The value to OR with the result of the AND operation.
459 @return The value written back to the PCI configuration register.
464 PciExpressAndThenOr16 (
471 Reads a bit field of a PCI configuration register.
473 Reads the bit field in a 16-bit PCI configuration register. The bit field is
474 specified by the StartBit and the EndBit. The value of the bit field is
477 If Address > 0x0FFFFFFF, then ASSERT().
478 If Address is not aligned on a 16-bit boundary, then ASSERT().
479 If StartBit is greater than 15, then ASSERT().
480 If EndBit is greater than 15, then ASSERT().
481 If EndBit is less than StartBit, then ASSERT().
483 @param Address PCI configuration register to read.
484 @param StartBit The ordinal of the least significant bit in the bit field.
486 @param EndBit The ordinal of the most significant bit in the bit field.
489 @return The value of the bit field read from the PCI configuration register.
494 PciExpressBitFieldRead16 (
501 Writes a bit field to a PCI configuration register.
503 Writes Value to the bit field of the PCI configuration register. The bit
504 field is specified by the StartBit and the EndBit. All other bits in the
505 destination PCI configuration register are preserved. The new value of the
506 16-bit register is returned.
508 If Address > 0x0FFFFFFF, then ASSERT().
509 If Address is not aligned on a 16-bit boundary, then ASSERT().
510 If StartBit is greater than 15, then ASSERT().
511 If EndBit is greater than 15, then ASSERT().
512 If EndBit is less than StartBit, then ASSERT().
514 @param Address PCI configuration register to write.
515 @param StartBit The ordinal of the least significant bit in the bit field.
517 @param EndBit The ordinal of the most significant bit in the bit field.
519 @param Value New value of the bit field.
521 @return The value written back to the PCI configuration register.
526 PciExpressBitFieldWrite16 (
534 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
535 writes the result back to the bit field in the 16-bit port.
537 Reads the 16-bit PCI configuration register specified by Address, performs a
538 bitwise inclusive OR between the read result and the value specified by
539 OrData, and writes the result to the 16-bit PCI configuration register
540 specified by Address. The value written to the PCI configuration register is
541 returned. This function must guarantee that all PCI read and write operations
542 are serialized. Extra left bits in OrData are stripped.
544 If Address > 0x0FFFFFFF, then ASSERT().
545 If Address is not aligned on a 16-bit boundary, then ASSERT().
546 If StartBit is greater than 15, then ASSERT().
547 If EndBit is greater than 15, then ASSERT().
548 If EndBit is less than StartBit, then ASSERT().
550 @param Address PCI configuration register to write.
551 @param StartBit The ordinal of the least significant bit in the bit field.
553 @param EndBit The ordinal of the most significant bit in the bit field.
555 @param OrData The value to OR with the PCI configuration register.
557 @return The value written back to the PCI configuration register.
562 PciExpressBitFieldOr16 (
570 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
571 AND, and writes the result back to the bit field in the 16-bit register.
573 Reads the 16-bit PCI configuration register specified by Address, performs a
574 bitwise AND between the read result and the value specified by AndData, and
575 writes the result to the 16-bit PCI configuration register specified by
576 Address. The value written to the PCI configuration register is returned.
577 This function must guarantee that all PCI read and write operations are
578 serialized. Extra left bits in AndData are stripped.
580 If Address > 0x0FFFFFFF, then ASSERT().
581 If Address is not aligned on a 16-bit boundary, then ASSERT().
582 If StartBit is greater than 15, then ASSERT().
583 If EndBit is greater than 15, then ASSERT().
584 If EndBit is less than StartBit, then ASSERT().
586 @param Address PCI configuration register to write.
587 @param StartBit The ordinal of the least significant bit in the bit field.
589 @param EndBit The ordinal of the most significant bit in the bit field.
591 @param AndData The value to AND with the PCI configuration register.
593 @return The value written back to the PCI configuration register.
598 PciExpressBitFieldAnd16 (
606 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
607 bitwise inclusive OR, and writes the result back to the bit field in the
610 Reads the 16-bit PCI configuration register specified by Address, performs a
611 bitwise AND followed by a bitwise inclusive OR between the read result and
612 the value specified by AndData, and writes the result to the 16-bit PCI
613 configuration register specified by Address. The value written to the PCI
614 configuration register is returned. This function must guarantee that all PCI
615 read and write operations are serialized. Extra left bits in both AndData and
618 If Address > 0x0FFFFFFF, then ASSERT().
619 If Address is not aligned on a 16-bit boundary, then ASSERT().
620 If StartBit is greater than 15, then ASSERT().
621 If EndBit is greater than 15, then ASSERT().
622 If EndBit is less than StartBit, then ASSERT().
624 @param Address PCI configuration register to write.
625 @param StartBit The ordinal of the least significant bit in the bit field.
627 @param EndBit The ordinal of the most significant bit in the bit field.
629 @param AndData The value to AND with the PCI configuration register.
630 @param OrData The value to OR with the result of the AND operation.
632 @return The value written back to the PCI configuration register.
637 PciExpressBitFieldAndThenOr16 (
646 Reads a 32-bit PCI configuration register.
648 Reads and returns the 32-bit PCI configuration register specified by Address.
649 This function must guarantee that all PCI read and write operations are
652 If Address > 0x0FFFFFFF, then ASSERT().
653 If Address is not aligned on a 32-bit boundary, then ASSERT().
655 @param Address Address that encodes the PCI Bus, Device, Function and
658 @return The read value from the PCI configuration register.
668 Writes a 32-bit PCI configuration register.
670 Writes the 32-bit PCI configuration register specified by Address with the
671 value specified by Value. Value is returned. This function must guarantee
672 that all PCI read and write operations are serialized.
674 If Address > 0x0FFFFFFF, then ASSERT().
675 If Address is not aligned on a 32-bit boundary, then ASSERT().
677 @param Address Address that encodes the PCI Bus, Device, Function and
679 @param Value The value to write.
681 @return The value written to the PCI configuration register.
692 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
695 Reads the 32-bit PCI configuration register specified by Address, performs a
696 bitwise inclusive OR between the read result and the value specified by
697 OrData, and writes the result to the 32-bit PCI configuration register
698 specified by Address. The value written to the PCI configuration register is
699 returned. This function must guarantee that all PCI read and write operations
702 If Address > 0x0FFFFFFF, then ASSERT().
703 If Address is not aligned on a 32-bit boundary, then ASSERT().
705 @param Address Address that encodes the PCI Bus, Device, Function and
707 @param OrData The value to OR with the PCI configuration register.
709 @return The value written back to the PCI configuration register.
720 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
723 Reads the 32-bit PCI configuration register specified by Address, performs a
724 bitwise AND between the read result and the value specified by AndData, and
725 writes the result to the 32-bit PCI configuration register specified by
726 Address. The value written to the PCI configuration register is returned.
727 This function must guarantee that all PCI read and write operations are
730 If Address > 0x0FFFFFFF, then ASSERT().
731 If Address is not aligned on a 32-bit boundary, then ASSERT().
733 @param Address Address that encodes the PCI Bus, Device, Function and
735 @param AndData The value to AND with the PCI configuration register.
737 @return The value written back to the PCI configuration register.
748 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
749 value, followed a bitwise inclusive OR with another 32-bit value.
751 Reads the 32-bit PCI configuration register specified by Address, performs a
752 bitwise AND between the read result and the value specified by AndData,
753 performs a bitwise inclusive OR between the result of the AND operation and
754 the value specified by OrData, and writes the result to the 32-bit PCI
755 configuration register specified by Address. The value written to the PCI
756 configuration register is returned. This function must guarantee that all PCI
757 read and write operations are serialized.
759 If Address > 0x0FFFFFFF, then ASSERT().
760 If Address is not aligned on a 32-bit boundary, then ASSERT().
762 @param Address Address that encodes the PCI Bus, Device, Function and
764 @param AndData The value to AND with the PCI configuration register.
765 @param OrData The value to OR with the result of the AND operation.
767 @return The value written back to the PCI configuration register.
772 PciExpressAndThenOr32 (
779 Reads a bit field of a PCI configuration register.
781 Reads the bit field in a 32-bit PCI configuration register. The bit field is
782 specified by the StartBit and the EndBit. The value of the bit field is
785 If Address > 0x0FFFFFFF, then ASSERT().
786 If Address is not aligned on a 32-bit boundary, then ASSERT().
787 If StartBit is greater than 31, then ASSERT().
788 If EndBit is greater than 31, then ASSERT().
789 If EndBit is less than StartBit, then ASSERT().
791 @param Address PCI configuration register to read.
792 @param StartBit The ordinal of the least significant bit in the bit field.
794 @param EndBit The ordinal of the most significant bit in the bit field.
797 @return The value of the bit field read from the PCI configuration register.
802 PciExpressBitFieldRead32 (
809 Writes a bit field to a PCI configuration register.
811 Writes Value to the bit field of the PCI configuration register. The bit
812 field is specified by the StartBit and the EndBit. All other bits in the
813 destination PCI configuration register are preserved. The new value of the
814 32-bit register is returned.
816 If Address > 0x0FFFFFFF, then ASSERT().
817 If Address is not aligned on a 32-bit boundary, then ASSERT().
818 If StartBit is greater than 31, then ASSERT().
819 If EndBit is greater than 31, then ASSERT().
820 If EndBit is less than StartBit, then ASSERT().
822 @param Address PCI configuration register to write.
823 @param StartBit The ordinal of the least significant bit in the bit field.
825 @param EndBit The ordinal of the most significant bit in the bit field.
827 @param Value New value of the bit field.
829 @return The value written back to the PCI configuration register.
834 PciExpressBitFieldWrite32 (
842 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
843 writes the result back to the bit field in the 32-bit port.
845 Reads the 32-bit PCI configuration register specified by Address, performs a
846 bitwise inclusive OR between the read result and the value specified by
847 OrData, and writes the result to the 32-bit PCI configuration register
848 specified by Address. The value written to the PCI configuration register is
849 returned. This function must guarantee that all PCI read and write operations
850 are serialized. Extra left bits in OrData are stripped.
852 If Address > 0x0FFFFFFF, then ASSERT().
853 If Address is not aligned on a 32-bit boundary, then ASSERT().
854 If StartBit is greater than 31, then ASSERT().
855 If EndBit is greater than 31, then ASSERT().
856 If EndBit is less than StartBit, then ASSERT().
858 @param Address PCI configuration register to write.
859 @param StartBit The ordinal of the least significant bit in the bit field.
861 @param EndBit The ordinal of the most significant bit in the bit field.
863 @param OrData The value to OR with the PCI configuration register.
865 @return The value written back to the PCI configuration register.
870 PciExpressBitFieldOr32 (
878 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
879 AND, and writes the result back to the bit field in the 32-bit register.
881 Reads the 32-bit PCI configuration register specified by Address, performs a
882 bitwise AND between the read result and the value specified by AndData, and
883 writes the result to the 32-bit PCI configuration register specified by
884 Address. The value written to the PCI configuration register is returned.
885 This function must guarantee that all PCI read and write operations are
886 serialized. Extra left bits in AndData are stripped.
888 If Address > 0x0FFFFFFF, then ASSERT().
889 If Address is not aligned on a 32-bit boundary, then ASSERT().
890 If StartBit is greater than 31, then ASSERT().
891 If EndBit is greater than 31, then ASSERT().
892 If EndBit is less than StartBit, then ASSERT().
894 @param Address PCI configuration register to write.
895 @param StartBit The ordinal of the least significant bit in the bit field.
897 @param EndBit The ordinal of the most significant bit in the bit field.
899 @param AndData The value to AND with the PCI configuration register.
901 @return The value written back to the PCI configuration register.
906 PciExpressBitFieldAnd32 (
914 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
915 bitwise inclusive OR, and writes the result back to the bit field in the
918 Reads the 32-bit PCI configuration register specified by Address, performs a
919 bitwise AND followed by a bitwise inclusive OR between the read result and
920 the value specified by AndData, and writes the result to the 32-bit PCI
921 configuration register specified by Address. The value written to the PCI
922 configuration register is returned. This function must guarantee that all PCI
923 read and write operations are serialized. Extra left bits in both AndData and
926 If Address > 0x0FFFFFFF, then ASSERT().
927 If Address is not aligned on a 32-bit boundary, then ASSERT().
928 If StartBit is greater than 31, then ASSERT().
929 If EndBit is greater than 31, then ASSERT().
930 If EndBit is less than StartBit, then ASSERT().
932 @param Address PCI configuration register to write.
933 @param StartBit The ordinal of the least significant bit in the bit field.
935 @param EndBit The ordinal of the most significant bit in the bit field.
937 @param AndData The value to AND with the PCI configuration register.
938 @param OrData The value to OR with the result of the AND operation.
940 @return The value written back to the PCI configuration register.
945 PciExpressBitFieldAndThenOr32 (
954 Reads a range of PCI configuration registers into a caller supplied buffer.
956 Reads the range of PCI configuration registers specified by StartAddress and
957 Size into the buffer specified by Buffer. This function only allows the PCI
958 configuration registers from a single PCI function to be read. Size is
959 returned. When possible 32-bit PCI configuration read cycles are used to read
960 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
961 and 16-bit PCI configuration read cycles may be used at the beginning and the
964 If StartAddress > 0x0FFFFFFF, then ASSERT().
965 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
966 If Size > 0 and Buffer is NULL, then ASSERT().
968 @param StartAddress Starting address that encodes the PCI Bus, Device,
969 Function and Register.
970 @param Size Size in bytes of the transfer.
971 @param Buffer Pointer to a buffer receiving the data read.
978 PciExpressReadBuffer (
979 IN UINTN StartAddress
,
985 Copies the data in a caller supplied buffer to a specified range of PCI
988 Writes the range of PCI configuration registers specified by StartAddress and
989 Size from the buffer specified by Buffer. This function only allows the PCI
990 configuration registers from a single PCI function to be written. Size is
991 returned. When possible 32-bit PCI configuration write cycles are used to
992 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
993 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
994 and the end of the range.
996 If StartAddress > 0x0FFFFFFF, then ASSERT().
997 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
998 If Size > 0 and Buffer is NULL, then ASSERT().
1000 @param StartAddress Starting address that encodes the PCI Bus, Device,
1001 Function and Register.
1002 @param Size Size in bytes of the transfer.
1003 @param Buffer Pointer to a buffer containing the data to write.
1010 PciExpressWriteBuffer (
1011 IN UINTN StartAddress
,