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2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
6 is defined by PcdPciExpressBaseAddress.
8 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __PCI_EXPRESS_LIB_H__
20 #define __PCI_EXPRESS_LIB_H__
23 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
24 address that can be passed to the PCI Library functions.
26 Computes an address that is compatible with the PCI Library functions. The
27 unused upper bits of Bus, Device, Function and Register are stripped prior to
28 the generation of the address.
30 @param Bus PCI Bus number. Range 0..255.
31 @param Device PCI Device number. Range 0..31.
32 @param Function PCI Function number. Range 0..7.
33 @param Register PCI Register number. Range 0..4095.
35 @return The encode PCI address.
38 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
39 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
42 Registers a PCI device so PCI configuration registers may be accessed after
43 SetVirtualAddressMap().
45 Registers the PCI device specified by Address so all the PCI configuration
46 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
49 If Address > 0x0FFFFFFF, then ASSERT().
51 @param Address Address that encodes the PCI Bus, Device, Function and
54 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
55 @retval RETURN_UNSUPPORTED An attempt was made to call this function
56 after ExitBootServices().
57 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
58 at runtime could not be mapped.
59 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
60 complete the registration.
65 PciExpressRegisterForRuntimeAccess (
70 Reads an 8-bit PCI configuration register.
72 Reads and returns the 8-bit PCI configuration register specified by Address.
73 This function must guarantee that all PCI read and write operations are
76 If Address > 0x0FFFFFFF, then ASSERT().
78 @param Address Address that encodes the PCI Bus, Device, Function and
81 @return The read value from the PCI configuration register.
91 Writes an 8-bit PCI configuration register.
93 Writes the 8-bit PCI configuration register specified by Address with the
94 value specified by Value. Value is returned. This function must guarantee
95 that all PCI read and write operations are serialized.
97 If Address > 0x0FFFFFFF, then ASSERT().
99 @param Address Address that encodes the PCI Bus, Device, Function and
101 @param Value The value to write.
103 @return The value written to the PCI configuration register.
114 Performs a bitwise OR of an 8-bit PCI configuration register with
117 Reads the 8-bit PCI configuration register specified by Address, performs a
118 bitwise OR between the read result and the value specified by
119 OrData, and writes the result to the 8-bit PCI configuration register
120 specified by Address. The value written to the PCI configuration register is
121 returned. This function must guarantee that all PCI read and write operations
124 If Address > 0x0FFFFFFF, then ASSERT().
126 @param Address Address that encodes the PCI Bus, Device, Function and
128 @param OrData The value to OR with the PCI configuration register.
130 @return The value written back to the PCI configuration register.
141 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
144 Reads the 8-bit PCI configuration register specified by Address, performs a
145 bitwise AND between the read result and the value specified by AndData, and
146 writes the result to the 8-bit PCI configuration register specified by
147 Address. The value written to the PCI configuration register is returned.
148 This function must guarantee that all PCI read and write operations are
151 If Address > 0x0FFFFFFF, then ASSERT().
153 @param Address Address that encodes the PCI Bus, Device, Function and
155 @param AndData The value to AND with the PCI configuration register.
157 @return The value written back to the PCI configuration register.
168 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
169 value, followed a bitwise OR with another 8-bit value.
171 Reads the 8-bit PCI configuration register specified by Address, performs a
172 bitwise AND between the read result and the value specified by AndData,
173 performs a bitwise OR between the result of the AND operation and
174 the value specified by OrData, and writes the result to the 8-bit PCI
175 configuration register specified by Address. The value written to the PCI
176 configuration register is returned. This function must guarantee that all PCI
177 read and write operations are serialized.
179 If Address > 0x0FFFFFFF, then ASSERT().
181 @param Address Address that encodes the PCI Bus, Device, Function and
183 @param AndData The value to AND with the PCI configuration register.
184 @param OrData The value to OR with the result of the AND operation.
186 @return The value written back to the PCI configuration register.
191 PciExpressAndThenOr8 (
198 Reads a bit field of a PCI configuration register.
200 Reads the bit field in an 8-bit PCI configuration register. The bit field is
201 specified by the StartBit and the EndBit. The value of the bit field is
204 If Address > 0x0FFFFFFF, then ASSERT().
205 If StartBit is greater than 7, then ASSERT().
206 If EndBit is greater than 7, then ASSERT().
207 If EndBit is less than StartBit, then ASSERT().
209 @param Address PCI configuration register to read.
210 @param StartBit The ordinal of the least significant bit in the bit field.
212 @param EndBit The ordinal of the most significant bit in the bit field.
215 @return The value of the bit field read from the PCI configuration register.
220 PciExpressBitFieldRead8 (
227 Writes a bit field to a PCI configuration register.
229 Writes Value to the bit field of the PCI configuration register. The bit
230 field is specified by the StartBit and the EndBit. All other bits in the
231 destination PCI configuration register are preserved. The new value of the
232 8-bit register is returned.
234 If Address > 0x0FFFFFFF, then ASSERT().
235 If StartBit is greater than 7, then ASSERT().
236 If EndBit is greater than 7, then ASSERT().
237 If EndBit is less than StartBit, then ASSERT().
238 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
240 @param Address PCI configuration register to write.
241 @param StartBit The ordinal of the least significant bit in the bit field.
243 @param EndBit The ordinal of the most significant bit in the bit field.
245 @param Value New value of the bit field.
247 @return The value written back to the PCI configuration register.
252 PciExpressBitFieldWrite8 (
260 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
261 writes the result back to the bit field in the 8-bit port.
263 Reads the 8-bit PCI configuration register specified by Address, performs a
264 bitwise OR between the read result and the value specified by
265 OrData, and writes the result to the 8-bit PCI configuration register
266 specified by Address. The value written to the PCI configuration register is
267 returned. This function must guarantee that all PCI read and write operations
268 are serialized. Extra left bits in OrData are stripped.
270 If Address > 0x0FFFFFFF, then ASSERT().
271 If StartBit is greater than 7, then ASSERT().
272 If EndBit is greater than 7, then ASSERT().
273 If EndBit is less than StartBit, then ASSERT().
274 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
276 @param Address PCI configuration register to write.
277 @param StartBit The ordinal of the least significant bit in the bit field.
279 @param EndBit The ordinal of the most significant bit in the bit field.
281 @param OrData The value to OR with the PCI configuration register.
283 @return The value written back to the PCI configuration register.
288 PciExpressBitFieldOr8 (
296 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
297 AND, and writes the result back to the bit field in the 8-bit register.
299 Reads the 8-bit PCI configuration register specified by Address, performs a
300 bitwise AND between the read result and the value specified by AndData, and
301 writes the result to the 8-bit PCI configuration register specified by
302 Address. The value written to the PCI configuration register is returned.
303 This function must guarantee that all PCI read and write operations are
304 serialized. Extra left bits in AndData are stripped.
306 If Address > 0x0FFFFFFF, then ASSERT().
307 If StartBit is greater than 7, then ASSERT().
308 If EndBit is greater than 7, then ASSERT().
309 If EndBit is less than StartBit, then ASSERT().
310 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
312 @param Address PCI configuration register to write.
313 @param StartBit The ordinal of the least significant bit in the bit field.
315 @param EndBit The ordinal of the most significant bit in the bit field.
317 @param AndData The value to AND with the PCI configuration register.
319 @return The value written back to the PCI configuration register.
324 PciExpressBitFieldAnd8 (
332 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
333 bitwise OR, and writes the result back to the bit field in the
336 Reads the 8-bit PCI configuration register specified by Address, performs a
337 bitwise AND followed by a bitwise OR between the read result and
338 the value specified by AndData, and writes the result to the 8-bit PCI
339 configuration register specified by Address. The value written to the PCI
340 configuration register is returned. This function must guarantee that all PCI
341 read and write operations are serialized. Extra left bits in both AndData and
344 If Address > 0x0FFFFFFF, then ASSERT().
345 If StartBit is greater than 7, then ASSERT().
346 If EndBit is greater than 7, then ASSERT().
347 If EndBit is less than StartBit, then ASSERT().
348 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
349 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
351 @param Address PCI configuration register to write.
352 @param StartBit The ordinal of the least significant bit in the bit field.
354 @param EndBit The ordinal of the most significant bit in the bit field.
356 @param AndData The value to AND with the PCI configuration register.
357 @param OrData The value to OR with the result of the AND operation.
359 @return The value written back to the PCI configuration register.
364 PciExpressBitFieldAndThenOr8 (
373 Reads a 16-bit PCI configuration register.
375 Reads and returns the 16-bit PCI configuration register specified by Address.
376 This function must guarantee that all PCI read and write operations are
379 If Address > 0x0FFFFFFF, then ASSERT().
380 If Address is not aligned on a 16-bit boundary, then ASSERT().
382 @param Address Address that encodes the PCI Bus, Device, Function and
385 @return The read value from the PCI configuration register.
395 Writes a 16-bit PCI configuration register.
397 Writes the 16-bit PCI configuration register specified by Address with the
398 value specified by Value. Value is returned. This function must guarantee
399 that all PCI read and write operations are serialized.
401 If Address > 0x0FFFFFFF, then ASSERT().
402 If Address is not aligned on a 16-bit boundary, then ASSERT().
404 @param Address Address that encodes the PCI Bus, Device, Function and
406 @param Value The value to write.
408 @return The value written to the PCI configuration register.
419 Performs a bitwise OR of a 16-bit PCI configuration register with
422 Reads the 16-bit PCI configuration register specified by Address, performs a
423 bitwise OR between the read result and the value specified by
424 OrData, and writes the result to the 16-bit PCI configuration register
425 specified by Address. The value written to the PCI configuration register is
426 returned. This function must guarantee that all PCI read and write operations
429 If Address > 0x0FFFFFFF, then ASSERT().
430 If Address is not aligned on a 16-bit boundary, then ASSERT().
432 @param Address Address that encodes the PCI Bus, Device, Function and
434 @param OrData The value to OR with the PCI configuration register.
436 @return The value written back to the PCI configuration register.
447 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
450 Reads the 16-bit PCI configuration register specified by Address, performs a
451 bitwise AND between the read result and the value specified by AndData, and
452 writes the result to the 16-bit PCI configuration register specified by
453 Address. The value written to the PCI configuration register is returned.
454 This function must guarantee that all PCI read and write operations are
457 If Address > 0x0FFFFFFF, then ASSERT().
458 If Address is not aligned on a 16-bit boundary, then ASSERT().
460 @param Address Address that encodes the PCI Bus, Device, Function and
462 @param AndData The value to AND with the PCI configuration register.
464 @return The value written back to the PCI configuration register.
475 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
476 value, followed a bitwise OR with another 16-bit value.
478 Reads the 16-bit PCI configuration register specified by Address, performs a
479 bitwise AND between the read result and the value specified by AndData,
480 performs a bitwise OR between the result of the AND operation and
481 the value specified by OrData, and writes the result to the 16-bit PCI
482 configuration register specified by Address. The value written to the PCI
483 configuration register is returned. This function must guarantee that all PCI
484 read and write operations are serialized.
486 If Address > 0x0FFFFFFF, then ASSERT().
487 If Address is not aligned on a 16-bit boundary, then ASSERT().
489 @param Address Address that encodes the PCI Bus, Device, Function and
491 @param AndData The value to AND with the PCI configuration register.
492 @param OrData The value to OR with the result of the AND operation.
494 @return The value written back to the PCI configuration register.
499 PciExpressAndThenOr16 (
506 Reads a bit field of a PCI configuration register.
508 Reads the bit field in a 16-bit PCI configuration register. The bit field is
509 specified by the StartBit and the EndBit. The value of the bit field is
512 If Address > 0x0FFFFFFF, then ASSERT().
513 If Address is not aligned on a 16-bit boundary, then ASSERT().
514 If StartBit is greater than 15, then ASSERT().
515 If EndBit is greater than 15, then ASSERT().
516 If EndBit is less than StartBit, then ASSERT().
518 @param Address PCI configuration register to read.
519 @param StartBit The ordinal of the least significant bit in the bit field.
521 @param EndBit The ordinal of the most significant bit in the bit field.
524 @return The value of the bit field read from the PCI configuration register.
529 PciExpressBitFieldRead16 (
536 Writes a bit field to a PCI configuration register.
538 Writes Value to the bit field of the PCI configuration register. The bit
539 field is specified by the StartBit and the EndBit. All other bits in the
540 destination PCI configuration register are preserved. The new value of the
541 16-bit register is returned.
543 If Address > 0x0FFFFFFF, then ASSERT().
544 If Address is not aligned on a 16-bit boundary, then ASSERT().
545 If StartBit is greater than 15, then ASSERT().
546 If EndBit is greater than 15, then ASSERT().
547 If EndBit is less than StartBit, then ASSERT().
548 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
550 @param Address PCI configuration register to write.
551 @param StartBit The ordinal of the least significant bit in the bit field.
553 @param EndBit The ordinal of the most significant bit in the bit field.
555 @param Value New value of the bit field.
557 @return The value written back to the PCI configuration register.
562 PciExpressBitFieldWrite16 (
570 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
571 writes the result back to the bit field in the 16-bit port.
573 Reads the 16-bit PCI configuration register specified by Address, performs a
574 bitwise OR between the read result and the value specified by
575 OrData, and writes the result to the 16-bit PCI configuration register
576 specified by Address. The value written to the PCI configuration register is
577 returned. This function must guarantee that all PCI read and write operations
578 are serialized. Extra left bits in OrData are stripped.
580 If Address > 0x0FFFFFFF, then ASSERT().
581 If Address is not aligned on a 16-bit boundary, then ASSERT().
582 If StartBit is greater than 15, then ASSERT().
583 If EndBit is greater than 15, then ASSERT().
584 If EndBit is less than StartBit, then ASSERT().
585 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
587 @param Address PCI configuration register to write.
588 @param StartBit The ordinal of the least significant bit in the bit field.
590 @param EndBit The ordinal of the most significant bit in the bit field.
592 @param OrData The value to OR with the PCI configuration register.
594 @return The value written back to the PCI configuration register.
599 PciExpressBitFieldOr16 (
607 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
608 AND, and writes the result back to the bit field in the 16-bit register.
610 Reads the 16-bit PCI configuration register specified by Address, performs a
611 bitwise AND between the read result and the value specified by AndData, and
612 writes the result to the 16-bit PCI configuration register specified by
613 Address. The value written to the PCI configuration register is returned.
614 This function must guarantee that all PCI read and write operations are
615 serialized. Extra left bits in AndData are stripped.
617 If Address > 0x0FFFFFFF, then ASSERT().
618 If Address is not aligned on a 16-bit boundary, then ASSERT().
619 If StartBit is greater than 15, then ASSERT().
620 If EndBit is greater than 15, then ASSERT().
621 If EndBit is less than StartBit, then ASSERT().
622 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
624 @param Address PCI configuration register to write.
625 @param StartBit The ordinal of the least significant bit in the bit field.
627 @param EndBit The ordinal of the most significant bit in the bit field.
629 @param AndData The value to AND with the PCI configuration register.
631 @return The value written back to the PCI configuration register.
636 PciExpressBitFieldAnd16 (
644 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
645 bitwise OR, and writes the result back to the bit field in the
648 Reads the 16-bit PCI configuration register specified by Address, performs a
649 bitwise AND followed by a bitwise OR between the read result and
650 the value specified by AndData, and writes the result to the 16-bit PCI
651 configuration register specified by Address. The value written to the PCI
652 configuration register is returned. This function must guarantee that all PCI
653 read and write operations are serialized. Extra left bits in both AndData and
656 If Address > 0x0FFFFFFF, then ASSERT().
657 If Address is not aligned on a 16-bit boundary, then ASSERT().
658 If StartBit is greater than 15, then ASSERT().
659 If EndBit is greater than 15, then ASSERT().
660 If EndBit is less than StartBit, then ASSERT().
661 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
662 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
664 @param Address PCI configuration register to write.
665 @param StartBit The ordinal of the least significant bit in the bit field.
667 @param EndBit The ordinal of the most significant bit in the bit field.
669 @param AndData The value to AND with the PCI configuration register.
670 @param OrData The value to OR with the result of the AND operation.
672 @return The value written back to the PCI configuration register.
677 PciExpressBitFieldAndThenOr16 (
686 Reads a 32-bit PCI configuration register.
688 Reads and returns the 32-bit PCI configuration register specified by Address.
689 This function must guarantee that all PCI read and write operations are
692 If Address > 0x0FFFFFFF, then ASSERT().
693 If Address is not aligned on a 32-bit boundary, then ASSERT().
695 @param Address Address that encodes the PCI Bus, Device, Function and
698 @return The read value from the PCI configuration register.
708 Writes a 32-bit PCI configuration register.
710 Writes the 32-bit PCI configuration register specified by Address with the
711 value specified by Value. Value is returned. This function must guarantee
712 that all PCI read and write operations are serialized.
714 If Address > 0x0FFFFFFF, then ASSERT().
715 If Address is not aligned on a 32-bit boundary, then ASSERT().
717 @param Address Address that encodes the PCI Bus, Device, Function and
719 @param Value The value to write.
721 @return The value written to the PCI configuration register.
732 Performs a bitwise OR of a 32-bit PCI configuration register with
735 Reads the 32-bit PCI configuration register specified by Address, performs a
736 bitwise OR between the read result and the value specified by
737 OrData, and writes the result to the 32-bit PCI configuration register
738 specified by Address. The value written to the PCI configuration register is
739 returned. This function must guarantee that all PCI read and write operations
742 If Address > 0x0FFFFFFF, then ASSERT().
743 If Address is not aligned on a 32-bit boundary, then ASSERT().
745 @param Address Address that encodes the PCI Bus, Device, Function and
747 @param OrData The value to OR with the PCI configuration register.
749 @return The value written back to the PCI configuration register.
760 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
763 Reads the 32-bit PCI configuration register specified by Address, performs a
764 bitwise AND between the read result and the value specified by AndData, and
765 writes the result to the 32-bit PCI configuration register specified by
766 Address. The value written to the PCI configuration register is returned.
767 This function must guarantee that all PCI read and write operations are
770 If Address > 0x0FFFFFFF, then ASSERT().
771 If Address is not aligned on a 32-bit boundary, then ASSERT().
773 @param Address Address that encodes the PCI Bus, Device, Function and
775 @param AndData The value to AND with the PCI configuration register.
777 @return The value written back to the PCI configuration register.
788 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
789 value, followed a bitwise OR with another 32-bit value.
791 Reads the 32-bit PCI configuration register specified by Address, performs a
792 bitwise AND between the read result and the value specified by AndData,
793 performs a bitwise OR between the result of the AND operation and
794 the value specified by OrData, and writes the result to the 32-bit PCI
795 configuration register specified by Address. The value written to the PCI
796 configuration register is returned. This function must guarantee that all PCI
797 read and write operations are serialized.
799 If Address > 0x0FFFFFFF, then ASSERT().
800 If Address is not aligned on a 32-bit boundary, then ASSERT().
802 @param Address Address that encodes the PCI Bus, Device, Function and
804 @param AndData The value to AND with the PCI configuration register.
805 @param OrData The value to OR with the result of the AND operation.
807 @return The value written back to the PCI configuration register.
812 PciExpressAndThenOr32 (
819 Reads a bit field of a PCI configuration register.
821 Reads the bit field in a 32-bit PCI configuration register. The bit field is
822 specified by the StartBit and the EndBit. The value of the bit field is
825 If Address > 0x0FFFFFFF, then ASSERT().
826 If Address is not aligned on a 32-bit boundary, then ASSERT().
827 If StartBit is greater than 31, then ASSERT().
828 If EndBit is greater than 31, then ASSERT().
829 If EndBit is less than StartBit, then ASSERT().
831 @param Address PCI configuration register to read.
832 @param StartBit The ordinal of the least significant bit in the bit field.
834 @param EndBit The ordinal of the most significant bit in the bit field.
837 @return The value of the bit field read from the PCI configuration register.
842 PciExpressBitFieldRead32 (
849 Writes a bit field to a PCI configuration register.
851 Writes Value to the bit field of the PCI configuration register. The bit
852 field is specified by the StartBit and the EndBit. All other bits in the
853 destination PCI configuration register are preserved. The new value of the
854 32-bit register is returned.
856 If Address > 0x0FFFFFFF, then ASSERT().
857 If Address is not aligned on a 32-bit boundary, then ASSERT().
858 If StartBit is greater than 31, then ASSERT().
859 If EndBit is greater than 31, then ASSERT().
860 If EndBit is less than StartBit, then ASSERT().
861 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
863 @param Address PCI configuration register to write.
864 @param StartBit The ordinal of the least significant bit in the bit field.
866 @param EndBit The ordinal of the most significant bit in the bit field.
868 @param Value New value of the bit field.
870 @return The value written back to the PCI configuration register.
875 PciExpressBitFieldWrite32 (
883 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
884 writes the result back to the bit field in the 32-bit port.
886 Reads the 32-bit PCI configuration register specified by Address, performs a
887 bitwise OR between the read result and the value specified by
888 OrData, and writes the result to the 32-bit PCI configuration register
889 specified by Address. The value written to the PCI configuration register is
890 returned. This function must guarantee that all PCI read and write operations
891 are serialized. Extra left bits in OrData are stripped.
893 If Address > 0x0FFFFFFF, then ASSERT().
894 If Address is not aligned on a 32-bit boundary, then ASSERT().
895 If StartBit is greater than 31, then ASSERT().
896 If EndBit is greater than 31, then ASSERT().
897 If EndBit is less than StartBit, then ASSERT().
898 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
900 @param Address PCI configuration register to write.
901 @param StartBit The ordinal of the least significant bit in the bit field.
903 @param EndBit The ordinal of the most significant bit in the bit field.
905 @param OrData The value to OR with the PCI configuration register.
907 @return The value written back to the PCI configuration register.
912 PciExpressBitFieldOr32 (
920 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
921 AND, and writes the result back to the bit field in the 32-bit register.
923 Reads the 32-bit PCI configuration register specified by Address, performs a
924 bitwise AND between the read result and the value specified by AndData, and
925 writes the result to the 32-bit PCI configuration register specified by
926 Address. The value written to the PCI configuration register is returned.
927 This function must guarantee that all PCI read and write operations are
928 serialized. Extra left bits in AndData are stripped.
930 If Address > 0x0FFFFFFF, then ASSERT().
931 If Address is not aligned on a 32-bit boundary, then ASSERT().
932 If StartBit is greater than 31, then ASSERT().
933 If EndBit is greater than 31, then ASSERT().
934 If EndBit is less than StartBit, then ASSERT().
935 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
937 @param Address PCI configuration register to write.
938 @param StartBit The ordinal of the least significant bit in the bit field.
940 @param EndBit The ordinal of the most significant bit in the bit field.
942 @param AndData The value to AND with the PCI configuration register.
944 @return The value written back to the PCI configuration register.
949 PciExpressBitFieldAnd32 (
957 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
958 bitwise OR, and writes the result back to the bit field in the
961 Reads the 32-bit PCI configuration register specified by Address, performs a
962 bitwise AND followed by a bitwise OR between the read result and
963 the value specified by AndData, and writes the result to the 32-bit PCI
964 configuration register specified by Address. The value written to the PCI
965 configuration register is returned. This function must guarantee that all PCI
966 read and write operations are serialized. Extra left bits in both AndData and
969 If Address > 0x0FFFFFFF, then ASSERT().
970 If Address is not aligned on a 32-bit boundary, then ASSERT().
971 If StartBit is greater than 31, then ASSERT().
972 If EndBit is greater than 31, then ASSERT().
973 If EndBit is less than StartBit, then ASSERT().
974 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
975 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
977 @param Address PCI configuration register to write.
978 @param StartBit The ordinal of the least significant bit in the bit field.
980 @param EndBit The ordinal of the most significant bit in the bit field.
982 @param AndData The value to AND with the PCI configuration register.
983 @param OrData The value to OR with the result of the AND operation.
985 @return The value written back to the PCI configuration register.
990 PciExpressBitFieldAndThenOr32 (
999 Reads a range of PCI configuration registers into a caller supplied buffer.
1001 Reads the range of PCI configuration registers specified by StartAddress and
1002 Size into the buffer specified by Buffer. This function only allows the PCI
1003 configuration registers from a single PCI function to be read. Size is
1004 returned. When possible 32-bit PCI configuration read cycles are used to read
1005 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1006 and 16-bit PCI configuration read cycles may be used at the beginning and the
1009 If StartAddress > 0x0FFFFFFF, then ASSERT().
1010 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1011 If Size > 0 and Buffer is NULL, then ASSERT().
1013 @param StartAddress Starting address that encodes the PCI Bus, Device,
1014 Function and Register.
1015 @param Size Size in bytes of the transfer.
1016 @param Buffer Pointer to a buffer receiving the data read.
1018 @return Size read data from StartAddress.
1023 PciExpressReadBuffer (
1024 IN UINTN StartAddress
,
1030 Copies the data in a caller supplied buffer to a specified range of PCI
1031 configuration space.
1033 Writes the range of PCI configuration registers specified by StartAddress and
1034 Size from the buffer specified by Buffer. This function only allows the PCI
1035 configuration registers from a single PCI function to be written. Size is
1036 returned. When possible 32-bit PCI configuration write cycles are used to
1037 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1038 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1039 and the end of the range.
1041 If StartAddress > 0x0FFFFFFF, then ASSERT().
1042 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1043 If Size > 0 and Buffer is NULL, then ASSERT().
1045 @param StartAddress Starting address that encodes the PCI Bus, Device,
1046 Function and Register.
1047 @param Size Size in bytes of the transfer.
1048 @param Buffer Pointer to a buffer containing the data to write.
1050 @return Size written to StartAddress.
1055 PciExpressWriteBuffer (
1056 IN UINTN StartAddress
,