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2 Provides services to access PCI Configuration Space.
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
6 or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
8 accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
9 PCI Express Library may be used in conjunction with the PCI Library. The functionality of
10 these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use
11 explicit access methods.
13 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
14 This program and the accompanying materials
15 are licensed and made available under the terms and conditions of the BSD License
16 which accompanies this distribution. The full text of the license may be found at
17 http://opensource.org/licenses/bsd-license.php
19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
20 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
28 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
29 address that can be passed to the PCI Library functions.
31 @param Bus PCI Bus number. Range 0..255.
32 @param Device PCI Device number. Range 0..31.
33 @param Function PCI Function number. Range 0..7.
34 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
37 @return The encoded PCI address.
40 #define PCI_LIB_ADDRESS(Bus,Device,Function,Register) \
41 (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
44 Registers a PCI device so PCI configuration registers may be accessed after
45 SetVirtualAddressMap().
47 Registers the PCI device specified by Address so all the PCI configuration registers
48 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
50 If Address > 0x0FFFFFFF, then ASSERT().
52 @param Address Address that encodes the PCI Bus, Device, Function and
55 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
56 @retval RETURN_UNSUPPORTED An attempt was made to call this function
57 after ExitBootServices().
58 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
59 at runtime could not be mapped.
60 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
61 complete the registration.
66 PciRegisterForRuntimeAccess (
71 Reads an 8-bit PCI configuration register.
73 Reads and returns the 8-bit PCI configuration register specified by Address.
74 This function must guarantee that all PCI read and write operations are
77 If Address > 0x0FFFFFFF, then ASSERT().
79 @param Address Address that encodes the PCI Bus, Device, Function and
82 @return The read value from the PCI configuration register.
92 Writes an 8-bit PCI configuration register.
94 Writes the 8-bit PCI configuration register specified by Address with the
95 value specified by Value. Value is returned. This function must guarantee
96 that all PCI read and write operations are serialized.
98 If Address > 0x0FFFFFFF, then ASSERT().
100 @param Address Address that encodes the PCI Bus, Device, Function and
102 @param Value The value to write.
104 @return The value written to the PCI configuration register.
115 Performs a bitwise OR of an 8-bit PCI configuration register with
118 Reads the 8-bit PCI configuration register specified by Address, performs a
119 bitwise OR between the read result and the value specified by
120 OrData, and writes the result to the 8-bit PCI configuration register
121 specified by Address. The value written to the PCI configuration register is
122 returned. This function must guarantee that all PCI read and write operations
125 If Address > 0x0FFFFFFF, then ASSERT().
127 @param Address Address that encodes the PCI Bus, Device, Function and
129 @param OrData The value to OR with the PCI configuration register.
131 @return The value written back to the PCI configuration register.
142 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
145 Reads the 8-bit PCI configuration register specified by Address, performs a
146 bitwise AND between the read result and the value specified by AndData, and
147 writes the result to the 8-bit PCI configuration register specified by
148 Address. The value written to the PCI configuration register is returned.
149 This function must guarantee that all PCI read and write operations are
152 If Address > 0x0FFFFFFF, then ASSERT().
154 @param Address Address that encodes the PCI Bus, Device, Function and
156 @param AndData The value to AND with the PCI configuration register.
158 @return The value written back to the PCI configuration register.
169 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
170 value, followed by a bitwise OR with another 8-bit value.
172 Reads the 8-bit PCI configuration register specified by Address, performs a
173 bitwise AND between the read result and the value specified by AndData,
174 performs a bitwise OR between the result of the AND operation and
175 the value specified by OrData, and writes the result to the 8-bit PCI
176 configuration register specified by Address. The value written to the PCI
177 configuration register is returned. This function must guarantee that all PCI
178 read and write operations are serialized.
180 If Address > 0x0FFFFFFF, then ASSERT().
182 @param Address Address that encodes the PCI Bus, Device, Function and
184 @param AndData The value to AND with the PCI configuration register.
185 @param OrData The value to OR with the result of the AND operation.
187 @return The value written back to the PCI configuration register.
199 Reads a bit field of a PCI configuration register.
201 Reads the bit field in an 8-bit PCI configuration register. The bit field is
202 specified by the StartBit and the EndBit. The value of the bit field is
205 If Address > 0x0FFFFFFF, then ASSERT().
206 If StartBit is greater than 7, then ASSERT().
207 If EndBit is greater than 7, then ASSERT().
208 If EndBit is less than StartBit, then ASSERT().
210 @param Address PCI configuration register to read.
211 @param StartBit The ordinal of the least significant bit in the bit field.
213 @param EndBit The ordinal of the most significant bit in the bit field.
216 @return The value of the bit field read from the PCI configuration register.
228 Writes a bit field to a PCI configuration register.
230 Writes Value to the bit field of the PCI configuration register. The bit
231 field is specified by the StartBit and the EndBit. All other bits in the
232 destination PCI configuration register are preserved. The new value of the
233 8-bit register is returned.
235 If Address > 0x0FFFFFFF, then ASSERT().
236 If StartBit is greater than 7, then ASSERT().
237 If EndBit is greater than 7, then ASSERT().
238 If EndBit is less than StartBit, then ASSERT().
239 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
241 @param Address PCI configuration register to write.
242 @param StartBit The ordinal of the least significant bit in the bit field.
244 @param EndBit The ordinal of the most significant bit in the bit field.
246 @param Value New value of the bit field.
248 @return The value written back to the PCI configuration register.
261 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
262 writes the result back to the bit field in the 8-bit port.
264 Reads the 8-bit PCI configuration register specified by Address, performs a
265 bitwise OR between the read result and the value specified by
266 OrData, and writes the result to the 8-bit PCI configuration register
267 specified by Address. The value written to the PCI configuration register is
268 returned. This function must guarantee that all PCI read and write operations
269 are serialized. Extra left bits in OrData are stripped.
271 If Address > 0x0FFFFFFF, then ASSERT().
272 If StartBit is greater than 7, then ASSERT().
273 If EndBit is greater than 7, then ASSERT().
274 If EndBit is less than StartBit, then ASSERT().
275 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
277 @param Address PCI configuration register to write.
278 @param StartBit The ordinal of the least significant bit in the bit field.
280 @param EndBit The ordinal of the most significant bit in the bit field.
282 @param OrData The value to OR with the PCI configuration register.
284 @return The value written back to the PCI configuration register.
297 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
298 AND, and writes the result back to the bit field in the 8-bit register.
300 Reads the 8-bit PCI configuration register specified by Address, performs a
301 bitwise AND between the read result and the value specified by AndData, and
302 writes the result to the 8-bit PCI configuration register specified by
303 Address. The value written to the PCI configuration register is returned.
304 This function must guarantee that all PCI read and write operations are
305 serialized. Extra left bits in AndData are stripped.
307 If Address > 0x0FFFFFFF, then ASSERT().
308 If StartBit is greater than 7, then ASSERT().
309 If EndBit is greater than 7, then ASSERT().
310 If EndBit is less than StartBit, then ASSERT().
311 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
313 @param Address PCI configuration register to write.
314 @param StartBit The ordinal of the least significant bit in the bit field.
316 @param EndBit The ordinal of the most significant bit in the bit field.
318 @param AndData The value to AND with the PCI configuration register.
320 @return The value written back to the PCI configuration register.
333 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
334 bitwise OR, and writes the result back to the bit field in the
337 Reads the 8-bit PCI configuration register specified by Address, performs a
338 bitwise AND followed by a bitwise OR between the read result and
339 the value specified by AndData, and writes the result to the 8-bit PCI
340 configuration register specified by Address. The value written to the PCI
341 configuration register is returned. This function must guarantee that all PCI
342 read and write operations are serialized. Extra left bits in both AndData and
345 If Address > 0x0FFFFFFF, then ASSERT().
346 If StartBit is greater than 7, then ASSERT().
347 If EndBit is greater than 7, then ASSERT().
348 If EndBit is less than StartBit, then ASSERT().
349 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
350 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
352 @param Address PCI configuration register to write.
353 @param StartBit The ordinal of the least significant bit in the bit field.
355 @param EndBit The ordinal of the most significant bit in the bit field.
357 @param AndData The value to AND with the PCI configuration register.
358 @param OrData The value to OR with the result of the AND operation.
360 @return The value written back to the PCI configuration register.
365 PciBitFieldAndThenOr8 (
374 Reads a 16-bit PCI configuration register.
376 Reads and returns the 16-bit PCI configuration register specified by Address.
377 This function must guarantee that all PCI read and write operations are
380 If Address > 0x0FFFFFFF, then ASSERT().
381 If Address is not aligned on a 16-bit boundary, then ASSERT().
383 @param Address Address that encodes the PCI Bus, Device, Function and
386 @return The read value from the PCI configuration register.
396 Writes a 16-bit PCI configuration register.
398 Writes the 16-bit PCI configuration register specified by Address with the
399 value specified by Value. Value is returned. This function must guarantee
400 that all PCI read and write operations are serialized.
402 If Address > 0x0FFFFFFF, then ASSERT().
403 If Address is not aligned on a 16-bit boundary, then ASSERT().
405 @param Address Address that encodes the PCI Bus, Device, Function and
407 @param Value The value to write.
409 @return The value written to the PCI configuration register.
420 Performs a bitwise OR of a 16-bit PCI configuration register with
423 Reads the 16-bit PCI configuration register specified by Address, performs a
424 bitwise OR between the read result and the value specified by
425 OrData, and writes the result to the 16-bit PCI configuration register
426 specified by Address. The value written to the PCI configuration register is
427 returned. This function must guarantee that all PCI read and write operations
430 If Address > 0x0FFFFFFF, then ASSERT().
431 If Address is not aligned on a 16-bit boundary, then ASSERT().
433 @param Address Address that encodes the PCI Bus, Device, Function and
435 @param OrData The value to OR with the PCI configuration register.
437 @return The value written back to the PCI configuration register.
448 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
451 Reads the 16-bit PCI configuration register specified by Address, performs a
452 bitwise AND between the read result and the value specified by AndData, and
453 writes the result to the 16-bit PCI configuration register specified by
454 Address. The value written to the PCI configuration register is returned.
455 This function must guarantee that all PCI read and write operations are
458 If Address > 0x0FFFFFFF, then ASSERT().
459 If Address is not aligned on a 16-bit boundary, then ASSERT().
461 @param Address Address that encodes the PCI Bus, Device, Function and
463 @param AndData The value to AND with the PCI configuration register.
465 @return The value written back to the PCI configuration register.
476 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
477 value, followed a bitwise OR with another 16-bit value.
479 Reads the 16-bit PCI configuration register specified by Address, performs a
480 bitwise AND between the read result and the value specified by AndData,
481 performs a bitwise OR between the result of the AND operation and
482 the value specified by OrData, and writes the result to the 16-bit PCI
483 configuration register specified by Address. The value written to the PCI
484 configuration register is returned. This function must guarantee that all PCI
485 read and write operations are serialized.
487 If Address > 0x0FFFFFFF, then ASSERT().
488 If Address is not aligned on a 16-bit boundary, then ASSERT().
490 @param Address Address that encodes the PCI Bus, Device, Function and
492 @param AndData The value to AND with the PCI configuration register.
493 @param OrData The value to OR with the result of the AND operation.
495 @return The value written back to the PCI configuration register.
507 Reads a bit field of a PCI configuration register.
509 Reads the bit field in a 16-bit PCI configuration register. The bit field is
510 specified by the StartBit and the EndBit. The value of the bit field is
513 If Address > 0x0FFFFFFF, then ASSERT().
514 If Address is not aligned on a 16-bit boundary, then ASSERT().
515 If StartBit is greater than 15, then ASSERT().
516 If EndBit is greater than 15, then ASSERT().
517 If EndBit is less than StartBit, then ASSERT().
519 @param Address PCI configuration register to read.
520 @param StartBit The ordinal of the least significant bit in the bit field.
522 @param EndBit The ordinal of the most significant bit in the bit field.
525 @return The value of the bit field read from the PCI configuration register.
537 Writes a bit field to a PCI configuration register.
539 Writes Value to the bit field of the PCI configuration register. The bit
540 field is specified by the StartBit and the EndBit. All other bits in the
541 destination PCI configuration register are preserved. The new value of the
542 16-bit register is returned.
544 If Address > 0x0FFFFFFF, then ASSERT().
545 If Address is not aligned on a 16-bit boundary, then ASSERT().
546 If StartBit is greater than 15, then ASSERT().
547 If EndBit is greater than 15, then ASSERT().
548 If EndBit is less than StartBit, then ASSERT().
549 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
551 @param Address PCI configuration register to write.
552 @param StartBit The ordinal of the least significant bit in the bit field.
554 @param EndBit The ordinal of the most significant bit in the bit field.
556 @param Value New value of the bit field.
558 @return The value written back to the PCI configuration register.
571 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
572 writes the result back to the bit field in the 16-bit port.
574 Reads the 16-bit PCI configuration register specified by Address, performs a
575 bitwise OR between the read result and the value specified by
576 OrData, and writes the result to the 16-bit PCI configuration register
577 specified by Address. The value written to the PCI configuration register is
578 returned. This function must guarantee that all PCI read and write operations
579 are serialized. Extra left bits in OrData are stripped.
581 If Address > 0x0FFFFFFF, then ASSERT().
582 If Address is not aligned on a 16-bit boundary, then ASSERT().
583 If StartBit is greater than 15, then ASSERT().
584 If EndBit is greater than 15, then ASSERT().
585 If EndBit is less than StartBit, then ASSERT().
586 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
588 @param Address PCI configuration register to write.
589 @param StartBit The ordinal of the least significant bit in the bit field.
591 @param EndBit The ordinal of the most significant bit in the bit field.
593 @param OrData The value to OR with the PCI configuration register.
595 @return The value written back to the PCI configuration register.
608 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
609 AND, and writes the result back to the bit field in the 16-bit register.
611 Reads the 16-bit PCI configuration register specified by Address, performs a
612 bitwise AND between the read result and the value specified by AndData, and
613 writes the result to the 16-bit PCI configuration register specified by
614 Address. The value written to the PCI configuration register is returned.
615 This function must guarantee that all PCI read and write operations are
616 serialized. Extra left bits in AndData are stripped.
618 If Address > 0x0FFFFFFF, then ASSERT().
619 If Address is not aligned on a 16-bit boundary, then ASSERT().
620 If StartBit is greater than 15, then ASSERT().
621 If EndBit is greater than 15, then ASSERT().
622 If EndBit is less than StartBit, then ASSERT().
623 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
625 @param Address PCI configuration register to write.
626 @param StartBit The ordinal of the least significant bit in the bit field.
628 @param EndBit The ordinal of the most significant bit in the bit field.
630 @param AndData The value to AND with the PCI configuration register.
632 @return The value written back to the PCI configuration register.
645 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
646 bitwise OR, and writes the result back to the bit field in the
649 Reads the 16-bit PCI configuration register specified by Address, performs a
650 bitwise AND followed by a bitwise OR between the read result and
651 the value specified by AndData, and writes the result to the 16-bit PCI
652 configuration register specified by Address. The value written to the PCI
653 configuration register is returned. This function must guarantee that all PCI
654 read and write operations are serialized. Extra left bits in both AndData and
657 If Address > 0x0FFFFFFF, then ASSERT().
658 If Address is not aligned on a 16-bit boundary, then ASSERT().
659 If StartBit is greater than 15, then ASSERT().
660 If EndBit is greater than 15, then ASSERT().
661 If EndBit is less than StartBit, then ASSERT().
662 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
663 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
665 @param Address PCI configuration register to write.
666 @param StartBit The ordinal of the least significant bit in the bit field.
668 @param EndBit The ordinal of the most significant bit in the bit field.
670 @param AndData The value to AND with the PCI configuration register.
671 @param OrData The value to OR with the result of the AND operation.
673 @return The value written back to the PCI configuration register.
678 PciBitFieldAndThenOr16 (
687 Reads a 32-bit PCI configuration register.
689 Reads and returns the 32-bit PCI configuration register specified by Address.
690 This function must guarantee that all PCI read and write operations are
693 If Address > 0x0FFFFFFF, then ASSERT().
694 If Address is not aligned on a 32-bit boundary, then ASSERT().
696 @param Address Address that encodes the PCI Bus, Device, Function and
699 @return The read value from the PCI configuration register.
709 Writes a 32-bit PCI configuration register.
711 Writes the 32-bit PCI configuration register specified by Address with the
712 value specified by Value. Value is returned. This function must guarantee
713 that all PCI read and write operations are serialized.
715 If Address > 0x0FFFFFFF, then ASSERT().
716 If Address is not aligned on a 32-bit boundary, then ASSERT().
718 @param Address Address that encodes the PCI Bus, Device, Function and
720 @param Value The value to write.
722 @return The value written to the PCI configuration register.
733 Performs a bitwise OR of a 32-bit PCI configuration register with
736 Reads the 32-bit PCI configuration register specified by Address, performs a
737 bitwise OR between the read result and the value specified by
738 OrData, and writes the result to the 32-bit PCI configuration register
739 specified by Address. The value written to the PCI configuration register is
740 returned. This function must guarantee that all PCI read and write operations
743 If Address > 0x0FFFFFFF, then ASSERT().
744 If Address is not aligned on a 32-bit boundary, then ASSERT().
746 @param Address Address that encodes the PCI Bus, Device, Function and
748 @param OrData The value to OR with the PCI configuration register.
750 @return The value written back to the PCI configuration register.
761 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
764 Reads the 32-bit PCI configuration register specified by Address, performs a
765 bitwise AND between the read result and the value specified by AndData, and
766 writes the result to the 32-bit PCI configuration register specified by
767 Address. The value written to the PCI configuration register is returned.
768 This function must guarantee that all PCI read and write operations are
771 If Address > 0x0FFFFFFF, then ASSERT().
772 If Address is not aligned on a 32-bit boundary, then ASSERT().
774 @param Address Address that encodes the PCI Bus, Device, Function and
776 @param AndData The value to AND with the PCI configuration register.
778 @return The value written back to the PCI configuration register.
789 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
790 value, followed a bitwise OR with another 32-bit value.
792 Reads the 32-bit PCI configuration register specified by Address, performs a
793 bitwise AND between the read result and the value specified by AndData,
794 performs a bitwise OR between the result of the AND operation and
795 the value specified by OrData, and writes the result to the 32-bit PCI
796 configuration register specified by Address. The value written to the PCI
797 configuration register is returned. This function must guarantee that all PCI
798 read and write operations are serialized.
800 If Address > 0x0FFFFFFF, then ASSERT().
801 If Address is not aligned on a 32-bit boundary, then ASSERT().
803 @param Address Address that encodes the PCI Bus, Device, Function and
805 @param AndData The value to AND with the PCI configuration register.
806 @param OrData The value to OR with the result of the AND operation.
808 @return The value written back to the PCI configuration register.
820 Reads a bit field of a PCI configuration register.
822 Reads the bit field in a 32-bit PCI configuration register. The bit field is
823 specified by the StartBit and the EndBit. The value of the bit field is
826 If Address > 0x0FFFFFFF, then ASSERT().
827 If Address is not aligned on a 32-bit boundary, then ASSERT().
828 If StartBit is greater than 31, then ASSERT().
829 If EndBit is greater than 31, then ASSERT().
830 If EndBit is less than StartBit, then ASSERT().
832 @param Address PCI configuration register to read.
833 @param StartBit The ordinal of the least significant bit in the bit field.
835 @param EndBit The ordinal of the most significant bit in the bit field.
838 @return The value of the bit field read from the PCI configuration register.
850 Writes a bit field to a PCI configuration register.
852 Writes Value to the bit field of the PCI configuration register. The bit
853 field is specified by the StartBit and the EndBit. All other bits in the
854 destination PCI configuration register are preserved. The new value of the
855 32-bit register is returned.
857 If Address > 0x0FFFFFFF, then ASSERT().
858 If Address is not aligned on a 32-bit boundary, then ASSERT().
859 If StartBit is greater than 31, then ASSERT().
860 If EndBit is greater than 31, then ASSERT().
861 If EndBit is less than StartBit, then ASSERT().
862 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
864 @param Address PCI configuration register to write.
865 @param StartBit The ordinal of the least significant bit in the bit field.
867 @param EndBit The ordinal of the most significant bit in the bit field.
869 @param Value New value of the bit field.
871 @return The value written back to the PCI configuration register.
884 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
885 writes the result back to the bit field in the 32-bit port.
887 Reads the 32-bit PCI configuration register specified by Address, performs a
888 bitwise OR between the read result and the value specified by
889 OrData, and writes the result to the 32-bit PCI configuration register
890 specified by Address. The value written to the PCI configuration register is
891 returned. This function must guarantee that all PCI read and write operations
892 are serialized. Extra left bits in OrData are stripped.
894 If Address > 0x0FFFFFFF, then ASSERT().
895 If Address is not aligned on a 32-bit boundary, then ASSERT().
896 If StartBit is greater than 31, then ASSERT().
897 If EndBit is greater than 31, then ASSERT().
898 If EndBit is less than StartBit, then ASSERT().
899 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
901 @param Address PCI configuration register to write.
902 @param StartBit The ordinal of the least significant bit in the bit field.
904 @param EndBit The ordinal of the most significant bit in the bit field.
906 @param OrData The value to OR with the PCI configuration register.
908 @return The value written back to the PCI configuration register.
921 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
922 AND, and writes the result back to the bit field in the 32-bit register.
924 Reads the 32-bit PCI configuration register specified by Address, performs a
925 bitwise AND between the read result and the value specified by AndData, and
926 writes the result to the 32-bit PCI configuration register specified by
927 Address. The value written to the PCI configuration register is returned.
928 This function must guarantee that all PCI read and write operations are
929 serialized. Extra left bits in AndData are stripped.
931 If Address > 0x0FFFFFFF, then ASSERT().
932 If Address is not aligned on a 32-bit boundary, then ASSERT().
933 If StartBit is greater than 31, then ASSERT().
934 If EndBit is greater than 31, then ASSERT().
935 If EndBit is less than StartBit, then ASSERT().
936 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
938 @param Address PCI configuration register to write.
939 @param StartBit The ordinal of the least significant bit in the bit field.
941 @param EndBit The ordinal of the most significant bit in the bit field.
943 @param AndData The value to AND with the PCI configuration register.
945 @return The value written back to the PCI configuration register.
958 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
959 bitwise OR, and writes the result back to the bit field in the
962 Reads the 32-bit PCI configuration register specified by Address, performs a
963 bitwise AND followed by a bitwise OR between the read result and
964 the value specified by AndData, and writes the result to the 32-bit PCI
965 configuration register specified by Address. The value written to the PCI
966 configuration register is returned. This function must guarantee that all PCI
967 read and write operations are serialized. Extra left bits in both AndData and
970 If Address > 0x0FFFFFFF, then ASSERT().
971 If Address is not aligned on a 32-bit boundary, then ASSERT().
972 If StartBit is greater than 31, then ASSERT().
973 If EndBit is greater than 31, then ASSERT().
974 If EndBit is less than StartBit, then ASSERT().
975 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
976 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
978 @param Address PCI configuration register to write.
979 @param StartBit The ordinal of the least significant bit in the bit field.
981 @param EndBit The ordinal of the most significant bit in the bit field.
983 @param AndData The value to AND with the PCI configuration register.
984 @param OrData The value to OR with the result of the AND operation.
986 @return The value written back to the PCI configuration register.
991 PciBitFieldAndThenOr32 (
1000 Reads a range of PCI configuration registers into a caller supplied buffer.
1002 Reads the range of PCI configuration registers specified by StartAddress and
1003 Size into the buffer specified by Buffer. This function only allows the PCI
1004 configuration registers from a single PCI function to be read. Size is
1005 returned. When possible 32-bit PCI configuration read cycles are used to read
1006 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1007 and 16-bit PCI configuration read cycles may be used at the beginning and the
1010 If StartAddress > 0x0FFFFFFF, then ASSERT().
1011 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1012 If Size > 0 and Buffer is NULL, then ASSERT().
1014 @param StartAddress Starting address that encodes the PCI Bus, Device,
1015 Function and Register.
1016 @param Size Size in bytes of the transfer.
1017 @param Buffer Pointer to a buffer receiving the data read.
1025 IN UINTN StartAddress
,
1031 Copies the data in a caller supplied buffer to a specified range of PCI
1032 configuration space.
1034 Writes the range of PCI configuration registers specified by StartAddress and
1035 Size from the buffer specified by Buffer. This function only allows the PCI
1036 configuration registers from a single PCI function to be written. Size is
1037 returned. When possible 32-bit PCI configuration write cycles are used to
1038 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1039 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1040 and the end of the range.
1042 If StartAddress > 0x0FFFFFFF, then ASSERT().
1043 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1044 If Size > 0 and Buffer is NULL, then ASSERT().
1046 @param StartAddress Starting address that encodes the PCI Bus, Device,
1047 Function and Register.
1048 @param Size Size in bytes of the transfer.
1049 @param Buffer Pointer to a buffer containing the data to write.
1051 @return Size written to StartAddress.
1057 IN UINTN StartAddress
,