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2 Provides services to access PCI Configuration Space.
4 Copyright (c) 2006 - 2008, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
20 address that can be passed to the PCI Library functions.
22 @param Bus PCI Bus number. Range 0..255.
23 @param Device PCI Device number. Range 0..31.
24 @param Function PCI Function number. Range 0..7.
25 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
28 @return The encoded PCI address.
31 #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \
32 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
35 Reads an 8-bit PCI configuration register.
37 Reads and returns the 8-bit PCI configuration register specified by Address.
38 This function must guarantee that all PCI read and write operations are
41 If Address > 0x0FFFFFFF, then ASSERT().
43 @param Address Address that encodes the PCI Bus, Device, Function and
46 @return The read value from the PCI configuration register.
56 Writes an 8-bit PCI configuration register.
58 Writes the 8-bit PCI configuration register specified by Address with the
59 value specified by Value. Value is returned. This function must guarantee
60 that all PCI read and write operations are serialized.
62 If Address > 0x0FFFFFFF, then ASSERT().
64 @param Address Address that encodes the PCI Bus, Device, Function and
66 @param Value The value to write.
68 @return The value written to the PCI configuration register.
79 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
82 Reads the 8-bit PCI configuration register specified by Address, performs a
83 bitwise inclusive OR between the read result and the value specified by
84 OrData, and writes the result to the 8-bit PCI configuration register
85 specified by Address. The value written to the PCI configuration register is
86 returned. This function must guarantee that all PCI read and write operations
89 If Address > 0x0FFFFFFF, then ASSERT().
91 @param Address Address that encodes the PCI Bus, Device, Function and
93 @param OrData The value to OR with the PCI configuration register.
95 @return The value written back to the PCI configuration register.
106 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
109 Reads the 8-bit PCI configuration register specified by Address, performs a
110 bitwise AND between the read result and the value specified by AndData, and
111 writes the result to the 8-bit PCI configuration register specified by
112 Address. The value written to the PCI configuration register is returned.
113 This function must guarantee that all PCI read and write operations are
116 If Address > 0x0FFFFFFF, then ASSERT().
118 @param Address Address that encodes the PCI Bus, Device, Function and
120 @param AndData The value to AND with the PCI configuration register.
122 @return The value written back to the PCI configuration register.
133 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
134 value, followed a bitwise inclusive OR with another 8-bit value.
136 Reads the 8-bit PCI configuration register specified by Address, performs a
137 bitwise AND between the read result and the value specified by AndData,
138 performs a bitwise inclusive OR between the result of the AND operation and
139 the value specified by OrData, and writes the result to the 8-bit PCI
140 configuration register specified by Address. The value written to the PCI
141 configuration register is returned. This function must guarantee that all PCI
142 read and write operations are serialized.
144 If Address > 0x0FFFFFFF, then ASSERT().
146 @param Address Address that encodes the PCI Bus, Device, Function and
148 @param AndData The value to AND with the PCI configuration register.
149 @param OrData The value to OR with the result of the AND operation.
151 @return The value written back to the PCI configuration register.
163 Reads a bit field of a PCI configuration register.
165 Reads the bit field in an 8-bit PCI configuration register. The bit field is
166 specified by the StartBit and the EndBit. The value of the bit field is
169 If Address > 0x0FFFFFFF, then ASSERT().
170 If StartBit is greater than 7, then ASSERT().
171 If EndBit is greater than 7, then ASSERT().
172 If EndBit is less than StartBit, then ASSERT().
174 @param Address PCI configuration register to read.
175 @param StartBit The ordinal of the least significant bit in the bit field.
177 @param EndBit The ordinal of the most significant bit in the bit field.
180 @return The value of the bit field read from the PCI configuration register.
192 Writes a bit field to a PCI configuration register.
194 Writes Value to the bit field of the PCI configuration register. The bit
195 field is specified by the StartBit and the EndBit. All other bits in the
196 destination PCI configuration register are preserved. The new value of the
197 8-bit register is returned.
199 If Address > 0x0FFFFFFF, then ASSERT().
200 If StartBit is greater than 7, then ASSERT().
201 If EndBit is greater than 7, then ASSERT().
202 If EndBit is less than StartBit, then ASSERT().
204 @param Address PCI configuration register to write.
205 @param StartBit The ordinal of the least significant bit in the bit field.
207 @param EndBit The ordinal of the most significant bit in the bit field.
209 @param Value New value of the bit field.
211 @return The value written back to the PCI configuration register.
224 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
225 writes the result back to the bit field in the 8-bit port.
227 Reads the 8-bit PCI configuration register specified by Address, performs a
228 bitwise inclusive OR between the read result and the value specified by
229 OrData, and writes the result to the 8-bit PCI configuration register
230 specified by Address. The value written to the PCI configuration register is
231 returned. This function must guarantee that all PCI read and write operations
232 are serialized. Extra left bits in OrData are stripped.
234 If Address > 0x0FFFFFFF, then ASSERT().
235 If StartBit is greater than 7, then ASSERT().
236 If EndBit is greater than 7, then ASSERT().
237 If EndBit is less than StartBit, then ASSERT().
239 @param Address PCI configuration register to write.
240 @param StartBit The ordinal of the least significant bit in the bit field.
242 @param EndBit The ordinal of the most significant bit in the bit field.
244 @param OrData The value to OR with the PCI configuration register.
246 @return The value written back to the PCI configuration register.
259 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
260 AND, and writes the result back to the bit field in the 8-bit register.
262 Reads the 8-bit PCI configuration register specified by Address, performs a
263 bitwise AND between the read result and the value specified by AndData, and
264 writes the result to the 8-bit PCI configuration register specified by
265 Address. The value written to the PCI configuration register is returned.
266 This function must guarantee that all PCI read and write operations are
267 serialized. Extra left bits in AndData are stripped.
269 If Address > 0x0FFFFFFF, then ASSERT().
270 If StartBit is greater than 7, then ASSERT().
271 If EndBit is greater than 7, then ASSERT().
272 If EndBit is less than StartBit, then ASSERT().
274 @param Address PCI configuration register to write.
275 @param StartBit The ordinal of the least significant bit in the bit field.
277 @param EndBit The ordinal of the most significant bit in the bit field.
279 @param AndData The value to AND with the PCI configuration register.
281 @return The value written back to the PCI configuration register.
294 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
295 bitwise inclusive OR, and writes the result back to the bit field in the
298 Reads the 8-bit PCI configuration register specified by Address, performs a
299 bitwise AND followed by a bitwise inclusive OR between the read result and
300 the value specified by AndData, and writes the result to the 8-bit PCI
301 configuration register specified by Address. The value written to the PCI
302 configuration register is returned. This function must guarantee that all PCI
303 read and write operations are serialized. Extra left bits in both AndData and
306 If Address > 0x0FFFFFFF, then ASSERT().
307 If StartBit is greater than 7, then ASSERT().
308 If EndBit is greater than 7, then ASSERT().
309 If EndBit is less than StartBit, then ASSERT().
311 @param Address PCI configuration register to write.
312 @param StartBit The ordinal of the least significant bit in the bit field.
314 @param EndBit The ordinal of the most significant bit in the bit field.
316 @param AndData The value to AND with the PCI configuration register.
317 @param OrData The value to OR with the result of the AND operation.
319 @return The value written back to the PCI configuration register.
324 PciBitFieldAndThenOr8 (
333 Reads a 16-bit PCI configuration register.
335 Reads and returns the 16-bit PCI configuration register specified by Address.
336 This function must guarantee that all PCI read and write operations are
339 If Address > 0x0FFFFFFF, then ASSERT().
340 If Address is not aligned on a 16-bit boundary, then ASSERT().
342 @param Address Address that encodes the PCI Bus, Device, Function and
345 @return The read value from the PCI configuration register.
355 Writes a 16-bit PCI configuration register.
357 Writes the 16-bit PCI configuration register specified by Address with the
358 value specified by Value. Value is returned. This function must guarantee
359 that all PCI read and write operations are serialized.
361 If Address > 0x0FFFFFFF, then ASSERT().
362 If Address is not aligned on a 16-bit boundary, then ASSERT().
364 @param Address Address that encodes the PCI Bus, Device, Function and
366 @param Value The value to write.
368 @return The value written to the PCI configuration register.
379 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
382 Reads the 16-bit PCI configuration register specified by Address, performs a
383 bitwise inclusive OR between the read result and the value specified by
384 OrData, and writes the result to the 16-bit PCI configuration register
385 specified by Address. The value written to the PCI configuration register is
386 returned. This function must guarantee that all PCI read and write operations
389 If Address > 0x0FFFFFFF, then ASSERT().
390 If Address is not aligned on a 16-bit boundary, then ASSERT().
392 @param Address Address that encodes the PCI Bus, Device, Function and
394 @param OrData The value to OR with the PCI configuration register.
396 @return The value written back to the PCI configuration register.
407 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
410 Reads the 16-bit PCI configuration register specified by Address, performs a
411 bitwise AND between the read result and the value specified by AndData, and
412 writes the result to the 16-bit PCI configuration register specified by
413 Address. The value written to the PCI configuration register is returned.
414 This function must guarantee that all PCI read and write operations are
417 If Address > 0x0FFFFFFF, then ASSERT().
418 If Address is not aligned on a 16-bit boundary, then ASSERT().
420 @param Address Address that encodes the PCI Bus, Device, Function and
422 @param AndData The value to AND with the PCI configuration register.
424 @return The value written back to the PCI configuration register.
435 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
436 value, followed a bitwise inclusive OR with another 16-bit value.
438 Reads the 16-bit PCI configuration register specified by Address, performs a
439 bitwise AND between the read result and the value specified by AndData,
440 performs a bitwise inclusive OR between the result of the AND operation and
441 the value specified by OrData, and writes the result to the 16-bit PCI
442 configuration register specified by Address. The value written to the PCI
443 configuration register is returned. This function must guarantee that all PCI
444 read and write operations are serialized.
446 If Address > 0x0FFFFFFF, then ASSERT().
447 If Address is not aligned on a 16-bit boundary, then ASSERT().
449 @param Address Address that encodes the PCI Bus, Device, Function and
451 @param AndData The value to AND with the PCI configuration register.
452 @param OrData The value to OR with the result of the AND operation.
454 @return The value written back to the PCI configuration register.
466 Reads a bit field of a PCI configuration register.
468 Reads the bit field in a 16-bit PCI configuration register. The bit field is
469 specified by the StartBit and the EndBit. The value of the bit field is
472 If Address > 0x0FFFFFFF, then ASSERT().
473 If Address is not aligned on a 16-bit boundary, then ASSERT().
474 If StartBit is greater than 15, then ASSERT().
475 If EndBit is greater than 15, then ASSERT().
476 If EndBit is less than StartBit, then ASSERT().
478 @param Address PCI configuration register to read.
479 @param StartBit The ordinal of the least significant bit in the bit field.
481 @param EndBit The ordinal of the most significant bit in the bit field.
484 @return The value of the bit field read from the PCI configuration register.
496 Writes a bit field to a PCI configuration register.
498 Writes Value to the bit field of the PCI configuration register. The bit
499 field is specified by the StartBit and the EndBit. All other bits in the
500 destination PCI configuration register are preserved. The new value of the
501 16-bit register is returned.
503 If Address > 0x0FFFFFFF, then ASSERT().
504 If Address is not aligned on a 16-bit boundary, then ASSERT().
505 If StartBit is greater than 15, then ASSERT().
506 If EndBit is greater than 15, then ASSERT().
507 If EndBit is less than StartBit, then ASSERT().
509 @param Address PCI configuration register to write.
510 @param StartBit The ordinal of the least significant bit in the bit field.
512 @param EndBit The ordinal of the most significant bit in the bit field.
514 @param Value New value of the bit field.
516 @return The value written back to the PCI configuration register.
529 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
530 writes the result back to the bit field in the 16-bit port.
532 Reads the 16-bit PCI configuration register specified by Address, performs a
533 bitwise inclusive OR between the read result and the value specified by
534 OrData, and writes the result to the 16-bit PCI configuration register
535 specified by Address. The value written to the PCI configuration register is
536 returned. This function must guarantee that all PCI read and write operations
537 are serialized. Extra left bits in OrData are stripped.
539 If Address > 0x0FFFFFFF, then ASSERT().
540 If Address is not aligned on a 16-bit boundary, then ASSERT().
541 If StartBit is greater than 15, then ASSERT().
542 If EndBit is greater than 15, then ASSERT().
543 If EndBit is less than StartBit, then ASSERT().
545 @param Address PCI configuration register to write.
546 @param StartBit The ordinal of the least significant bit in the bit field.
548 @param EndBit The ordinal of the most significant bit in the bit field.
550 @param OrData The value to OR with the PCI configuration register.
552 @return The value written back to the PCI configuration register.
565 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
566 AND, and writes the result back to the bit field in the 16-bit register.
568 Reads the 16-bit PCI configuration register specified by Address, performs a
569 bitwise AND between the read result and the value specified by AndData, and
570 writes the result to the 16-bit PCI configuration register specified by
571 Address. The value written to the PCI configuration register is returned.
572 This function must guarantee that all PCI read and write operations are
573 serialized. Extra left bits in AndData are stripped.
575 If Address > 0x0FFFFFFF, then ASSERT().
576 If Address is not aligned on a 16-bit boundary, then ASSERT().
577 If StartBit is greater than 15, then ASSERT().
578 If EndBit is greater than 15, then ASSERT().
579 If EndBit is less than StartBit, then ASSERT().
581 @param Address PCI configuration register to write.
582 @param StartBit The ordinal of the least significant bit in the bit field.
584 @param EndBit The ordinal of the most significant bit in the bit field.
586 @param AndData The value to AND with the PCI configuration register.
588 @return The value written back to the PCI configuration register.
601 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
602 bitwise inclusive OR, and writes the result back to the bit field in the
605 Reads the 16-bit PCI configuration register specified by Address, performs a
606 bitwise AND followed by a bitwise inclusive OR between the read result and
607 the value specified by AndData, and writes the result to the 16-bit PCI
608 configuration register specified by Address. The value written to the PCI
609 configuration register is returned. This function must guarantee that all PCI
610 read and write operations are serialized. Extra left bits in both AndData and
613 If Address > 0x0FFFFFFF, then ASSERT().
614 If Address is not aligned on a 16-bit boundary, then ASSERT().
615 If StartBit is greater than 15, then ASSERT().
616 If EndBit is greater than 15, then ASSERT().
617 If EndBit is less than StartBit, then ASSERT().
619 @param Address PCI configuration register to write.
620 @param StartBit The ordinal of the least significant bit in the bit field.
622 @param EndBit The ordinal of the most significant bit in the bit field.
624 @param AndData The value to AND with the PCI configuration register.
625 @param OrData The value to OR with the result of the AND operation.
627 @return The value written back to the PCI configuration register.
632 PciBitFieldAndThenOr16 (
641 Reads a 32-bit PCI configuration register.
643 Reads and returns the 32-bit PCI configuration register specified by Address.
644 This function must guarantee that all PCI read and write operations are
647 If Address > 0x0FFFFFFF, then ASSERT().
648 If Address is not aligned on a 32-bit boundary, then ASSERT().
650 @param Address Address that encodes the PCI Bus, Device, Function and
653 @return The read value from the PCI configuration register.
663 Writes a 32-bit PCI configuration register.
665 Writes the 32-bit PCI configuration register specified by Address with the
666 value specified by Value. Value is returned. This function must guarantee
667 that all PCI read and write operations are serialized.
669 If Address > 0x0FFFFFFF, then ASSERT().
670 If Address is not aligned on a 32-bit boundary, then ASSERT().
672 @param Address Address that encodes the PCI Bus, Device, Function and
674 @param Value The value to write.
676 @return The value written to the PCI configuration register.
687 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
690 Reads the 32-bit PCI configuration register specified by Address, performs a
691 bitwise inclusive OR between the read result and the value specified by
692 OrData, and writes the result to the 32-bit PCI configuration register
693 specified by Address. The value written to the PCI configuration register is
694 returned. This function must guarantee that all PCI read and write operations
697 If Address > 0x0FFFFFFF, then ASSERT().
698 If Address is not aligned on a 32-bit boundary, then ASSERT().
700 @param Address Address that encodes the PCI Bus, Device, Function and
702 @param OrData The value to OR with the PCI configuration register.
704 @return The value written back to the PCI configuration register.
715 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
718 Reads the 32-bit PCI configuration register specified by Address, performs a
719 bitwise AND between the read result and the value specified by AndData, and
720 writes the result to the 32-bit PCI configuration register specified by
721 Address. The value written to the PCI configuration register is returned.
722 This function must guarantee that all PCI read and write operations are
725 If Address > 0x0FFFFFFF, then ASSERT().
726 If Address is not aligned on a 32-bit boundary, then ASSERT().
728 @param Address Address that encodes the PCI Bus, Device, Function and
730 @param AndData The value to AND with the PCI configuration register.
732 @return The value written back to the PCI configuration register.
743 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
744 value, followed a bitwise inclusive OR with another 32-bit value.
746 Reads the 32-bit PCI configuration register specified by Address, performs a
747 bitwise AND between the read result and the value specified by AndData,
748 performs a bitwise inclusive OR between the result of the AND operation and
749 the value specified by OrData, and writes the result to the 32-bit PCI
750 configuration register specified by Address. The value written to the PCI
751 configuration register is returned. This function must guarantee that all PCI
752 read and write operations are serialized.
754 If Address > 0x0FFFFFFF, then ASSERT().
755 If Address is not aligned on a 32-bit boundary, then ASSERT().
757 @param Address Address that encodes the PCI Bus, Device, Function and
759 @param AndData The value to AND with the PCI configuration register.
760 @param OrData The value to OR with the result of the AND operation.
762 @return The value written back to the PCI configuration register.
774 Reads a bit field of a PCI configuration register.
776 Reads the bit field in a 32-bit PCI configuration register. The bit field is
777 specified by the StartBit and the EndBit. The value of the bit field is
780 If Address > 0x0FFFFFFF, then ASSERT().
781 If Address is not aligned on a 32-bit boundary, then ASSERT().
782 If StartBit is greater than 31, then ASSERT().
783 If EndBit is greater than 31, then ASSERT().
784 If EndBit is less than StartBit, then ASSERT().
786 @param Address PCI configuration register to read.
787 @param StartBit The ordinal of the least significant bit in the bit field.
789 @param EndBit The ordinal of the most significant bit in the bit field.
792 @return The value of the bit field read from the PCI configuration register.
804 Writes a bit field to a PCI configuration register.
806 Writes Value to the bit field of the PCI configuration register. The bit
807 field is specified by the StartBit and the EndBit. All other bits in the
808 destination PCI configuration register are preserved. The new value of the
809 32-bit register is returned.
811 If Address > 0x0FFFFFFF, then ASSERT().
812 If Address is not aligned on a 32-bit boundary, then ASSERT().
813 If StartBit is greater than 31, then ASSERT().
814 If EndBit is greater than 31, then ASSERT().
815 If EndBit is less than StartBit, then ASSERT().
817 @param Address PCI configuration register to write.
818 @param StartBit The ordinal of the least significant bit in the bit field.
820 @param EndBit The ordinal of the most significant bit in the bit field.
822 @param Value New value of the bit field.
824 @return The value written back to the PCI configuration register.
837 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
838 writes the result back to the bit field in the 32-bit port.
840 Reads the 32-bit PCI configuration register specified by Address, performs a
841 bitwise inclusive OR between the read result and the value specified by
842 OrData, and writes the result to the 32-bit PCI configuration register
843 specified by Address. The value written to the PCI configuration register is
844 returned. This function must guarantee that all PCI read and write operations
845 are serialized. Extra left bits in OrData are stripped.
847 If Address > 0x0FFFFFFF, then ASSERT().
848 If Address is not aligned on a 32-bit boundary, then ASSERT().
849 If StartBit is greater than 31, then ASSERT().
850 If EndBit is greater than 31, then ASSERT().
851 If EndBit is less than StartBit, then ASSERT().
853 @param Address PCI configuration register to write.
854 @param StartBit The ordinal of the least significant bit in the bit field.
856 @param EndBit The ordinal of the most significant bit in the bit field.
858 @param OrData The value to OR with the PCI configuration register.
860 @return The value written back to the PCI configuration register.
873 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
874 AND, and writes the result back to the bit field in the 32-bit register.
876 Reads the 32-bit PCI configuration register specified by Address, performs a
877 bitwise AND between the read result and the value specified by AndData, and
878 writes the result to the 32-bit PCI configuration register specified by
879 Address. The value written to the PCI configuration register is returned.
880 This function must guarantee that all PCI read and write operations are
881 serialized. Extra left bits in AndData are stripped.
883 If Address > 0x0FFFFFFF, then ASSERT().
884 If Address is not aligned on a 32-bit boundary, then ASSERT().
885 If StartBit is greater than 31, then ASSERT().
886 If EndBit is greater than 31, then ASSERT().
887 If EndBit is less than StartBit, then ASSERT().
889 @param Address PCI configuration register to write.
890 @param StartBit The ordinal of the least significant bit in the bit field.
892 @param EndBit The ordinal of the most significant bit in the bit field.
894 @param AndData The value to AND with the PCI configuration register.
896 @return The value written back to the PCI configuration register.
909 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
910 bitwise inclusive OR, and writes the result back to the bit field in the
913 Reads the 32-bit PCI configuration register specified by Address, performs a
914 bitwise AND followed by a bitwise inclusive OR between the read result and
915 the value specified by AndData, and writes the result to the 32-bit PCI
916 configuration register specified by Address. The value written to the PCI
917 configuration register is returned. This function must guarantee that all PCI
918 read and write operations are serialized. Extra left bits in both AndData and
921 If Address > 0x0FFFFFFF, then ASSERT().
922 If Address is not aligned on a 32-bit boundary, then ASSERT().
923 If StartBit is greater than 31, then ASSERT().
924 If EndBit is greater than 31, then ASSERT().
925 If EndBit is less than StartBit, then ASSERT().
927 @param Address PCI configuration register to write.
928 @param StartBit The ordinal of the least significant bit in the bit field.
930 @param EndBit The ordinal of the most significant bit in the bit field.
932 @param AndData The value to AND with the PCI configuration register.
933 @param OrData The value to OR with the result of the AND operation.
935 @return The value written back to the PCI configuration register.
940 PciBitFieldAndThenOr32 (
949 Reads a range of PCI configuration registers into a caller supplied buffer.
951 Reads the range of PCI configuration registers specified by StartAddress and
952 Size into the buffer specified by Buffer. This function only allows the PCI
953 configuration registers from a single PCI function to be read. Size is
954 returned. When possible 32-bit PCI configuration read cycles are used to read
955 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
956 and 16-bit PCI configuration read cycles may be used at the beginning and the
959 If StartAddress > 0x0FFFFFFF, then ASSERT().
960 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
961 If Size > 0 and Buffer is NULL, then ASSERT().
963 @param StartAddress Starting address that encodes the PCI Bus, Device,
964 Function and Register.
965 @param Size Size in bytes of the transfer.
966 @param Buffer Pointer to a buffer receiving the data read.
974 IN UINTN StartAddress
,
980 Copies the data in a caller supplied buffer to a specified range of PCI
983 Writes the range of PCI configuration registers specified by StartAddress and
984 Size from the buffer specified by Buffer. This function only allows the PCI
985 configuration registers from a single PCI function to be written. Size is
986 returned. When possible 32-bit PCI configuration write cycles are used to
987 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
988 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
989 and the end of the range.
991 If StartAddress > 0x0FFFFFFF, then ASSERT().
992 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
993 If Size > 0 and Buffer is NULL, then ASSERT().
995 @param StartAddress Starting address that encodes the PCI Bus, Device,
996 Function and Register.
997 @param Size Size in bytes of the transfer.
998 @param Buffer Pointer to a buffer containing the data to write.
1000 @return Size written to StartAddress.
1006 IN UINTN StartAddress
,