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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Library/S3PciLib.h
2 The PCI configuration Library Services that carry out PCI configuration and enable
3 the PCI operations to be replayed during an S3 resume. This library class
4 maps directly on top of the PciLib class.
6 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #ifndef __S3_PCI_LIB_H__
13 #define __S3_PCI_LIB_H__
16 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
17 address that can be passed to the S3 PCI Library functions.
19 @param Bus The PCI Bus number. Range 0..255.
20 @param Device The PCI Device number. Range 0..31.
21 @param Function The PCI Function number. Range 0..7.
22 @param Register The PCI Register number. Range 0..255 for PCI. Range 0..4095
25 @return The encoded PCI address.
28 #define S3_PCI_LIB_ADDRESS(Bus,Device,Function,Register) \
29 (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
33 Reads and returns the 8-bit PCI configuration register specified by Address,
34 and saves the value in the S3 script to be replayed on S3 resume.
35 This function must guarantee that all PCI read and write operations are
38 If Address > 0x0FFFFFFF, then ASSERT().
40 @param[in] Address The address that encodes the PCI Bus, Device, Function and
43 @return The value read from the PCI configuration register.
53 Writes an 8-bit PCI configuration register, and saves the value in the S3
54 script to be replayed on S3 resume.
56 Writes the 8-bit PCI configuration register specified by Address with the
57 value specified by Value. Value is returned. This function must guarantee
58 that all PCI read and write operations are serialized.
60 If Address > 0x0FFFFFFF, then ASSERT().
62 @param[in] Address The address that encodes the PCI Bus, Device, Function and
64 @param[in] Value The value to write.
66 @return The value written to the PCI configuration register.
77 Performs a bitwise OR of an 8-bit PCI configuration register with
78 an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.
80 Reads the 8-bit PCI configuration register specified by Address, performs a
81 bitwise OR between the read result and the value specified by
82 OrData, and writes the result to the 8-bit PCI configuration register
83 specified by Address. The value written to the PCI configuration register is
84 returned. This function must guarantee that all PCI read and write operations
87 If Address > 0x0FFFFFFF, then ASSERT().
89 @param[in] Address The address that encodes the PCI Bus, Device, Function and
91 @param[in] OrData The value to OR with the PCI configuration register.
93 @return The value written back to the PCI configuration register.
104 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
105 value, and saves the value in the S3 script to be replayed on S3 resume.
107 Reads the 8-bit PCI configuration register specified by Address, performs a
108 bitwise AND between the read result and the value specified by AndData, and
109 writes the result to the 8-bit PCI configuration register specified by
110 Address. The value written to the PCI configuration register is returned.
111 This function must guarantee that all PCI read and write operations are
114 If Address > 0x0FFFFFFF, then ASSERT().
116 @param[in] Address The address that encodes the PCI Bus, Device, Function and
118 @param[in] AndData The value to AND with the PCI configuration register.
120 @return The value written back to the PCI configuration register.
131 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
132 value, followed a bitwise OR with another 8-bit value, and saves
133 the value in the S3 script to be replayed on S3 resume.
135 Reads the 8-bit PCI configuration register specified by Address, performs a
136 bitwise AND between the read result and the value specified by AndData,
137 performs a bitwise OR between the result of the AND operation and
138 the value specified by OrData, and writes the result to the 8-bit PCI
139 configuration register specified by Address. The value written to the PCI
140 configuration register is returned. This function must guarantee that all PCI
141 read and write operations are serialized.
143 If Address > 0x0FFFFFFF, then ASSERT().
145 @param[in] Address The address that encodes the PCI Bus, Device, Function and
147 @param[in] AndData The value to AND with the PCI configuration register.
148 @param[in] OrData The value to OR with the result of the AND operation.
150 @return The value written back to the PCI configuration register.
162 Reads a bit field of a PCI configuration register, and saves the value in
163 the S3 script to be replayed on S3 resume.
165 Reads the bit field in an 8-bit PCI configuration register. The bit field is
166 specified by the StartBit and the EndBit. The value of the bit field is
169 If Address > 0x0FFFFFFF, then ASSERT().
170 If StartBit is greater than 7, then ASSERT().
171 If EndBit is greater than 7, then ASSERT().
172 If EndBit is less than StartBit, then ASSERT().
174 @param[in] Address The PCI configuration register to read.
175 @param[in] StartBit The ordinal of the least significant bit in the bit field.
177 @param[in] EndBit The ordinal of the most significant bit in the bit field.
180 @return The value of the bit field read from the PCI configuration register.
192 Writes a bit field to a PCI configuration register, and saves the value in
193 the S3 script to be replayed on S3 resume.
195 Writes Value to the bit field of the PCI configuration register. The bit
196 field is specified by the StartBit and the EndBit. All other bits in the
197 destination PCI configuration register are preserved. The new value of the
198 8-bit register is returned.
200 If Address > 0x0FFFFFFF, then ASSERT().
201 If StartBit is greater than 7, then ASSERT().
202 If EndBit is greater than 7, then ASSERT().
203 If EndBit is less than StartBit, then ASSERT().
204 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
206 @param[in] Address The PCI configuration register to write.
207 @param[in] StartBit The ordinal of the least significant bit in the bit field.
209 @param[in] EndBit The ordinal of the most significant bit in the bit field.
211 @param[in] Value New value of the bit field.
213 @return The value written back to the PCI configuration register.
218 S3PciBitFieldWrite8 (
226 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
227 writes the result back to the bit field in the 8-bit port, and saves the value
228 in the S3 script to be replayed on S3 resume.
230 Reads the 8-bit PCI configuration register specified by Address, performs a
231 bitwise OR between the read result and the value specified by
232 OrData, and writes the result to the 8-bit PCI configuration register
233 specified by Address. The value written to the PCI configuration register is
234 returned. This function must guarantee that all PCI read and write operations
235 are serialized. Extra left bits in OrData are stripped.
237 If Address > 0x0FFFFFFF, then ASSERT().
238 If StartBit is greater than 7, then ASSERT().
239 If EndBit is greater than 7, then ASSERT().
240 If EndBit is less than StartBit, then ASSERT().
241 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
243 @param[in] Address The PCI configuration register to write.
244 @param[in] StartBit The ordinal of the least significant bit in the bit field.
246 @param[in] EndBit The ordinal of the most significant bit in the bit field.
248 @param[in] OrData The value to OR with the PCI configuration register.
250 @return The value written back to the PCI configuration register.
263 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
264 AND, and writes the result back to the bit field in the 8-bit register and
265 saves the value in the S3 script to be replayed on S3 resume.
267 Reads the 8-bit PCI configuration register specified by Address, performs a
268 bitwise AND between the read result and the value specified by AndData, and
269 writes the result to the 8-bit PCI configuration register specified by
270 Address. The value written to the PCI configuration register is returned.
271 This function must guarantee that all PCI read and write operations are
272 serialized. Extra left bits in AndData are stripped.
274 If Address > 0x0FFFFFFF, then ASSERT().
275 If StartBit is greater than 7, then ASSERT().
276 If EndBit is greater than 7, then ASSERT().
277 If EndBit is less than StartBit, then ASSERT().
278 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
280 @param[in] Address The PCI configuration register to write.
281 @param[in] StartBit The ordinal of the least significant bit in the bit field.
283 @param[in] EndBit The ordinal of the most significant bit in the bit field.
285 @param[in] AndData The value to AND with the PCI configuration register.
287 @return The value written back to the PCI configuration register.
300 Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a
301 bitwise OR, and writes the result back to the bit field in the
302 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.
304 Reads the 8-bit PCI configuration register specified by Address, performs a
305 bitwise AND followed by a bitwise OR between the read result and
306 the value specified by AndData, and writes the result to the 8-bit PCI
307 configuration register specified by Address. The value written to the PCI
308 configuration register is returned. This function must guarantee that all PCI
309 read and write operations are serialized. Extra left bits in both AndData and
312 If Address > 0x0FFFFFFF, then ASSERT().
313 If StartBit is greater than 7, then ASSERT().
314 If EndBit is greater than 7, then ASSERT().
315 If EndBit is less than StartBit, then ASSERT().
316 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
317 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
319 @param[in] Address The PCI configuration register to write.
320 @param[in] StartBit The ordinal of the least significant bit in the bit field.
322 @param[in] EndBit The ordinal of the most significant bit in the bit field.
324 @param[in] AndData The value to AND with the PCI configuration register.
325 @param[in] OrData The value to OR with the result of the AND operation.
327 @return The value written back to the PCI configuration register.
332 S3PciBitFieldAndThenOr8 (
341 Reads a 16-bit PCI configuration register, and saves the value in the S3
342 script to be replayed on S3 resume.
344 Reads and returns the 16-bit PCI configuration register specified by Address.
345 This function must guarantee that all PCI read and write operations are
348 If Address > 0x0FFFFFFF, then ASSERT().
349 If Address is not aligned on a 16-bit boundary, then ASSERT().
351 @param[in] Address The address that encodes the PCI Bus, Device, Function and
354 @return The read value from the PCI configuration register.
364 Writes a 16-bit PCI configuration register, and saves the value in the S3
365 script to be replayed on S3 resume.
367 Writes the 16-bit PCI configuration register specified by Address with the
368 value specified by Value. Value is returned. This function must guarantee
369 that all PCI read and write operations are serialized.
371 If Address > 0x0FFFFFFF, then ASSERT().
372 If Address is not aligned on a 16-bit boundary, then ASSERT().
374 @param[in] Address The address that encodes the PCI Bus, Device, Function and
376 @param[in] Value The value to write.
378 @return The value written to the PCI configuration register.
389 Performs a bitwise OR of a 16-bit PCI configuration register with
390 a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.
392 Reads the 16-bit PCI configuration register specified by Address, performs a
393 bitwise OR between the read result and the value specified by
394 OrData, and writes the result to the 16-bit PCI configuration register
395 specified by Address. The value written to the PCI configuration register is
396 returned. This function must guarantee that all PCI read and write operations
399 If Address > 0x0FFFFFFF, then ASSERT().
400 If Address is not aligned on a 16-bit boundary, then ASSERT().
402 @param[in] Address The address that encodes the PCI Bus, Device, Function and
404 @param[in] OrData The value to OR with the PCI configuration register.
406 @return The value written back to the PCI configuration register.
417 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
418 value, and saves the value in the S3 script to be replayed on S3 resume.
420 Reads the 16-bit PCI configuration register specified by Address, performs a
421 bitwise AND between the read result and the value specified by AndData, and
422 writes the result to the 16-bit PCI configuration register specified by
423 Address. The value written to the PCI configuration register is returned.
424 This function must guarantee that all PCI read and write operations are
427 If Address > 0x0FFFFFFF, then ASSERT().
428 If Address is not aligned on a 16-bit boundary, then ASSERT().
430 @param[in] Address The address that encodes the PCI Bus, Device, Function and
432 @param[in] AndData The value to AND with the PCI configuration register.
434 @return The value written back to the PCI configuration register.
445 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
446 value, followed a bitwise OR with another 16-bit value, and saves
447 the value in the S3 script to be replayed on S3 resume.
449 Reads the 16-bit PCI configuration register specified by Address, performs a
450 bitwise AND between the read result and the value specified by AndData,
451 performs a bitwise OR between the result of the AND operation and
452 the value specified by OrData, and writes the result to the 16-bit PCI
453 configuration register specified by Address. The value written to the PCI
454 configuration register is returned. This function must guarantee that all PCI
455 read and write operations are serialized.
457 If Address > 0x0FFFFFFF, then ASSERT().
458 If Address is not aligned on a 16-bit boundary, then ASSERT().
460 @param[in] Address The address that encodes the PCI Bus, Device, Function and
462 @param[in] AndData The value to AND with the PCI configuration register.
463 @param[in] OrData The value to OR with the result of the AND operation.
465 @return The value written back to the PCI configuration register.
477 Reads a bit field of a PCI configuration register, and saves the value in
478 the S3 script to be replayed on S3 resume.
480 Reads the bit field in a 16-bit PCI configuration register. The bit field is
481 specified by the StartBit and the EndBit. The value of the bit field is
484 If Address > 0x0FFFFFFF, then ASSERT().
485 If Address is not aligned on a 16-bit boundary, then ASSERT().
486 If StartBit is greater than 15, then ASSERT().
487 If EndBit is greater than 15, then ASSERT().
488 If EndBit is less than StartBit, then ASSERT().
490 @param[in] Address The PCI configuration register to read.
491 @param[in] StartBit The ordinal of the least significant bit in the bit field.
493 @param[in] EndBit The ordinal of the most significant bit in the bit field.
496 @return The value of the bit field read from the PCI configuration register.
501 S3PciBitFieldRead16 (
508 Writes a bit field to a PCI configuration register, and saves the value in
509 the S3 script to be replayed on S3 resume.
511 Writes Value to the bit field of the PCI configuration register. The bit
512 field is specified by the StartBit and the EndBit. All other bits in the
513 destination PCI configuration register are preserved. The new value of the
514 16-bit register is returned.
516 If Address > 0x0FFFFFFF, then ASSERT().
517 If Address is not aligned on a 16-bit boundary, then ASSERT().
518 If StartBit is greater than 15, then ASSERT().
519 If EndBit is greater than 15, then ASSERT().
520 If EndBit is less than StartBit, then ASSERT().
521 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
523 @param[in] Address The PCI configuration register to write.
524 @param[in] StartBit The ordinal of the least significant bit in the bit field.
526 @param[in] EndBit The ordinal of the most significant bit in the bit field.
528 @param[in] Value New value of the bit field.
530 @return The value written back to the PCI configuration register.
535 S3PciBitFieldWrite16 (
543 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
544 writes the result back to the bit field in the 16-bit port, and saves the value
545 in the S3 script to be replayed on S3 resume.
547 Reads the 16-bit PCI configuration register specified by Address, performs a
548 bitwise OR between the read result and the value specified by
549 OrData, and writes the result to the 16-bit PCI configuration register
550 specified by Address. The value written to the PCI configuration register is
551 returned. This function must guarantee that all PCI read and write operations
552 are serialized. Extra left bits in OrData are stripped.
554 If Address > 0x0FFFFFFF, then ASSERT().
555 If Address is not aligned on a 16-bit boundary, then ASSERT().
556 If StartBit is greater than 15, then ASSERT().
557 If EndBit is greater than 15, then ASSERT().
558 If EndBit is less than StartBit, then ASSERT().
559 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
561 @param[in] Address The PCI configuration register to write.
562 @param[in] StartBit The ordinal of the least significant bit in the bit field.
564 @param[in] EndBit The ordinal of the most significant bit in the bit field.
566 @param[in] OrData The value to OR with the PCI configuration register.
568 @return The value written back to the PCI configuration register.
581 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
582 AND, and writes the result back to the bit field in the 16-bit register and
583 saves the value in the S3 script to be replayed on S3 resume.
585 Reads the 16-bit PCI configuration register specified by Address, performs a
586 bitwise AND between the read result and the value specified by AndData, and
587 writes the result to the 16-bit PCI configuration register specified by
588 Address. The value written to the PCI configuration register is returned.
589 This function must guarantee that all PCI read and write operations are
590 serialized. Extra left bits in AndData are stripped.
592 If Address > 0x0FFFFFFF, then ASSERT().
593 If Address is not aligned on a 16-bit boundary, then ASSERT().
594 If StartBit is greater than 15, then ASSERT().
595 If EndBit is greater than 15, then ASSERT().
596 If EndBit is less than StartBit, then ASSERT().
597 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
599 @param[in] Address The PCI configuration register to write.
600 @param[in] StartBit The ordinal of the least significant bit in the bit field.
602 @param[in] EndBit The ordinal of the most significant bit in the bit field.
604 @param[in] AndData The value to AND with the PCI configuration register.
606 @return The value written back to the PCI configuration register.
619 Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a
620 bitwise OR, and writes the result back to the bit field in the
621 16-bit port, and saves the value in the S3 script to be replayed on S3 resume.
623 Reads the 16-bit PCI configuration register specified by Address, performs a
624 bitwise AND followed by a bitwise OR between the read result and
625 the value specified by AndData, and writes the result to the 16-bit PCI
626 configuration register specified by Address. The value written to the PCI
627 configuration register is returned. This function must guarantee that all PCI
628 read and write operations are serialized. Extra left bits in both AndData and
631 If Address > 0x0FFFFFFF, then ASSERT().
632 If Address is not aligned on a 16-bit boundary, then ASSERT().
633 If StartBit is greater than 15, then ASSERT().
634 If EndBit is greater than 15, then ASSERT().
635 If EndBit is less than StartBit, then ASSERT().
636 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
637 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
639 @param[in] Address The PCI configuration register to write.
640 @param[in] StartBit The ordinal of the least significant bit in the bit field.
642 @param[in] EndBit The ordinal of the most significant bit in the bit field.
644 @param[in] AndData The value to AND with the PCI configuration register.
645 @param[in] OrData The value to OR with the result of the AND operation.
647 @return The value written back to the PCI configuration register.
652 S3PciBitFieldAndThenOr16 (
661 Reads a 32-bit PCI configuration register, and saves the value in the S3
662 script to be replayed on S3 resume.
664 Reads and returns the 32-bit PCI configuration register specified by Address.
665 This function must guarantee that all PCI read and write operations are
668 If Address > 0x0FFFFFFF, then ASSERT().
669 If Address is not aligned on a 32-bit boundary, then ASSERT().
671 @param[in] Address The address that encodes the PCI Bus, Device, Function and
674 @return The read value from the PCI configuration register.
684 Writes a 32-bit PCI configuration register, and saves the value in the S3
685 script to be replayed on S3 resume.
687 Writes the 32-bit PCI configuration register specified by Address with the
688 value specified by Value. Value is returned. This function must guarantee
689 that all PCI read and write operations are serialized.
691 If Address > 0x0FFFFFFF, then ASSERT().
692 If Address is not aligned on a 32-bit boundary, then ASSERT().
694 @param[in] Address The address that encodes the PCI Bus, Device, Function and
696 @param[in] Value The value to write.
698 @return The value written to the PCI configuration register.
709 Performs a bitwise OR of a 32-bit PCI configuration register with
710 a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.
712 Reads the 32-bit PCI configuration register specified by Address, performs a
713 bitwise OR between the read result and the value specified by
714 OrData, and writes the result to the 32-bit PCI configuration register
715 specified by Address. The value written to the PCI configuration register is
716 returned. This function must guarantee that all PCI read and write operations
719 If Address > 0x0FFFFFFF, then ASSERT().
720 If Address is not aligned on a 32-bit boundary, then ASSERT().
722 @param[in] Address The address that encodes the PCI Bus, Device, Function and
724 @param[in] OrData The value to OR with the PCI configuration register.
726 @return The value written back to the PCI configuration register.
737 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
738 value, and saves the value in the S3 script to be replayed on S3 resume.
740 Reads the 32-bit PCI configuration register specified by Address, performs a
741 bitwise AND between the read result and the value specified by AndData, and
742 writes the result to the 32-bit PCI configuration register specified by
743 Address. The value written to the PCI configuration register is returned.
744 This function must guarantee that all PCI read and write operations are
747 If Address > 0x0FFFFFFF, then ASSERT().
748 If Address is not aligned on a 32-bit boundary, then ASSERT().
750 @param[in] Address The address that encodes the PCI Bus, Device, Function and
752 @param[in] AndData The value to AND with the PCI configuration register.
754 @return The value written back to the PCI configuration register.
765 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
766 value, followed a bitwise OR with another 32-bit value, and saves
767 the value in the S3 script to be replayed on S3 resume.
769 Reads the 32-bit PCI configuration register specified by Address, performs a
770 bitwise AND between the read result and the value specified by AndData,
771 performs a bitwise OR between the result of the AND operation and
772 the value specified by OrData, and writes the result to the 32-bit PCI
773 configuration register specified by Address. The value written to the PCI
774 configuration register is returned. This function must guarantee that all PCI
775 read and write operations are serialized.
777 If Address > 0x0FFFFFFF, then ASSERT().
778 If Address is not aligned on a 32-bit boundary, then ASSERT().
780 @param[in] Address The address that encodes the PCI Bus, Device, Function and
782 @param[in] AndData The value to AND with the PCI configuration register.
783 @param[in] OrData The value to OR with the result of the AND operation.
785 @return The value written back to the PCI configuration register.
797 Reads a bit field of a PCI configuration register, and saves the value in
798 the S3 script to be replayed on S3 resume.
800 Reads the bit field in a 32-bit PCI configuration register. The bit field is
801 specified by the StartBit and the EndBit. The value of the bit field is
804 If Address > 0x0FFFFFFF, then ASSERT().
805 If Address is not aligned on a 32-bit boundary, then ASSERT().
806 If StartBit is greater than 31, then ASSERT().
807 If EndBit is greater than 31, then ASSERT().
808 If EndBit is less than StartBit, then ASSERT().
810 @param[in] Address The PCI configuration register to read.
811 @param[in] StartBit The ordinal of the least significant bit in the bit field.
813 @param[in] EndBit The ordinal of the most significant bit in the bit field.
816 @return The value of the bit field read from the PCI configuration register.
821 S3PciBitFieldRead32 (
828 Writes a bit field to a PCI configuration register, and saves the value in
829 the S3 script to be replayed on S3 resume.
831 Writes Value to the bit field of the PCI configuration register. The bit
832 field is specified by the StartBit and the EndBit. All other bits in the
833 destination PCI configuration register are preserved. The new value of the
834 32-bit register is returned.
836 If Address > 0x0FFFFFFF, then ASSERT().
837 If Address is not aligned on a 32-bit boundary, then ASSERT().
838 If StartBit is greater than 31, then ASSERT().
839 If EndBit is greater than 31, then ASSERT().
840 If EndBit is less than StartBit, then ASSERT().
841 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
843 @param[in] Address The PCI configuration register to write.
844 @param[in] StartBit The ordinal of the least significant bit in the bit field.
846 @param[in] EndBit The ordinal of the most significant bit in the bit field.
848 @param[in] Value New value of the bit field.
850 @return The value written back to the PCI configuration register.
855 S3PciBitFieldWrite32 (
863 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
864 writes the result back to the bit field in the 32-bit port, and saves the value
865 in the S3 script to be replayed on S3 resume.
867 Reads the 32-bit PCI configuration register specified by Address, performs a
868 bitwise OR between the read result and the value specified by
869 OrData, and writes the result to the 32-bit PCI configuration register
870 specified by Address. The value written to the PCI configuration register is
871 returned. This function must guarantee that all PCI read and write operations
872 are serialized. Extra left bits in OrData are stripped.
874 If Address > 0x0FFFFFFF, then ASSERT().
875 If Address is not aligned on a 32-bit boundary, then ASSERT().
876 If StartBit is greater than 31, then ASSERT().
877 If EndBit is greater than 31, then ASSERT().
878 If EndBit is less than StartBit, then ASSERT().
879 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
881 @param[in] Address The PCI configuration register to write.
882 @param[in] StartBit The ordinal of the least significant bit in the bit field.
884 @param[in] EndBit The ordinal of the most significant bit in the bit field.
886 @param[in] OrData The value to OR with the PCI configuration register.
888 @return The value written back to the PCI configuration register.
901 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
902 AND, and writes the result back to the bit field in the 32-bit register and
903 saves the value in the S3 script to be replayed on S3 resume.
905 Reads the 32-bit PCI configuration register specified by Address, performs a
906 bitwise AND between the read result and the value specified by AndData, and
907 writes the result to the 32-bit PCI configuration register specified by
908 Address. The value written to the PCI configuration register is returned.
909 This function must guarantee that all PCI read and write operations are
910 serialized. Extra left bits in AndData are stripped.
912 If Address > 0x0FFFFFFF, then ASSERT().
913 If Address is not aligned on a 32-bit boundary, then ASSERT().
914 If StartBit is greater than 31, then ASSERT().
915 If EndBit is greater than 31, then ASSERT().
916 If EndBit is less than StartBit, then ASSERT().
917 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
919 @param[in] Address The PCI configuration register to write.
920 @param[in] StartBit The ordinal of the least significant bit in the bit field.
922 @param[in] EndBit The ordinal of the most significant bit in the bit field.
924 @param[in] AndData The value to AND with the PCI configuration register.
926 @return The value written back to the PCI configuration register.
939 Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a
940 bitwise OR, and writes the result back to the bit field in the
941 32-bit port, and saves the value in the S3 script to be replayed on S3 resume.
943 Reads the 32-bit PCI configuration register specified by Address, performs a
944 bitwise AND followed by a bitwise OR between the read result and
945 the value specified by AndData, and writes the result to the 32-bit PCI
946 configuration register specified by Address. The value written to the PCI
947 configuration register is returned. This function must guarantee that all PCI
948 read and write operations are serialized. Extra left bits in both AndData and
951 If Address > 0x0FFFFFFF, then ASSERT().
952 If Address is not aligned on a 32-bit boundary, then ASSERT().
953 If StartBit is greater than 31, then ASSERT().
954 If EndBit is greater than 31, then ASSERT().
955 If EndBit is less than StartBit, then ASSERT().
956 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
957 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
959 @param[in] Address The PCI configuration register to write.
960 @param[in] StartBit The ordinal of the least significant bit in the bit field.
962 @param[in] EndBit The ordinal of the most significant bit in the bit field.
964 @param[in] AndData The value to AND with the PCI configuration register.
965 @param[in] OrData The value to OR with the result of the AND operation.
967 @return The value written back to the PCI configuration register.
972 S3PciBitFieldAndThenOr32 (
981 Reads a range of PCI configuration registers into a caller supplied buffer,
982 and saves the value in the S3 script to be replayed on S3 resume.
984 Reads the range of PCI configuration registers specified by StartAddress and
985 Size into the buffer specified by Buffer. This function only allows the PCI
986 configuration registers from a single PCI function to be read. Size is
987 returned. When possible 32-bit PCI configuration read cycles are used to read
988 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
989 and 16-bit PCI configuration read cycles may be used at the beginning and the
992 If StartAddress > 0x0FFFFFFF, then ASSERT().
993 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
994 If Size > 0 and Buffer is NULL, then ASSERT().
996 @param[in] StartAddress Starting address that encodes the PCI Bus, Device,
997 Function and Register.
998 @param[in] Size Size in bytes of the transfer.
999 @param[out] Buffer The pointer to a buffer receiving the data read.
1007 IN UINTN StartAddress
,
1013 Copies the data in a caller supplied buffer to a specified range of PCI
1014 configuration space, and saves the value in the S3 script to be replayed on S3
1017 Writes the range of PCI configuration registers specified by StartAddress and
1018 Size from the buffer specified by Buffer. This function only allows the PCI
1019 configuration registers from a single PCI function to be written. Size is
1020 returned. When possible 32-bit PCI configuration write cycles are used to
1021 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1022 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1023 and the end of the range.
1025 If StartAddress > 0x0FFFFFFF, then ASSERT().
1026 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1027 If Size > 0 and Buffer is NULL, then ASSERT().
1029 @param[in] StartAddress Starting address that encodes the PCI Bus, Device,
1030 Function and Register.
1031 @param[in] Size Size in bytes of the transfer.
1032 @param[in] Buffer The pointer to a buffer containing the data to write.
1040 IN UINTN StartAddress
,