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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Library/S3PciLib.h
2 The PCI configuration Library Services that carry out PCI configuration and enable
3 the PCI operations to be replayed during an S3 resume. This library class
4 maps directly on top of the PciLib class.
6 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions
10 of the BSD License which accompanies this distribution. The
11 full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __S3_PCI_LIB_H__
20 #define __S3_PCI_LIB_H__
23 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
24 address that can be passed to the S3 PCI Library functions.
26 @param Bus The PCI Bus number. Range 0..255.
27 @param Device The PCI Device number. Range 0..31.
28 @param Function The PCI Function number. Range 0..7.
29 @param Register The PCI Register number. Range 0..255 for PCI. Range 0..4095
32 @return The encoded PCI address.
35 #define S3_PCI_LIB_ADDRESS(Bus,Device,Function,Register) \
36 (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
40 Reads and returns the 8-bit PCI configuration register specified by Address,
41 and saves the value in the S3 script to be replayed on S3 resume.
42 This function must guarantee that all PCI read and write operations are
45 If Address > 0x0FFFFFFF, then ASSERT().
47 @param[in] Address The address that encodes the PCI Bus, Device, Function and
50 @return The value read from the PCI configuration register.
60 Writes an 8-bit PCI configuration register, and saves the value in the S3
61 script to be replayed on S3 resume.
63 Writes the 8-bit PCI configuration register specified by Address with the
64 value specified by Value. Value is returned. This function must guarantee
65 that all PCI read and write operations are serialized.
67 If Address > 0x0FFFFFFF, then ASSERT().
69 @param[in] Address The address that encodes the PCI Bus, Device, Function and
71 @param[in] Value The value to write.
73 @return The value written to the PCI configuration register.
84 Performs a bitwise OR of an 8-bit PCI configuration register with
85 an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.
87 Reads the 8-bit PCI configuration register specified by Address, performs a
88 bitwise OR between the read result and the value specified by
89 OrData, and writes the result to the 8-bit PCI configuration register
90 specified by Address. The value written to the PCI configuration register is
91 returned. This function must guarantee that all PCI read and write operations
94 If Address > 0x0FFFFFFF, then ASSERT().
96 @param[in] Address The address that encodes the PCI Bus, Device, Function and
98 @param[in] OrData The value to OR with the PCI configuration register.
100 @return The value written back to the PCI configuration register.
111 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
112 value, and saves the value in the S3 script to be replayed on S3 resume.
114 Reads the 8-bit PCI configuration register specified by Address, performs a
115 bitwise AND between the read result and the value specified by AndData, and
116 writes the result to the 8-bit PCI configuration register specified by
117 Address. The value written to the PCI configuration register is returned.
118 This function must guarantee that all PCI read and write operations are
121 If Address > 0x0FFFFFFF, then ASSERT().
123 @param[in] Address The address that encodes the PCI Bus, Device, Function and
125 @param[in] AndData The value to AND with the PCI configuration register.
127 @return The value written back to the PCI configuration register.
138 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
139 value, followed a bitwise OR with another 8-bit value, and saves
140 the value in the S3 script to be replayed on S3 resume.
142 Reads the 8-bit PCI configuration register specified by Address, performs a
143 bitwise AND between the read result and the value specified by AndData,
144 performs a bitwise OR between the result of the AND operation and
145 the value specified by OrData, and writes the result to the 8-bit PCI
146 configuration register specified by Address. The value written to the PCI
147 configuration register is returned. This function must guarantee that all PCI
148 read and write operations are serialized.
150 If Address > 0x0FFFFFFF, then ASSERT().
152 @param[in] Address The address that encodes the PCI Bus, Device, Function and
154 @param[in] AndData The value to AND with the PCI configuration register.
155 @param[in] OrData The value to OR with the result of the AND operation.
157 @return The value written back to the PCI configuration register.
169 Reads a bit field of a PCI configuration register, and saves the value in
170 the S3 script to be replayed on S3 resume.
172 Reads the bit field in an 8-bit PCI configuration register. The bit field is
173 specified by the StartBit and the EndBit. The value of the bit field is
176 If Address > 0x0FFFFFFF, then ASSERT().
177 If StartBit is greater than 7, then ASSERT().
178 If EndBit is greater than 7, then ASSERT().
179 If EndBit is less than StartBit, then ASSERT().
181 @param[in] Address The PCI configuration register to read.
182 @param[in] StartBit The ordinal of the least significant bit in the bit field.
184 @param[in] EndBit The ordinal of the most significant bit in the bit field.
187 @return The value of the bit field read from the PCI configuration register.
199 Writes a bit field to a PCI configuration register, and saves the value in
200 the S3 script to be replayed on S3 resume.
202 Writes Value to the bit field of the PCI configuration register. The bit
203 field is specified by the StartBit and the EndBit. All other bits in the
204 destination PCI configuration register are preserved. The new value of the
205 8-bit register is returned.
207 If Address > 0x0FFFFFFF, then ASSERT().
208 If StartBit is greater than 7, then ASSERT().
209 If EndBit is greater than 7, then ASSERT().
210 If EndBit is less than StartBit, then ASSERT().
212 @param[in] Address The PCI configuration register to write.
213 @param[in] StartBit The ordinal of the least significant bit in the bit field.
215 @param[in] EndBit The ordinal of the most significant bit in the bit field.
217 @param[in] Value New value of the bit field.
219 @return The value written back to the PCI configuration register.
224 S3PciBitFieldWrite8 (
232 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
233 writes the result back to the bit field in the 8-bit port, and saves the value
234 in the S3 script to be replayed on S3 resume.
236 Reads the 8-bit PCI configuration register specified by Address, performs a
237 bitwise OR between the read result and the value specified by
238 OrData, and writes the result to the 8-bit PCI configuration register
239 specified by Address. The value written to the PCI configuration register is
240 returned. This function must guarantee that all PCI read and write operations
241 are serialized. Extra left bits in OrData are stripped.
243 If Address > 0x0FFFFFFF, then ASSERT().
244 If StartBit is greater than 7, then ASSERT().
245 If EndBit is greater than 7, then ASSERT().
246 If EndBit is less than StartBit, then ASSERT().
248 @param[in] Address The PCI configuration register to write.
249 @param[in] StartBit The ordinal of the least significant bit in the bit field.
251 @param[in] EndBit The ordinal of the most significant bit in the bit field.
253 @param[in] OrData The value to OR with the PCI configuration register.
255 @return The value written back to the PCI configuration register.
268 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
269 AND, and writes the result back to the bit field in the 8-bit register and
270 saves the value in the S3 script to be replayed on S3 resume.
272 Reads the 8-bit PCI configuration register specified by Address, performs a
273 bitwise AND between the read result and the value specified by AndData, and
274 writes the result to the 8-bit PCI configuration register specified by
275 Address. The value written to the PCI configuration register is returned.
276 This function must guarantee that all PCI read and write operations are
277 serialized. Extra left bits in AndData are stripped.
279 If Address > 0x0FFFFFFF, then ASSERT().
280 If StartBit is greater than 7, then ASSERT().
281 If EndBit is greater than 7, then ASSERT().
282 If EndBit is less than StartBit, then ASSERT().
284 @param[in] Address The PCI configuration register to write.
285 @param[in] StartBit The ordinal of the least significant bit in the bit field.
287 @param[in] EndBit The ordinal of the most significant bit in the bit field.
289 @param[in] AndData The value to AND with the PCI configuration register.
291 @return The value written back to the PCI configuration register.
304 Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a
305 bitwise OR, and writes the result back to the bit field in the
306 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.
308 Reads the 8-bit PCI configuration register specified by Address, performs a
309 bitwise AND followed by a bitwise OR between the read result and
310 the value specified by AndData, and writes the result to the 8-bit PCI
311 configuration register specified by Address. The value written to the PCI
312 configuration register is returned. This function must guarantee that all PCI
313 read and write operations are serialized. Extra left bits in both AndData and
316 If Address > 0x0FFFFFFF, then ASSERT().
317 If StartBit is greater than 7, then ASSERT().
318 If EndBit is greater than 7, then ASSERT().
319 If EndBit is less than StartBit, then ASSERT().
321 @param[in] Address The PCI configuration register to write.
322 @param[in] StartBit The ordinal of the least significant bit in the bit field.
324 @param[in] EndBit The ordinal of the most significant bit in the bit field.
326 @param[in] AndData The value to AND with the PCI configuration register.
327 @param[in] OrData The value to OR with the result of the AND operation.
329 @return The value written back to the PCI configuration register.
334 S3PciBitFieldAndThenOr8 (
343 Reads a 16-bit PCI configuration register, and saves the value in the S3
344 script to be replayed on S3 resume.
346 Reads and returns the 16-bit PCI configuration register specified by Address.
347 This function must guarantee that all PCI read and write operations are
350 If Address > 0x0FFFFFFF, then ASSERT().
351 If Address is not aligned on a 16-bit boundary, then ASSERT().
353 @param[in] Address The address that encodes the PCI Bus, Device, Function and
356 @return The read value from the PCI configuration register.
366 Writes a 16-bit PCI configuration register, and saves the value in the S3
367 script to be replayed on S3 resume.
369 Writes the 16-bit PCI configuration register specified by Address with the
370 value specified by Value. Value is returned. This function must guarantee
371 that all PCI read and write operations are serialized.
373 If Address > 0x0FFFFFFF, then ASSERT().
374 If Address is not aligned on a 16-bit boundary, then ASSERT().
376 @param[in] Address The address that encodes the PCI Bus, Device, Function and
378 @param[in] Value The value to write.
380 @return The value written to the PCI configuration register.
391 Performs a bitwise OR of a 16-bit PCI configuration register with
392 a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.
394 Reads the 16-bit PCI configuration register specified by Address, performs a
395 bitwise OR between the read result and the value specified by
396 OrData, and writes the result to the 16-bit PCI configuration register
397 specified by Address. The value written to the PCI configuration register is
398 returned. This function must guarantee that all PCI read and write operations
401 If Address > 0x0FFFFFFF, then ASSERT().
402 If Address is not aligned on a 16-bit boundary, then ASSERT().
404 @param[in] Address The address that encodes the PCI Bus, Device, Function and
406 @param[in] OrData The value to OR with the PCI configuration register.
408 @return The value written back to the PCI configuration register.
419 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
420 value, and saves the value in the S3 script to be replayed on S3 resume.
422 Reads the 16-bit PCI configuration register specified by Address, performs a
423 bitwise AND between the read result and the value specified by AndData, and
424 writes the result to the 16-bit PCI configuration register specified by
425 Address. The value written to the PCI configuration register is returned.
426 This function must guarantee that all PCI read and write operations are
429 If Address > 0x0FFFFFFF, then ASSERT().
430 If Address is not aligned on a 16-bit boundary, then ASSERT().
432 @param[in] Address The address that encodes the PCI Bus, Device, Function and
434 @param[in] AndData The value to AND with the PCI configuration register.
436 @return The value written back to the PCI configuration register.
447 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
448 value, followed a bitwise OR with another 16-bit value, and saves
449 the value in the S3 script to be replayed on S3 resume.
451 Reads the 16-bit PCI configuration register specified by Address, performs a
452 bitwise AND between the read result and the value specified by AndData,
453 performs a bitwise OR between the result of the AND operation and
454 the value specified by OrData, and writes the result to the 16-bit PCI
455 configuration register specified by Address. The value written to the PCI
456 configuration register is returned. This function must guarantee that all PCI
457 read and write operations are serialized.
459 If Address > 0x0FFFFFFF, then ASSERT().
460 If Address is not aligned on a 16-bit boundary, then ASSERT().
462 @param[in] Address The address that encodes the PCI Bus, Device, Function and
464 @param[in] AndData The value to AND with the PCI configuration register.
465 @param[in] OrData The value to OR with the result of the AND operation.
467 @return The value written back to the PCI configuration register.
479 Reads a bit field of a PCI configuration register, and saves the value in
480 the S3 script to be replayed on S3 resume.
482 Reads the bit field in a 16-bit PCI configuration register. The bit field is
483 specified by the StartBit and the EndBit. The value of the bit field is
486 If Address > 0x0FFFFFFF, then ASSERT().
487 If Address is not aligned on a 16-bit boundary, then ASSERT().
488 If StartBit is greater than 15, then ASSERT().
489 If EndBit is greater than 15, then ASSERT().
490 If EndBit is less than StartBit, then ASSERT().
492 @param[in] Address The PCI configuration register to read.
493 @param[in] StartBit The ordinal of the least significant bit in the bit field.
495 @param[in] EndBit The ordinal of the most significant bit in the bit field.
498 @return The value of the bit field read from the PCI configuration register.
503 S3PciBitFieldRead16 (
510 Writes a bit field to a PCI configuration register, and saves the value in
511 the S3 script to be replayed on S3 resume.
513 Writes Value to the bit field of the PCI configuration register. The bit
514 field is specified by the StartBit and the EndBit. All other bits in the
515 destination PCI configuration register are preserved. The new value of the
516 16-bit register is returned.
518 If Address > 0x0FFFFFFF, then ASSERT().
519 If Address is not aligned on a 16-bit boundary, then ASSERT().
520 If StartBit is greater than 15, then ASSERT().
521 If EndBit is greater than 15, then ASSERT().
522 If EndBit is less than StartBit, then ASSERT().
524 @param[in] Address The PCI configuration register to write.
525 @param[in] StartBit The ordinal of the least significant bit in the bit field.
527 @param[in] EndBit The ordinal of the most significant bit in the bit field.
529 @param[in] Value New value of the bit field.
531 @return The value written back to the PCI configuration register.
536 S3PciBitFieldWrite16 (
544 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
545 writes the result back to the bit field in the 16-bit port, and saves the value
546 in the S3 script to be replayed on S3 resume.
548 Reads the 16-bit PCI configuration register specified by Address, performs a
549 bitwise OR between the read result and the value specified by
550 OrData, and writes the result to the 16-bit PCI configuration register
551 specified by Address. The value written to the PCI configuration register is
552 returned. This function must guarantee that all PCI read and write operations
553 are serialized. Extra left bits in OrData are stripped.
555 If Address > 0x0FFFFFFF, then ASSERT().
556 If Address is not aligned on a 16-bit boundary, then ASSERT().
557 If StartBit is greater than 15, then ASSERT().
558 If EndBit is greater than 15, then ASSERT().
559 If EndBit is less than StartBit, then ASSERT().
561 @param[in] Address The PCI configuration register to write.
562 @param[in] StartBit The ordinal of the least significant bit in the bit field.
564 @param[in] EndBit The ordinal of the most significant bit in the bit field.
566 @param[in] OrData The value to OR with the PCI configuration register.
568 @return The value written back to the PCI configuration register.
581 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
582 AND, and writes the result back to the bit field in the 16-bit register and
583 saves the value in the S3 script to be replayed on S3 resume.
585 Reads the 16-bit PCI configuration register specified by Address, performs a
586 bitwise AND between the read result and the value specified by AndData, and
587 writes the result to the 16-bit PCI configuration register specified by
588 Address. The value written to the PCI configuration register is returned.
589 This function must guarantee that all PCI read and write operations are
590 serialized. Extra left bits in AndData are stripped.
592 If Address > 0x0FFFFFFF, then ASSERT().
593 If Address is not aligned on a 16-bit boundary, then ASSERT().
594 If StartBit is greater than 15, then ASSERT().
595 If EndBit is greater than 15, then ASSERT().
596 If EndBit is less than StartBit, then ASSERT().
598 @param[in] Address The PCI configuration register to write.
599 @param[in] StartBit The ordinal of the least significant bit in the bit field.
601 @param[in] EndBit The ordinal of the most significant bit in the bit field.
603 @param[in] AndData The value to AND with the PCI configuration register.
605 @return The value written back to the PCI configuration register.
618 Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a
619 bitwise OR, and writes the result back to the bit field in the
620 16-bit port, and saves the value in the S3 script to be replayed on S3 resume.
622 Reads the 16-bit PCI configuration register specified by Address, performs a
623 bitwise AND followed by a bitwise OR between the read result and
624 the value specified by AndData, and writes the result to the 16-bit PCI
625 configuration register specified by Address. The value written to the PCI
626 configuration register is returned. This function must guarantee that all PCI
627 read and write operations are serialized. Extra left bits in both AndData and
630 If Address > 0x0FFFFFFF, then ASSERT().
631 If Address is not aligned on a 16-bit boundary, then ASSERT().
632 If StartBit is greater than 15, then ASSERT().
633 If EndBit is greater than 15, then ASSERT().
634 If EndBit is less than StartBit, then ASSERT().
636 @param[in] Address The PCI configuration register to write.
637 @param[in] StartBit The ordinal of the least significant bit in the bit field.
639 @param[in] EndBit The ordinal of the most significant bit in the bit field.
641 @param[in] AndData The value to AND with the PCI configuration register.
642 @param[in] OrData The value to OR with the result of the AND operation.
644 @return The value written back to the PCI configuration register.
649 S3PciBitFieldAndThenOr16 (
658 Reads a 32-bit PCI configuration register, and saves the value in the S3
659 script to be replayed on S3 resume.
661 Reads and returns the 32-bit PCI configuration register specified by Address.
662 This function must guarantee that all PCI read and write operations are
665 If Address > 0x0FFFFFFF, then ASSERT().
666 If Address is not aligned on a 32-bit boundary, then ASSERT().
668 @param[in] Address The address that encodes the PCI Bus, Device, Function and
671 @return The read value from the PCI configuration register.
681 Writes a 32-bit PCI configuration register, and saves the value in the S3
682 script to be replayed on S3 resume.
684 Writes the 32-bit PCI configuration register specified by Address with the
685 value specified by Value. Value is returned. This function must guarantee
686 that all PCI read and write operations are serialized.
688 If Address > 0x0FFFFFFF, then ASSERT().
689 If Address is not aligned on a 32-bit boundary, then ASSERT().
691 @param[in] Address The address that encodes the PCI Bus, Device, Function and
693 @param[in] Value The value to write.
695 @return The value written to the PCI configuration register.
706 Performs a bitwise OR of a 32-bit PCI configuration register with
707 a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.
709 Reads the 32-bit PCI configuration register specified by Address, performs a
710 bitwise OR between the read result and the value specified by
711 OrData, and writes the result to the 32-bit PCI configuration register
712 specified by Address. The value written to the PCI configuration register is
713 returned. This function must guarantee that all PCI read and write operations
716 If Address > 0x0FFFFFFF, then ASSERT().
717 If Address is not aligned on a 32-bit boundary, then ASSERT().
719 @param[in] Address The address that encodes the PCI Bus, Device, Function and
721 @param[in] OrData The value to OR with the PCI configuration register.
723 @return The value written back to the PCI configuration register.
734 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
735 value, and saves the value in the S3 script to be replayed on S3 resume.
737 Reads the 32-bit PCI configuration register specified by Address, performs a
738 bitwise AND between the read result and the value specified by AndData, and
739 writes the result to the 32-bit PCI configuration register specified by
740 Address. The value written to the PCI configuration register is returned.
741 This function must guarantee that all PCI read and write operations are
744 If Address > 0x0FFFFFFF, then ASSERT().
745 If Address is not aligned on a 32-bit boundary, then ASSERT().
747 @param[in] Address The address that encodes the PCI Bus, Device, Function and
749 @param[in] AndData The value to AND with the PCI configuration register.
751 @return The value written back to the PCI configuration register.
762 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
763 value, followed a bitwise OR with another 32-bit value, and saves
764 the value in the S3 script to be replayed on S3 resume.
766 Reads the 32-bit PCI configuration register specified by Address, performs a
767 bitwise AND between the read result and the value specified by AndData,
768 performs a bitwise OR between the result of the AND operation and
769 the value specified by OrData, and writes the result to the 32-bit PCI
770 configuration register specified by Address. The value written to the PCI
771 configuration register is returned. This function must guarantee that all PCI
772 read and write operations are serialized.
774 If Address > 0x0FFFFFFF, then ASSERT().
775 If Address is not aligned on a 32-bit boundary, then ASSERT().
777 @param[in] Address The address that encodes the PCI Bus, Device, Function and
779 @param[in] AndData The value to AND with the PCI configuration register.
780 @param[in] OrData The value to OR with the result of the AND operation.
782 @return The value written back to the PCI configuration register.
794 Reads a bit field of a PCI configuration register, and saves the value in
795 the S3 script to be replayed on S3 resume.
797 Reads the bit field in a 32-bit PCI configuration register. The bit field is
798 specified by the StartBit and the EndBit. The value of the bit field is
801 If Address > 0x0FFFFFFF, then ASSERT().
802 If Address is not aligned on a 32-bit boundary, then ASSERT().
803 If StartBit is greater than 31, then ASSERT().
804 If EndBit is greater than 31, then ASSERT().
805 If EndBit is less than StartBit, then ASSERT().
807 @param[in] Address The PCI configuration register to read.
808 @param[in] StartBit The ordinal of the least significant bit in the bit field.
810 @param[in] EndBit The ordinal of the most significant bit in the bit field.
813 @return The value of the bit field read from the PCI configuration register.
818 S3PciBitFieldRead32 (
825 Writes a bit field to a PCI configuration register, and saves the value in
826 the S3 script to be replayed on S3 resume.
828 Writes Value to the bit field of the PCI configuration register. The bit
829 field is specified by the StartBit and the EndBit. All other bits in the
830 destination PCI configuration register are preserved. The new value of the
831 32-bit register is returned.
833 If Address > 0x0FFFFFFF, then ASSERT().
834 If Address is not aligned on a 32-bit boundary, then ASSERT().
835 If StartBit is greater than 31, then ASSERT().
836 If EndBit is greater than 31, then ASSERT().
837 If EndBit is less than StartBit, then ASSERT().
839 @param[in] Address The PCI configuration register to write.
840 @param[in] StartBit The ordinal of the least significant bit in the bit field.
842 @param[in] EndBit The ordinal of the most significant bit in the bit field.
844 @param[in] Value New value of the bit field.
846 @return The value written back to the PCI configuration register.
851 S3PciBitFieldWrite32 (
859 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
860 writes the result back to the bit field in the 32-bit port, and saves the value
861 in the S3 script to be replayed on S3 resume.
863 Reads the 32-bit PCI configuration register specified by Address, performs a
864 bitwise OR between the read result and the value specified by
865 OrData, and writes the result to the 32-bit PCI configuration register
866 specified by Address. The value written to the PCI configuration register is
867 returned. This function must guarantee that all PCI read and write operations
868 are serialized. Extra left bits in OrData are stripped.
870 If Address > 0x0FFFFFFF, then ASSERT().
871 If Address is not aligned on a 32-bit boundary, then ASSERT().
872 If StartBit is greater than 31, then ASSERT().
873 If EndBit is greater than 31, then ASSERT().
874 If EndBit is less than StartBit, then ASSERT().
876 @param[in] Address The PCI configuration register to write.
877 @param[in] StartBit The ordinal of the least significant bit in the bit field.
879 @param[in] EndBit The ordinal of the most significant bit in the bit field.
881 @param[in] OrData The value to OR with the PCI configuration register.
883 @return The value written back to the PCI configuration register.
896 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
897 AND, and writes the result back to the bit field in the 32-bit register and
898 saves the value in the S3 script to be replayed on S3 resume.
900 Reads the 32-bit PCI configuration register specified by Address, performs a
901 bitwise AND between the read result and the value specified by AndData, and
902 writes the result to the 32-bit PCI configuration register specified by
903 Address. The value written to the PCI configuration register is returned.
904 This function must guarantee that all PCI read and write operations are
905 serialized. Extra left bits in AndData are stripped.
907 If Address > 0x0FFFFFFF, then ASSERT().
908 If Address is not aligned on a 32-bit boundary, then ASSERT().
909 If StartBit is greater than 31, then ASSERT().
910 If EndBit is greater than 31, then ASSERT().
911 If EndBit is less than StartBit, then ASSERT().
913 @param[in] Address The PCI configuration register to write.
914 @param[in] StartBit The ordinal of the least significant bit in the bit field.
916 @param[in] EndBit The ordinal of the most significant bit in the bit field.
918 @param[in] AndData The value to AND with the PCI configuration register.
920 @return The value written back to the PCI configuration register.
933 Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a
934 bitwise OR, and writes the result back to the bit field in the
935 32-bit port, and saves the value in the S3 script to be replayed on S3 resume.
937 Reads the 32-bit PCI configuration register specified by Address, performs a
938 bitwise AND followed by a bitwise OR between the read result and
939 the value specified by AndData, and writes the result to the 32-bit PCI
940 configuration register specified by Address. The value written to the PCI
941 configuration register is returned. This function must guarantee that all PCI
942 read and write operations are serialized. Extra left bits in both AndData and
945 If Address > 0x0FFFFFFF, then ASSERT().
946 If Address is not aligned on a 32-bit boundary, then ASSERT().
947 If StartBit is greater than 31, then ASSERT().
948 If EndBit is greater than 31, then ASSERT().
949 If EndBit is less than StartBit, then ASSERT().
951 @param[in] Address The PCI configuration register to write.
952 @param[in] StartBit The ordinal of the least significant bit in the bit field.
954 @param[in] EndBit The ordinal of the most significant bit in the bit field.
956 @param[in] AndData The value to AND with the PCI configuration register.
957 @param[in] OrData The value to OR with the result of the AND operation.
959 @return The value written back to the PCI configuration register.
964 S3PciBitFieldAndThenOr32 (
973 Reads a range of PCI configuration registers into a caller supplied buffer,
974 and saves the value in the S3 script to be replayed on S3 resume.
976 Reads the range of PCI configuration registers specified by StartAddress and
977 Size into the buffer specified by Buffer. This function only allows the PCI
978 configuration registers from a single PCI function to be read. Size is
979 returned. When possible 32-bit PCI configuration read cycles are used to read
980 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
981 and 16-bit PCI configuration read cycles may be used at the beginning and the
984 If StartAddress > 0x0FFFFFFF, then ASSERT().
985 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
986 If Size > 0 and Buffer is NULL, then ASSERT().
988 @param[in] StartAddress Starting address that encodes the PCI Bus, Device,
989 Function and Register.
990 @param[in] Size Size in bytes of the transfer.
991 @param[out] Buffer The pointer to a buffer receiving the data read.
999 IN UINTN StartAddress
,
1005 Copies the data in a caller supplied buffer to a specified range of PCI
1006 configuration space, and saves the value in the S3 script to be replayed on S3
1009 Writes the range of PCI configuration registers specified by StartAddress and
1010 Size from the buffer specified by Buffer. This function only allows the PCI
1011 configuration registers from a single PCI function to be written. Size is
1012 returned. When possible 32-bit PCI configuration write cycles are used to
1013 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1014 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1015 and the end of the range.
1017 If StartAddress > 0x0FFFFFFF, then ASSERT().
1018 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1019 If Size > 0 and Buffer is NULL, then ASSERT().
1021 @param[in] StartAddress Starting address that encodes the PCI Bus, Device,
1022 Function and Register.
1023 @param[in] Size Size in bytes of the transfer.
1024 @param[in] Buffer The pointer to a buffer containing the data to write.
1032 IN UINTN StartAddress
,