MdePkg/Include/Ppi/PciCfg2.h

   1 /** @file
   2   This file declares PciCfg2 PPI.
   3
   4   This ppi Provides platform or chipset-specific access to
   5   the PCI configuration space for a specific PCI segment.
   6
   7   Copyright (c) 2006 - 2009, Intel Corporation
   8   All rights reserved. This program and the accompanying materials
   9   are licensed and made available under the terms and conditions of the BSD License
  10   which accompanies this distribution.  The full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16   @par Revision Reference:
  17   This PPI is introduced in PI Version 1.0.
  18
  19 **/
  20
  21 #ifndef __PEI_PCI_CFG2_H__
  22 #define __PEI_PCI_CFG2_H__
  23
  24 #define EFI_PEI_PCI_CFG2_PPI_GUID \
  25   { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
  26
  27
  28 typedef struct _EFI_PEI_PCI_CFG2_PPI   EFI_PEI_PCI_CFG2_PPI;
  29
  30 #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
  31   (((bus) << 24) | \
  32   ((dev) << 16) | \
  33   ((func) << 8) | \
  34   ((reg) < 256 ? (reg) : ((UINT64)(reg) << 32)));
  35
  36 ///
  37 /// EFI_PEI_PCI_CFG_PPI_WIDTH
  38 ///
  39 typedef enum {
  40   ///
  41   ///  8-bit access
  42   ///
  43   EfiPeiPciCfgWidthUint8  = 0,
  44   ///
  45   /// 16-bit access
  46   ///
  47   EfiPeiPciCfgWidthUint16 = 1,
  48   ///
  49   /// 32-bit access
  50   ///
  51   EfiPeiPciCfgWidthUint32 = 2,
  52   ///
  53   /// 64-bit access
  54   ///
  55   EfiPeiPciCfgWidthUint64 = 3,
  56   EfiPeiPciCfgWidthMaximum
  57 } EFI_PEI_PCI_CFG_PPI_WIDTH;
  58
  59 ///
  60 /// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
  61 ///
  62 typedef struct {
  63   ///
  64   /// 8-bit register offset within the PCI configuration space for a given device's function
  65   /// space.
  66   ///
  67   UINT8   Register;
  68   ///
  69   /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a
  70   /// given device.
  71   ///
  72   UINT8   Function;
  73   ///
  74   /// Only the 5 least-significant bits are used to encode one of 32 possible devices.
  75   ///
  76   UINT8   Device;
  77   ///
  78   /// 8-bit value to encode between 0 and 255 buses.
  79   ///
  80   UINT8   Bus;
  81   ///
  82   /// Register number in PCI configuration space. If this field is zero, then Register is used
  83   /// for the register number. If this field is non-zero, then Register is ignored and this field
  84   /// is used for the register number.
  85   ///
  86   UINT32  ExtendedRegister;
  87 } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
  88
  89 /**
  90   Reads from or write to a given location in the PCI configuration space.
  91
  92   @param  PeiServices     An indirect pointer to the PEI Services Table published by the PEI Foundation.
  93
  94   @param  This            Pointer to local data for the interface.
  95
  96   @param  Width           The width of the access. Enumerated in bytes.
  97                           See EFI_PEI_PCI_CFG_PPI_WIDTH above.
  98
  99   @param  Address         The physical address of the access. The format of
 100                           the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
 101
 102   @param  Buffer          A pointer to the buffer of data..
 103
 104
 105   @retval EFI_SUCCESS           The function completed successfully.
 106
 107   @retval EFI_DEVICE_ERROR      There was a problem with the transaction.
 108
 109   @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting the operation at this
 110                                 time.
 111
 112 **/
 113 typedef
 114 EFI_STATUS
 115 (EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO)(
 116   IN CONST  EFI_PEI_SERVICES          **PeiServices,
 117   IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,
 118   IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
 119   IN        UINT64                    Address,
 120   IN OUT    VOID                      *Buffer
 121 );
 122
 123
 124 /**
 125   Performs a read-modify-write operation on the contents
 126   from a given location in the PCI configuration space.
 127
 128   @param  PeiServices     An indirect pointer to the PEI Services Table
 129                           published by the PEI Foundation.
 130
 131   @param  This            Pointer to local data for the interface.
 132
 133   @param  Width           The width of the access. Enumerated in bytes. Type
 134                           EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
 135
 136   @param  Address         The physical address of the access.
 137
 138   @param  SetBits         Points to value to bitwise-OR with the read configuration value.
 139
 140                           The size of the value is determined by Width.
 141
 142   @param  ClearBits       Points to the value to negate and bitwise-AND with the read configuration value.
 143                           The size of the value is determined by Width.
 144
 145
 146   @retval EFI_SUCCESS           The function completed successfully.
 147
 148   @retval EFI_DEVICE_ERROR      There was a problem with the transaction.
 149
 150   @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting
 151                                 the operation at this time.
 152
 153 **/
 154 typedef
 155 EFI_STATUS
 156 (EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW)(
 157   IN CONST  EFI_PEI_SERVICES          **PeiServices,
 158   IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,
 159   IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
 160   IN        UINT64                    Address,
 161   IN        VOID                      *SetBits,
 162   IN        VOID                      *ClearBits
 163 );
 164
 165 ///
 166 /// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
 167 /// controllers behind a PCI root bridge controller.
 168 ///
 169 struct _EFI_PEI_PCI_CFG2_PPI {
 170   EFI_PEI_PCI_CFG2_PPI_IO  Read;
 171   EFI_PEI_PCI_CFG2_PPI_IO  Write;
 172   EFI_PEI_PCI_CFG2_PPI_RW  Modify;
 173   ///
 174   /// The PCI bus segment which the specified functions will access.
 175   ///
 176   UINT16                  Segment;
 177 };
 178
 179
 180 extern EFI_GUID gEfiPciCfg2PpiGuid;
 181
 182 #endif