2 This file declares PciCfg PPI used to access PCI configuration space in PEI
4 Copyright (c) 2006 - 2007, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 @par Revision Reference:
14 This PPI is defined in PI
19 #ifndef __PEI_PCI_CFG2_H__
20 #define __PEI_PCI_CFG2_H__
23 #define EFI_PEI_PCI_CFG2_PPI_GUID \
24 { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
27 typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI
;
29 #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
33 ((reg) < 256 ? (reg) : ((UINT64) (reg) << 32)));
36 // EFI_PEI_PCI_CFG_PPI_WIDTH
39 EfiPeiPciCfgWidthUint8
= 0,
40 EfiPeiPciCfgWidthUint16
= 1,
41 EfiPeiPciCfgWidthUint32
= 2,
42 EfiPeiPciCfgWidthUint64
= 3,
43 EfiPeiPciCfgWidthMaximum
44 } EFI_PEI_PCI_CFG_PPI_WIDTH
;
47 // EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
54 UINT32 ExtendedRegister
;
55 } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
;
58 Reads from or write to a given location in the PCI configuration space.
60 @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
62 @param This Pointer to local data for the interface.
64 @param Width The width of the access. Enumerated in bytes.
65 See EFI_PEI_PCI_CFG_PPI_WIDTH above.
67 @param Address The physical address of the access. The format of
68 the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
70 @param Buffer A pointer to the buffer of data..
73 @retval EFI_SUCCESS The function completed successfully.
75 @retval EFI_DEVICE_ERROR There was a problem with the transaction.
77 @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this
83 (EFIAPI
*EFI_PEI_PCI_CFG2_PPI_IO
) (
84 IN CONST EFI_PEI_SERVICES
**PeiServices
,
85 IN CONST EFI_PEI_PCI_CFG2_PPI
*This
,
86 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
93 PCI read-modify-write operation.
95 @param PeiServices An indirect pointer to the PEI Services Table
96 published by the PEI Foundation.
98 @param This Pointer to local data for the interface.
100 @param Width The width of the access. Enumerated in bytes. Type
101 EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
103 @param Address The physical address of the access.
105 @param SetBits Points to value to bitwise-OR with the read configuration value.
107 The size of the value is determined by Width.
109 @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.
110 The size of the value is determined by Width.
113 @retval EFI_SUCCESS The function completed successfully.
115 @retval EFI_DEVICE_ERROR There was a problem with the transaction.
117 @retval EFI_DEVICE_NOT_READY The device is not capable of supporting
118 the operation at this time.
123 (EFIAPI
*EFI_PEI_PCI_CFG2_PPI_RW
) (
124 IN CONST EFI_PEI_SERVICES
**PeiServices
,
125 IN CONST EFI_PEI_PCI_CFG2_PPI
*This
,
126 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
128 IN CONST VOID
*SetBits
,
129 IN CONST VOID
*ClearBits
133 @par Ppi Description:
134 The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
135 controllers behind a PCI root bridge controller.
137 @param Read PCI read services. See the Read() function description.
139 @param Write PCI write services. See the Write() function description.
141 @param Modify PCI read-modify-write services. See the Modify() function description.
143 @param Segment The PCI bus segment which the specified functions will access.
146 struct _EFI_PEI_PCI_CFG2_PPI
{
147 EFI_PEI_PCI_CFG2_PPI_IO Read
;
148 EFI_PEI_PCI_CFG2_PPI_IO Write
;
149 EFI_PEI_PCI_CFG2_PPI_RW Modify
;
154 extern EFI_GUID gEfiPciCfg2PpiGuid
;