2 MM CPU I/O 2 protocol as defined in the PI 1.5 specification.
4 This protocol provides CPU I/O and memory access within MM.
6 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
14 #define EFI_MM_CPU_IO_PROTOCOL_GUID \
16 0x3242A9D8, 0xCE70, 0x4AA0, { 0x95, 0x5D, 0x5E, 0x7B, 0x14, 0x0D, 0xE4, 0xD2 } \
19 typedef struct _EFI_MM_CPU_IO_PROTOCOL EFI_MM_CPU_IO_PROTOCOL
;
22 /// Width of the MM CPU I/O operations
32 Provides the basic memory and I/O interfaces used toabstract accesses to devices.
34 The I/O operations are carried out exactly as requested. The caller is
35 responsible for any alignment and I/O width issues that the bus, device,
36 platform, or type of I/O might require.
38 @param[in] This The EFI_MM_CPU_IO_PROTOCOL instance.
39 @param[in] Width Signifies the width of the I/O operations.
40 @param[in] Address The base address of the I/O operations. The caller is
41 responsible for aligning the Address if required.
42 @param[in] Count The number of I/O operations to perform.
43 @param[in,out] Buffer For read operations, the destination buffer to store
44 the results. For write operations, the source buffer
45 from which to write data.
47 @retval EFI_SUCCESS The data was read from or written to the device.
48 @retval EFI_UNSUPPORTED The Address is not valid for this system.
49 @retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.
50 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack
55 (EFIAPI
*EFI_MM_CPU_IO
)(
56 IN CONST EFI_MM_CPU_IO_PROTOCOL
*This
,
57 IN EFI_MM_IO_WIDTH Width
,
65 /// This service provides the various modalities of memory and I/O read.
69 /// This service provides the various modalities of memory and I/O write.
75 /// MM CPU I/O Protocol provides CPU I/O and memory access within MM.
77 struct _EFI_MM_CPU_IO_PROTOCOL
{
79 /// Allows reads and writes to memory-mapped I/O space.
83 /// Allows reads and writes to I/O space.
88 extern EFI_GUID gEfiMmCpuIoProtocolGuid
;