2 CPUID leaf definitions.
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
9 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
13 @par Specification Reference:
14 AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
18 #ifndef __AMD_CPUID_H__
19 #define __AMD_CPUID_H__
22 CPUID Signature Information
24 @param EAX CPUID_SIGNATURE (0x00)
26 @retval EAX Returns the highest value the CPUID instruction recognizes for
27 returning basic processor information. The value is returned is
29 @retval EBX First 4 characters of a vendor identification string.
30 @retval ECX Last 4 characters of a vendor identification string.
31 @retval EDX Middle 4 characters of a vendor identification string.
36 /// @{ CPUID signature values returned by AMD processors
38 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')
39 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')
40 #define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')
46 CPUID Extended Processor Signature and Features
48 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
50 @retval EAX Extended Family, Model, Stepping Identifiers
51 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
52 @retval EBX Brand Identifier
53 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
54 @retval ECX Extended Feature Identifiers
55 described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
56 @retval EDX Extended Feature Identifiers
57 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
61 CPUID Extended Processor Signature and Features EAX for CPUID leaf
62 #CPUID_EXTENDED_CPU_SIG.
66 /// Individual bit fields
70 /// [Bits 3:0] Stepping.
74 /// [Bits 7:4] Base Model.
78 /// [Bits 11:8] Base Family.
80 UINT32 BaseFamily
: 4;
82 /// [Bit 15:12] Reserved.
86 /// [Bits 19:16] Extended Model.
90 /// [Bits 27:20] Extended Family.
94 /// [Bit 31:28] Reserved.
99 /// All bit fields as a 32-bit value
102 } CPUID_AMD_EXTENDED_CPU_SIG_EAX
;
105 CPUID Extended Processor Signature and Features EBX for CPUID leaf
106 #CPUID_EXTENDED_CPU_SIG.
110 /// Individual bit fields
114 /// [Bits 27:0] Reserved.
116 UINT32 Reserved
: 28;
118 /// [Bit 31:28] Package Type.
123 /// All bit fields as a 32-bit value
126 } CPUID_AMD_EXTENDED_CPU_SIG_EBX
;
129 CPUID Extended Processor Signature and Features ECX for CPUID leaf
130 #CPUID_EXTENDED_CPU_SIG.
134 /// Individual bit fields
138 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
140 UINT32 LAHF_SAHF
: 1;
142 /// [Bit 1] Core multi-processing legacy mode.
144 UINT32 CmpLegacy
: 1;
146 /// [Bit 2] Secure Virtual Mode feature.
150 /// [Bit 3] Extended APIC register space.
152 UINT32 ExtApicSpace
: 1;
154 /// [Bit 4] LOCK MOV CR0 means MOV CR8.
156 UINT32 AltMovCr8
: 1;
158 /// [Bit 5] LZCNT instruction support.
162 /// [Bit 6] SSE4A instruction support.
166 /// [Bit 7] Misaligned SSE Mode.
168 UINT32 MisAlignSse
: 1;
170 /// [Bit 8] ThreeDNow Prefetch instructions.
172 UINT32 PREFETCHW
: 1;
174 /// [Bit 9] OS Visible Work-around support.
178 /// [Bit 10] Instruction Based Sampling.
182 /// [Bit 11] Extended Operation Support.
186 /// [Bit 12] SKINIT and STGI support.
190 /// [Bit 13] Watchdog Timer support.
194 /// [Bit 14] Reserved.
196 UINT32 Reserved1
: 1;
198 /// [Bit 15] Lightweight Profiling support.
202 /// [Bit 16] 4-Operand FMA instruction support.
206 /// [Bit 17] Translation Cache Extension.
210 /// [Bit 21:18] Reserved.
212 UINT32 Reserved2
: 4;
214 /// [Bit 22] Topology Extensions support.
216 UINT32 TopologyExtensions
: 1;
218 /// [Bit 23] Core Performance Counter Extensions.
220 UINT32 PerfCtrExtCore
: 1;
222 /// [Bit 25:24] Reserved.
224 UINT32 Reserved3
: 2;
226 /// [Bit 26] Data Breakpoint Extension.
228 UINT32 DataBreakpointExtension
: 1;
230 /// [Bit 27] Performance Time-Stamp Counter.
234 /// [Bit 28] L3 Performance Counter Extensions.
236 UINT32 PerfCtrExtL3
: 1;
238 /// [Bit 29] MWAITX and MONITORX capability.
240 UINT32 MwaitExtended
: 1;
242 /// [Bit 31:30] Reserved.
244 UINT32 Reserved4
: 2;
247 /// All bit fields as a 32-bit value
250 } CPUID_AMD_EXTENDED_CPU_SIG_ECX
;
253 CPUID Extended Processor Signature and Features EDX for CPUID leaf
254 #CPUID_EXTENDED_CPU_SIG.
258 /// Individual bit fields
262 /// [Bit 0] x87 floating point unit on-chip.
266 /// [Bit 1] Virtual-mode enhancements.
270 /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
274 /// [Bit 3] Page-size extensions (4 MB pages).
278 /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
282 /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
286 /// [Bit 6] Physical-address extensions (PAE).
290 /// [Bit 7] Machine check exception, CR4.MCE.
294 /// [Bit 8] CMPXCHG8B instruction.
296 UINT32 CMPXCHG8B
: 1;
298 /// [Bit 9] APIC exists and is enabled.
302 /// [Bit 10] Reserved.
304 UINT32 Reserved1
: 1;
306 /// [Bit 11] SYSCALL and SYSRET instructions.
308 UINT32 SYSCALL_SYSRET
: 1;
310 /// [Bit 12] Memory-type range registers.
314 /// [Bit 13] Page global extension, CR4.PGE.
318 /// [Bit 14] Machine check architecture, MCG_CAP.
322 /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
326 /// [Bit 16] Page attribute table.
330 /// [Bit 17] Page-size extensions.
334 /// [Bit 19:18] Reserved.
336 UINT32 Reserved2
: 2;
338 /// [Bit 20] No-execute page protection.
342 /// [Bit 21] Reserved.
344 UINT32 Reserved3
: 1;
346 /// [Bit 22] AMD Extensions to MMX instructions.
350 /// [Bit 23] MMX instructions.
354 /// [Bit 24] FXSAVE and FXRSTOR instructions.
358 /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
362 /// [Bit 26] 1-GByte large page support.
366 /// [Bit 27] RDTSCP instructions.
370 /// [Bit 28] Reserved.
372 UINT32 Reserved4
: 1;
374 /// [Bit 29] Long Mode.
378 /// [Bit 30] 3DNow! instructions.
380 UINT32 ThreeDNow
: 1;
382 /// [Bit 31] AMD Extensions to 3DNow! instructions.
384 UINT32 ThreeDNowExt
: 1;
387 /// All bit fields as a 32-bit value
390 } CPUID_AMD_EXTENDED_CPU_SIG_EDX
;
393 CPUID Linear Physical Address Size
395 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
397 @retval EAX Linear/Physical Address Size described by the type
398 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
399 @retval EBX Linear/Physical Address Size described by the type
400 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
401 @retval ECX Linear/Physical Address Size described by the type
402 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
403 @retval EDX Reserved.
407 CPUID Linear Physical Address Size EAX for CPUID leaf
408 #CPUID_VIR_PHY_ADDRESS_SIZE.
412 /// Individual bit fields
416 /// [Bits 7:0] Maximum physical byte address size in bits.
418 UINT32 PhysicalAddressBits
: 8;
420 /// [Bits 15:8] Maximum linear byte address size in bits.
422 UINT32 LinearAddressBits
: 8;
424 /// [Bits 23:16] Maximum guest physical byte address size in bits.
426 UINT32 GuestPhysAddrSize
: 8;
428 /// [Bit 31:24] Reserved.
433 /// All bit fields as a 32-bit value
436 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX
;
439 CPUID Linear Physical Address Size EBX for CPUID leaf
440 #CPUID_VIR_PHY_ADDRESS_SIZE.
444 /// Individual bit fields
448 /// [Bits 0] Clear Zero Instruction.
452 /// [Bits 1] Instructions retired count support.
456 /// [Bits 2] Restore error pointers for XSave instructions.
458 UINT32 XSaveErPtr
: 1;
460 /// [Bit 31:3] Reserved.
462 UINT32 Reserved
: 29;
465 /// All bit fields as a 32-bit value
468 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
;
471 CPUID Linear Physical Address Size ECX for CPUID leaf
472 #CPUID_VIR_PHY_ADDRESS_SIZE.
476 /// Individual bit fields
480 /// [Bits 7:0] Number of threads - 1.
484 /// [Bit 11:8] Reserved.
486 UINT32 Reserved1
: 4;
488 /// [Bits 15:12] APIC ID size.
490 UINT32 ApicIdCoreIdSize
: 4;
492 /// [Bits 17:16] Performance time-stamp counter size.
494 UINT32 PerfTscSize
: 2;
496 /// [Bit 31:18] Reserved.
498 UINT32 Reserved2
: 14;
501 /// All bit fields as a 32-bit value
504 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
;
507 CPUID AMD Processor Topology
509 @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
511 @retval EAX Extended APIC ID described by the type
512 CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
513 @retval EBX Core Identifiers described by the type
514 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
515 @retval ECX Node Identifiers described by the type
516 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
517 @retval EDX Reserved.
519 #define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E
522 CPUID AMD Processor Topology EAX for CPUID leaf
523 #CPUID_AMD_PROCESSOR_TOPOLOGY.
527 /// Individual bit fields
531 /// [Bit 31:0] Extended APIC Id.
533 UINT32 ExtendedApicId
;
536 /// All bit fields as a 32-bit value
539 } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX
;
542 CPUID AMD Processor Topology EBX for CPUID leaf
543 #CPUID_AMD_PROCESSOR_TOPOLOGY.
547 /// Individual bit fields
551 /// [Bits 7:0] Core Id.
555 /// [Bits 15:8] Threads per core.
557 UINT32 ThreadsPerCore
: 8;
559 /// [Bit 31:16] Reserved.
561 UINT32 Reserved
: 16;
564 /// All bit fields as a 32-bit value
567 } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
;
570 CPUID AMD Processor Topology ECX for CPUID leaf
571 #CPUID_AMD_PROCESSOR_TOPOLOGY.
575 /// Individual bit fields
579 /// [Bits 7:0] Node Id.
583 /// [Bits 10:8] Nodes per processor.
585 UINT32 NodesPerProcessor
: 3;
587 /// [Bit 31:11] Reserved.
589 UINT32 Reserved
: 21;
592 /// All bit fields as a 32-bit value
595 } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
;
598 CPUID Memory Encryption Information
600 @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
602 @retval EAX Returns the memory encryption feature support status.
603 @retval EBX If memory encryption feature is present then return
604 the page table bit number used to enable memory encryption support
605 and reducing of physical address space in bits.
606 @retval ECX Returns number of encrypted guest supported simultaneously.
607 @retval EDX Returns minimum SEV enabled and SEV disabled ASID.
616 AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);
620 #define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F
623 CPUID Memory Encryption support information EAX for CPUID leaf
624 #CPUID_MEMORY_ENCRYPTION_INFO.
628 /// Individual bit fields
632 /// [Bit 0] Secure Memory Encryption (Sme) Support
637 /// [Bit 1] Secure Encrypted Virtualization (Sev) Support
642 /// [Bit 2] Page flush MSR support
644 UINT32 PageFlushMsrBit
: 1;
647 /// [Bit 3] Encrypted state support
652 /// [Bit 31:4] Reserved
654 UINT32 ReservedBits
: 28;
657 /// All bit fields as a 32-bit value
660 } CPUID_MEMORY_ENCRYPTION_INFO_EAX
;
663 CPUID Memory Encryption support information EBX for CPUID leaf
664 #CPUID_MEMORY_ENCRYPTION_INFO.
668 /// Individual bit fields
672 /// [Bit 5:0] Page table bit number used to enable memory encryption
674 UINT32 PtePosBits
: 6;
677 /// [Bit 11:6] Reduction of system physical address space bits when
678 /// memory encryption is enabled
680 UINT32 ReducedPhysBits
: 5;
683 /// [Bit 31:12] Reserved
685 UINT32 ReservedBits
: 21;
688 /// All bit fields as a 32-bit value
691 } CPUID_MEMORY_ENCRYPTION_INFO_EBX
;
694 CPUID Memory Encryption support information ECX for CPUID leaf
695 #CPUID_MEMORY_ENCRYPTION_INFO.
699 /// Individual bit fields
703 /// [Bit 31:0] Number of encrypted guest supported simultaneously
708 /// All bit fields as a 32-bit value
711 } CPUID_MEMORY_ENCRYPTION_INFO_ECX
;
714 CPUID Memory Encryption support information EDX for CPUID leaf
715 #CPUID_MEMORY_ENCRYPTION_INFO.
719 /// Individual bit fields
723 /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
728 /// All bit fields as a 32-bit value
731 } CPUID_MEMORY_ENCRYPTION_INFO_EDX
;