2 Intel Architectural MSR Definitions.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __INTEL_ARCHITECTURAL_MSR_H__
19 #define __INTEL_ARCHITECTURAL_MSR_H__
22 See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
24 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
25 @param EAX Lower 32-bits of MSR value.
26 @param EDX Upper 32-bits of MSR value.
32 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
33 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
35 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
37 #define MSR_IA32_P5_MC_ADDR 0x00000000
41 See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
43 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
44 @param EAX Lower 32-bits of MSR value.
45 @param EDX Upper 32-bits of MSR value.
51 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
52 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
54 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
56 #define MSR_IA32_P5_MC_TYPE 0x00000001
60 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
61 at Display Family / Display Model 0F_03H.
63 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
64 @param EAX Lower 32-bits of MSR value.
65 @param EDX Upper 32-bits of MSR value.
71 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
72 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
74 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
76 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
80 See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
83 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
84 @param EAX Lower 32-bits of MSR value.
85 @param EDX Upper 32-bits of MSR value.
91 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
92 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
94 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
96 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
100 Platform ID (RO) The operating system can use this MSR to determine "slot"
101 information for the processor and the proper microcode update to load.
102 Introduced at Display Family / Display Model 06_01H.
104 @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
105 @param EAX Lower 32-bits of MSR value.
106 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
107 @param EDX Upper 32-bits of MSR value.
108 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
112 MSR_IA32_PLATFORM_ID_REGISTER Msr;
114 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
116 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
118 #define MSR_IA32_PLATFORM_ID 0x00000017
121 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
125 /// Individual bit fields
131 /// [Bits 52:50] Platform Id (RO) Contains information concerning the
132 /// intended platform for the processor.
135 /// 0 0 0 Processor Flag 0.
136 /// 0 0 1 Processor Flag 1
137 /// 0 1 0 Processor Flag 2
138 /// 0 1 1 Processor Flag 3
139 /// 1 0 0 Processor Flag 4
140 /// 1 0 1 Processor Flag 5
141 /// 1 1 0 Processor Flag 6
142 /// 1 1 1 Processor Flag 7
148 /// All bit fields as a 64-bit value
151 } MSR_IA32_PLATFORM_ID_REGISTER
;
157 @param ECX MSR_IA32_APIC_BASE (0x0000001B)
158 @param EAX Lower 32-bits of MSR value.
159 Described by the type MSR_IA32_APIC_BASE_REGISTER.
160 @param EDX Upper 32-bits of MSR value.
161 Described by the type MSR_IA32_APIC_BASE_REGISTER.
165 MSR_IA32_APIC_BASE_REGISTER Msr;
167 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
168 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
170 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
172 #define MSR_IA32_APIC_BASE 0x0000001B
175 MSR information returned for MSR index #MSR_IA32_APIC_BASE
179 /// Individual bit fields
184 /// [Bit 8] BSP flag (R/W).
189 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
194 /// [Bit 11] APIC Global Enable (R/W).
198 /// [Bits 31:12] APIC Base (R/W).
202 /// [Bits 63:32] APIC Base (R/W).
204 UINT32 ApicBaseHi
:32;
207 /// All bit fields as a 64-bit value
210 } MSR_IA32_APIC_BASE_REGISTER
;
214 Control Features in Intel 64 Processor (R/W). If any one enumeration
215 condition for defined bit field holds.
217 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
218 @param EAX Lower 32-bits of MSR value.
219 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
220 @param EDX Upper 32-bits of MSR value.
221 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
225 MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
227 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
228 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
230 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
232 #define MSR_IA32_FEATURE_CONTROL 0x0000003A
235 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
239 /// Individual bit fields
243 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
244 /// being written, writes to this bit will result in GP(0). Note: Once the
245 /// Lock bit is set, the contents of this register cannot be modified.
246 /// Therefore the lock bit must be set after configuring support for Intel
247 /// Virtualization Technology and prior to transferring control to an
248 /// option ROM or the OS. Hence, once the Lock bit is set, the entire
249 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
250 /// is not deasserted. If any one enumeration condition for defined bit
251 /// field position greater than bit 0 holds.
255 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
256 /// system executive to use VMX in conjunction with SMX to support
257 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
258 /// when the CPUID function 1 returns VMX feature flag and SMX feature
259 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
260 /// CPUID.01H:ECX[6] = 1.
262 UINT32 EnableVmxInsideSmx
:1;
264 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
265 /// for system executive that do not require SMX. BIOS must set this bit
266 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
267 /// 5). If CPUID.01H:ECX[5] = 1.
269 UINT32 EnableVmxOutsideSmx
:1;
272 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
273 /// in the field represents an enable control for a corresponding SENTER
274 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
275 /// CPUID.01H:ECX[6] = 1.
277 UINT32 SenterLocalFunctionEnables
:7;
279 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
280 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
281 /// 6] is set. If CPUID.01H:ECX[6] = 1.
283 UINT32 SenterGlobalEnable
:1;
286 /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
287 /// enable runtime reconfiguration of SGX Launch Control via
288 /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
290 UINT32 SgxLaunchControlEnable
:1;
292 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
293 /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
298 /// [Bit 20] LMCE On (R/WL): When set, system software can program the
299 /// MSRs associated with LMCE to configure delivery of some machine check
300 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
307 /// All bit fields as a 32-bit value
311 /// All bit fields as a 64-bit value
314 } MSR_IA32_FEATURE_CONTROL_REGISTER
;
318 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
319 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
320 a logical processor. Reset value is Zero. A write to IA32_TSC will modify
321 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
322 not affect the internal invariant TSC hardware.
324 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
325 @param EAX Lower 32-bits of MSR value.
326 @param EDX Upper 32-bits of MSR value.
332 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
333 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
335 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
337 #define MSR_IA32_TSC_ADJUST 0x0000003B
341 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
342 microcode update to be loaded into the processor. See Section 9.11.6,
343 "Microcode Update Loader." A processor may prevent writing to this MSR when
344 loading guest states on VM entries or saving guest states on VM exits.
345 Introduced at Display Family / Display Model 06_01H.
347 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
348 @param EAX Lower 32-bits of MSR value.
349 @param EDX Upper 32-bits of MSR value.
356 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
358 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
360 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
364 BIOS Update Signature (RO) Returns the microcode update signature following
365 the execution of CPUID.01H. A processor may prevent writing to this MSR when
366 loading guest states on VM entries or saving guest states on VM exits.
367 Introduced at Display Family / Display Model 06_01H.
369 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
370 @param EAX Lower 32-bits of MSR value.
371 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
372 @param EDX Upper 32-bits of MSR value.
373 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
377 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
379 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
381 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
383 #define MSR_IA32_BIOS_SIGN_ID 0x0000008B
386 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
390 /// Individual bit fields
395 /// [Bits 63:32] Microcode update signature. This field contains the
396 /// signature of the currently loaded microcode update when read following
397 /// the execution of the CPUID instruction, function 1. It is required
398 /// that this register field be pre-loaded with zero prior to executing
399 /// the CPUID, function 1. If the field remains equal to zero, then there
400 /// is no microcode update loaded. Another nonzero value will be the
403 UINT32 MicrocodeUpdateSignature
:32;
406 /// All bit fields as a 64-bit value
409 } MSR_IA32_BIOS_SIGN_ID_REGISTER
;
413 IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
414 SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
415 default value is the digest of Intel's signing key. Read permitted If
416 CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):
417 EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.
419 @param ECX MSR_IA32_SGXLEPUBKEYHASHn
420 @param EAX Lower 32-bits of MSR value.
421 @param EDX Upper 32-bits of MSR value.
427 Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
428 AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);
430 @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.
431 MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.
432 MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.
433 MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
436 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
437 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
438 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
439 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
444 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
447 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
448 @param EAX Lower 32-bits of MSR value.
449 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
450 @param EDX Upper 32-bits of MSR value.
451 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
455 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
457 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
458 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
460 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
462 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
465 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
469 /// Individual bit fields
473 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
474 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
475 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
476 /// if the bit is 0. This bit is cleared when the logical processor is
482 /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
483 /// IA32_VMX_MISC[28].
488 /// [Bits 31:12] MSEG Base (R/W).
494 /// All bit fields as a 32-bit value
498 /// All bit fields as a 64-bit value
501 } MSR_IA32_SMM_MONITOR_CTL_REGISTER
;
504 MSEG header that is located at the physical address specified by the MsegBase
505 field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
509 /// Different processors may use different MSEG revision identifiers. These
510 /// identifiers enable software to avoid using an MSEG header formatted for
511 /// one processor on a processor that uses a different format. Software can
512 /// discover the MSEG revision identifier that a processor uses by reading
513 /// the VMX capability MSR IA32_VMX_MISC.
515 UINT32 MsegHeaderRevision
;
517 /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
518 /// is the IA-32e mode SMM feature bit. It indicates whether the logical
519 /// processor will be in IA-32e mode after the STM is activated.
521 UINT32 MonitorFeatures
;
523 UINT32 GdtrBaseOffset
;
529 /// Pad header so total size is 2KB
531 UINT8 Reserved
[SIZE_2KB
- 8 * sizeof (UINT32
)];
535 /// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
537 #define STM_FEATURES_IA32E 0x1
543 Base address of the logical processor's SMRAM image (RO, SMM only). If
546 @param ECX MSR_IA32_SMBASE (0x0000009E)
547 @param EAX Lower 32-bits of MSR value.
548 @param EDX Upper 32-bits of MSR value.
554 Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
556 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
558 #define MSR_IA32_SMBASE 0x0000009E
562 General Performance Counters (R/W).
563 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
565 @param ECX MSR_IA32_PMCn
566 @param EAX Lower 32-bits of MSR value.
567 @param EDX Upper 32-bits of MSR value.
573 Msr = AsmReadMsr64 (MSR_IA32_PMC0);
574 AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
576 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
577 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
578 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
579 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
580 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
581 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
582 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
583 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
586 #define MSR_IA32_PMC0 0x000000C1
587 #define MSR_IA32_PMC1 0x000000C2
588 #define MSR_IA32_PMC2 0x000000C3
589 #define MSR_IA32_PMC3 0x000000C4
590 #define MSR_IA32_PMC4 0x000000C5
591 #define MSR_IA32_PMC5 0x000000C6
592 #define MSR_IA32_PMC6 0x000000C7
593 #define MSR_IA32_PMC7 0x000000C8
598 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
599 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
600 to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
601 wrap-around of IA32_APERF.
603 @param ECX MSR_IA32_MPERF (0x000000E7)
604 @param EAX Lower 32-bits of MSR value.
605 @param EDX Upper 32-bits of MSR value.
611 Msr = AsmReadMsr64 (MSR_IA32_MPERF);
612 AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
614 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
616 #define MSR_IA32_MPERF 0x000000E7
620 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
621 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
622 the coordinated clock frequency, when the logical processor is in C0.
623 Cleared upon overflow / wrap-around of IA32_MPERF.
625 @param ECX MSR_IA32_APERF (0x000000E8)
626 @param EAX Lower 32-bits of MSR value.
627 @param EDX Upper 32-bits of MSR value.
633 Msr = AsmReadMsr64 (MSR_IA32_APERF);
634 AsmWriteMsr64 (MSR_IA32_APERF, Msr);
636 @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
638 #define MSR_IA32_APERF 0x000000E8
642 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
643 Introduced at Display Family / Display Model 06_01H.
645 @param ECX MSR_IA32_MTRRCAP (0x000000FE)
646 @param EAX Lower 32-bits of MSR value.
647 Described by the type MSR_IA32_MTRRCAP_REGISTER.
648 @param EDX Upper 32-bits of MSR value.
649 Described by the type MSR_IA32_MTRRCAP_REGISTER.
653 MSR_IA32_MTRRCAP_REGISTER Msr;
655 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
657 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
659 #define MSR_IA32_MTRRCAP 0x000000FE
662 MSR information returned for MSR index #MSR_IA32_MTRRCAP
666 /// Individual bit fields
670 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
675 /// [Bit 8] Fixed range MTRRs are supported when set.
680 /// [Bit 10] WC Supported when set.
684 /// [Bit 11] SMRR Supported when set.
691 /// All bit fields as a 32-bit value
695 /// All bit fields as a 64-bit value
698 } MSR_IA32_MTRRCAP_REGISTER
;
702 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
704 @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
705 @param EAX Lower 32-bits of MSR value.
706 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
707 @param EDX Upper 32-bits of MSR value.
708 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
712 MSR_IA32_SYSENTER_CS_REGISTER Msr;
714 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
715 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
717 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
719 #define MSR_IA32_SYSENTER_CS 0x00000174
722 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
726 /// Individual bit fields
730 /// [Bits 15:0] CS Selector.
737 /// All bit fields as a 32-bit value
741 /// All bit fields as a 64-bit value
744 } MSR_IA32_SYSENTER_CS_REGISTER
;
748 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
750 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
751 @param EAX Lower 32-bits of MSR value.
752 @param EDX Upper 32-bits of MSR value.
758 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
759 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
761 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
763 #define MSR_IA32_SYSENTER_ESP 0x00000175
767 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
769 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
770 @param EAX Lower 32-bits of MSR value.
771 @param EDX Upper 32-bits of MSR value.
777 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
778 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
780 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
782 #define MSR_IA32_SYSENTER_EIP 0x00000176
786 Global Machine Check Capability (RO). Introduced at Display Family / Display
789 @param ECX MSR_IA32_MCG_CAP (0x00000179)
790 @param EAX Lower 32-bits of MSR value.
791 Described by the type MSR_IA32_MCG_CAP_REGISTER.
792 @param EDX Upper 32-bits of MSR value.
793 Described by the type MSR_IA32_MCG_CAP_REGISTER.
797 MSR_IA32_MCG_CAP_REGISTER Msr;
799 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
801 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
803 #define MSR_IA32_MCG_CAP 0x00000179
806 MSR information returned for MSR index #MSR_IA32_MCG_CAP
810 /// Individual bit fields
814 /// [Bits 7:0] Count: Number of reporting banks.
818 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
822 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
823 /// if this bit is set.
827 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
828 /// Introduced at Display Family / Display Model 06_01H.
832 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
833 /// if this bit is set.
838 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
839 /// registers present.
841 UINT32 MCG_EXT_CNT
:8;
843 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
849 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
850 /// firmware to be invoked when an error is detected so that it may
851 /// provide additional platform specific information in an ACPI format
852 /// "Generic Error Data Entry" that augments the data included in machine
853 /// check bank registers. Introduced at Display Family / Display Model
858 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
859 /// state in IA32_MCG_STATUS and associated MSR necessary to configure
860 /// Local Machine Check Exception (LMCE). Introduced at Display Family /
861 /// Display Model 06_3EH.
868 /// All bit fields as a 32-bit value
872 /// All bit fields as a 64-bit value
875 } MSR_IA32_MCG_CAP_REGISTER
;
879 Global Machine Check Status (R/W0). Introduced at Display Family / Display
882 @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
883 @param EAX Lower 32-bits of MSR value.
884 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
885 @param EDX Upper 32-bits of MSR value.
886 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
890 MSR_IA32_MCG_STATUS_REGISTER Msr;
892 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
893 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
895 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
897 #define MSR_IA32_MCG_STATUS 0x0000017A
900 MSR information returned for MSR index #MSR_IA32_MCG_STATUS
904 /// Individual bit fields
908 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
913 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
918 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
919 /// / Display Model 06_01H.
923 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
930 /// All bit fields as a 32-bit value
934 /// All bit fields as a 64-bit value
937 } MSR_IA32_MCG_STATUS_REGISTER
;
941 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
943 @param ECX MSR_IA32_MCG_CTL (0x0000017B)
944 @param EAX Lower 32-bits of MSR value.
945 @param EDX Upper 32-bits of MSR value.
951 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
952 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
954 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
956 #define MSR_IA32_MCG_CTL 0x0000017B
960 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
962 @param ECX MSR_IA32_PERFEVTSELn
963 @param EAX Lower 32-bits of MSR value.
964 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
965 @param EDX Upper 32-bits of MSR value.
966 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
970 MSR_IA32_PERFEVTSEL_REGISTER Msr;
972 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
973 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
975 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
976 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
977 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
978 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
981 #define MSR_IA32_PERFEVTSEL0 0x00000186
982 #define MSR_IA32_PERFEVTSEL1 0x00000187
983 #define MSR_IA32_PERFEVTSEL2 0x00000188
984 #define MSR_IA32_PERFEVTSEL3 0x00000189
988 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
989 #MSR_IA32_PERFEVTSEL3
993 /// Individual bit fields
997 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
999 UINT32 EventSelect
:8;
1001 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
1002 /// detect on the selected event logic.
1006 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
1010 /// [Bit 17] OS: Counts while in privilege level is ring 0.
1014 /// [Bit 18] Edge: Enables edge detection if set.
1018 /// [Bit 19] PC: enables pin control.
1022 /// [Bit 20] INT: enables interrupt on counter overflow.
1026 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
1027 /// event conditions occurring across all logical processors sharing a
1028 /// processor core. When set to 0, the counter only increments the
1029 /// associated event conditions occurring in the logical processor which
1030 /// programmed the MSR.
1034 /// [Bit 22] EN: enables the corresponding performance counter to commence
1035 /// counting when this bit is set.
1039 /// [Bit 23] INV: invert the CMASK.
1043 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
1044 /// performance counter increments each cycle if the event count is
1045 /// greater than or equal to the CMASK.
1051 /// All bit fields as a 32-bit value
1055 /// All bit fields as a 64-bit value
1058 } MSR_IA32_PERFEVTSEL_REGISTER
;
1062 Current performance state(P-State) operating point (RO). Introduced at
1063 Display Family / Display Model 0F_03H.
1065 @param ECX MSR_IA32_PERF_STATUS (0x00000198)
1066 @param EAX Lower 32-bits of MSR value.
1067 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1068 @param EDX Upper 32-bits of MSR value.
1069 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1071 <b>Example usage</b>
1073 MSR_IA32_PERF_STATUS_REGISTER Msr;
1075 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
1077 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
1079 #define MSR_IA32_PERF_STATUS 0x00000198
1082 MSR information returned for MSR index #MSR_IA32_PERF_STATUS
1086 /// Individual bit fields
1090 /// [Bits 15:0] Current performance State Value.
1093 UINT32 Reserved1
:16;
1094 UINT32 Reserved2
:32;
1097 /// All bit fields as a 32-bit value
1101 /// All bit fields as a 64-bit value
1104 } MSR_IA32_PERF_STATUS_REGISTER
;
1108 (R/W). Introduced at Display Family / Display Model 0F_03H.
1110 @param ECX MSR_IA32_PERF_CTL (0x00000199)
1111 @param EAX Lower 32-bits of MSR value.
1112 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1113 @param EDX Upper 32-bits of MSR value.
1114 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1116 <b>Example usage</b>
1118 MSR_IA32_PERF_CTL_REGISTER Msr;
1120 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
1121 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
1123 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
1125 #define MSR_IA32_PERF_CTL 0x00000199
1128 MSR information returned for MSR index #MSR_IA32_PERF_CTL
1132 /// Individual bit fields
1136 /// [Bits 15:0] Target performance State Value.
1138 UINT32 TargetState
:16;
1139 UINT32 Reserved1
:16;
1141 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
1145 UINT32 Reserved2
:31;
1148 /// All bit fields as a 64-bit value
1151 } MSR_IA32_PERF_CTL_REGISTER
;
1155 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
1156 Clock Modulation.". If CPUID.01H:EDX[22] = 1.
1158 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
1159 @param EAX Lower 32-bits of MSR value.
1160 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1161 @param EDX Upper 32-bits of MSR value.
1162 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1164 <b>Example usage</b>
1166 MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
1168 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
1169 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
1171 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
1173 #define MSR_IA32_CLOCK_MODULATION 0x0000019A
1176 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
1180 /// Individual bit fields
1184 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
1185 /// CPUID.06H:EAX[5] = 1.
1187 UINT32 ExtendedOnDemandClockModulationDutyCycle
:1;
1189 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
1190 /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
1192 UINT32 OnDemandClockModulationDutyCycle
:3;
1194 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
1195 /// If CPUID.01H:EDX[22] = 1.
1197 UINT32 OnDemandClockModulationEnable
:1;
1198 UINT32 Reserved1
:27;
1199 UINT32 Reserved2
:32;
1202 /// All bit fields as a 32-bit value
1206 /// All bit fields as a 64-bit value
1209 } MSR_IA32_CLOCK_MODULATION_REGISTER
;
1213 Thermal Interrupt Control (R/W) Enables and disables the generation of an
1214 interrupt on temperature transitions detected with the processor's thermal
1215 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
1216 If CPUID.01H:EDX[22] = 1
1218 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
1219 @param EAX Lower 32-bits of MSR value.
1220 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1221 @param EDX Upper 32-bits of MSR value.
1222 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1224 <b>Example usage</b>
1226 MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
1228 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
1229 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
1231 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
1233 #define MSR_IA32_THERM_INTERRUPT 0x0000019B
1236 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
1240 /// Individual bit fields
1244 /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1246 UINT32 HighTempEnable
:1;
1248 /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1250 UINT32 LowTempEnable
:1;
1252 /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1254 UINT32 PROCHOT_Enable
:1;
1256 /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1258 UINT32 FORCEPR_Enable
:1;
1260 /// [Bit 4] Critical Temperature Interrupt Enable.
1261 /// If CPUID.01H:EDX[22] = 1.
1263 UINT32 CriticalTempEnable
:1;
1266 /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
1268 UINT32 Threshold1
:7;
1270 /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1272 UINT32 Threshold1Enable
:1;
1274 /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
1276 UINT32 Threshold2
:7;
1278 /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1280 UINT32 Threshold2Enable
:1;
1282 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
1284 UINT32 PowerLimitNotificationEnable
:1;
1286 UINT32 Reserved3
:32;
1289 /// All bit fields as a 32-bit value
1293 /// All bit fields as a 64-bit value
1296 } MSR_IA32_THERM_INTERRUPT_REGISTER
;
1300 Thermal Status Information (RO) Contains status information about the
1301 processor's thermal sensor and automatic thermal monitoring facilities. See
1302 Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.
1304 @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
1305 @param EAX Lower 32-bits of MSR value.
1306 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1307 @param EDX Upper 32-bits of MSR value.
1308 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1310 <b>Example usage</b>
1312 MSR_IA32_THERM_STATUS_REGISTER Msr;
1314 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
1316 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
1318 #define MSR_IA32_THERM_STATUS 0x0000019C
1321 MSR information returned for MSR index #MSR_IA32_THERM_STATUS
1325 /// Individual bit fields
1329 /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
1331 UINT32 ThermalStatus
:1;
1333 /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
1335 UINT32 ThermalStatusLog
:1;
1337 /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
1339 UINT32 PROCHOT_FORCEPR_Event
:1;
1341 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
1343 UINT32 PROCHOT_FORCEPR_Log
:1;
1345 /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
1347 UINT32 CriticalTempStatus
:1;
1349 /// [Bit 5] Critical Temperature Status log (R/WC0).
1350 /// If CPUID.01H:EDX[22] = 1.
1352 UINT32 CriticalTempStatusLog
:1;
1354 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
1356 UINT32 ThermalThreshold1Status
:1;
1358 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1360 UINT32 ThermalThreshold1Log
:1;
1362 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
1364 UINT32 ThermalThreshold2Status
:1;
1366 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1368 UINT32 ThermalThreshold2Log
:1;
1370 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
1372 UINT32 PowerLimitStatus
:1;
1374 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
1376 UINT32 PowerLimitLog
:1;
1378 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1380 UINT32 CurrentLimitStatus
:1;
1382 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1384 UINT32 CurrentLimitLog
:1;
1386 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1388 UINT32 CrossDomainLimitStatus
:1;
1390 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1392 UINT32 CrossDomainLimitLog
:1;
1394 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
1396 UINT32 DigitalReadout
:7;
1399 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
1402 UINT32 ResolutionInDegreesCelsius
:4;
1404 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
1406 UINT32 ReadingValid
:1;
1407 UINT32 Reserved2
:32;
1410 /// All bit fields as a 32-bit value
1414 /// All bit fields as a 64-bit value
1417 } MSR_IA32_THERM_STATUS_REGISTER
;
1421 Enable Misc. Processor Features (R/W) Allows a variety of processor
1422 functions to be enabled and disabled.
1424 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
1425 @param EAX Lower 32-bits of MSR value.
1426 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1427 @param EDX Upper 32-bits of MSR value.
1428 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1430 <b>Example usage</b>
1432 MSR_IA32_MISC_ENABLE_REGISTER Msr;
1434 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
1435 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
1437 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
1439 #define MSR_IA32_MISC_ENABLE 0x000001A0
1442 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
1446 /// Individual bit fields
1450 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
1451 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
1452 /// are disabled. Introduced at Display Family / Display Model 0F_0H.
1454 UINT32 FastStrings
:1;
1457 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
1458 /// this bit enables the thermal control circuit (TCC) portion of the
1459 /// Intel Thermal Monitor feature. This allows the processor to
1460 /// automatically reduce power consumption in response to TCC activation.
1461 /// 0 = Disabled. Note: In some products clearing this bit might be
1462 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
1463 /// thermal throttling will still be activated. The default value of this
1464 /// field varies with product. See respective tables where default value is
1465 /// listed. Introduced at Display Family / Display Model 0F_0H.
1467 UINT32 AutomaticThermalControlCircuit
:1;
1470 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
1471 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
1472 /// Display Family / Display Model 0F_0H.
1474 UINT32 PerformanceMonitoring
:1;
1477 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
1478 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
1479 /// Display Family / Display Model 0F_0H.
1483 /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =
1484 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
1485 /// Family / Display Model 06_0FH.
1490 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
1491 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
1492 /// Technology enabled. If CPUID.01H: ECX[7] =1.
1497 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
1498 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
1499 /// indicates that MONITOR/MWAIT are not supported. Software attempts to
1500 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
1501 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
1502 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
1503 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
1504 /// in the default state. Writing this bit when the SSE3 feature flag is
1505 /// set to 0 may generate a #GP exception. Introduced at Display Family /
1506 /// Display Model 0F_03H.
1511 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
1512 /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
1513 /// question that allows users to specify when the installed OS does not
1514 /// support CPUID functions greater than 2. Before setting this bit, BIOS
1515 /// must execute the CPUID.0H and examine the maximum value returned in
1516 /// EAX[7:0]. If the maximum value is greater than 2, this bit is
1517 /// supported. Otherwise, this bit is not supported. Setting this bit when
1518 /// the maximum value is not greater than 2 may generate a #GP exception.
1519 /// Setting this bit may cause unexpected behavior in software that
1520 /// depends on the availability of CPUID leaves greater than 2. Introduced
1521 /// at Display Family / Display Model 0F_03H.
1523 UINT32 LimitCpuidMaxval
:1;
1525 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
1526 /// disabled. xTPR messages are optional messages that allow the processor
1527 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
1529 UINT32 xTPR_Message_Disable
:1;
1533 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
1534 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
1535 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
1536 /// Execute Disable Bit feature (if available) allows the OS to enable PAE
1537 /// paging and take advantage of data only pages. BIOS must not alter the
1538 /// contents of this bit location, if XD bit is not supported. Writing
1539 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
1540 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
1543 UINT32 Reserved9
:29;
1546 /// All bit fields as a 64-bit value
1549 } MSR_IA32_MISC_ENABLE_REGISTER
;
1553 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
1555 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
1556 @param EAX Lower 32-bits of MSR value.
1557 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1558 @param EDX Upper 32-bits of MSR value.
1559 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1561 <b>Example usage</b>
1563 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
1565 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
1566 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
1568 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
1570 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1573 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
1577 /// Individual bit fields
1581 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
1582 /// performance. 15 indicates preference to maximize energy saving.
1584 UINT32 PowerPolicyPreference
:4;
1585 UINT32 Reserved1
:28;
1586 UINT32 Reserved2
:32;
1589 /// All bit fields as a 32-bit value
1593 /// All bit fields as a 64-bit value
1596 } MSR_IA32_ENERGY_PERF_BIAS_REGISTER
;
1600 Package Thermal Status Information (RO) Contains status information about
1601 the package's thermal sensor. See Section 14.8, "Package Level Thermal
1602 Management.". If CPUID.06H: EAX[6] = 1.
1604 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
1605 @param EAX Lower 32-bits of MSR value.
1606 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1607 @param EDX Upper 32-bits of MSR value.
1608 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1610 <b>Example usage</b>
1612 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
1614 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
1616 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
1618 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1621 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
1625 /// Individual bit fields
1629 /// [Bit 0] Pkg Thermal Status (RO):.
1631 UINT32 ThermalStatus
:1;
1633 /// [Bit 1] Pkg Thermal Status Log (R/W):.
1635 UINT32 ThermalStatusLog
:1;
1637 /// [Bit 2] Pkg PROCHOT # event (RO).
1639 UINT32 PROCHOT_Event
:1;
1641 /// [Bit 3] Pkg PROCHOT # log (R/WC0).
1643 UINT32 PROCHOT_Log
:1;
1645 /// [Bit 4] Pkg Critical Temperature Status (RO).
1647 UINT32 CriticalTempStatus
:1;
1649 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
1651 UINT32 CriticalTempStatusLog
:1;
1653 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
1655 UINT32 ThermalThreshold1Status
:1;
1657 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
1659 UINT32 ThermalThreshold1Log
:1;
1661 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
1663 UINT32 ThermalThreshold2Status
:1;
1665 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
1667 UINT32 ThermalThreshold2Log
:1;
1669 /// [Bit 10] Pkg Power Limitation Status (RO).
1671 UINT32 PowerLimitStatus
:1;
1673 /// [Bit 11] Pkg Power Limitation log (R/WC0).
1675 UINT32 PowerLimitLog
:1;
1678 /// [Bits 22:16] Pkg Digital Readout (RO).
1680 UINT32 DigitalReadout
:7;
1682 UINT32 Reserved3
:32;
1685 /// All bit fields as a 32-bit value
1689 /// All bit fields as a 64-bit value
1692 } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
;
1696 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
1697 an interrupt on temperature transitions detected with the package's thermal
1698 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
1701 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
1702 @param EAX Lower 32-bits of MSR value.
1703 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1704 @param EDX Upper 32-bits of MSR value.
1705 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1707 <b>Example usage</b>
1709 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
1711 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
1712 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
1714 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
1716 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1719 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
1723 /// Individual bit fields
1727 /// [Bit 0] Pkg High-Temperature Interrupt Enable.
1729 UINT32 HighTempEnable
:1;
1731 /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
1733 UINT32 LowTempEnable
:1;
1735 /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
1737 UINT32 PROCHOT_Enable
:1;
1740 /// [Bit 4] Pkg Overheat Interrupt Enable.
1742 UINT32 OverheatEnable
:1;
1745 /// [Bits 14:8] Pkg Threshold #1 Value.
1747 UINT32 Threshold1
:7;
1749 /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
1751 UINT32 Threshold1Enable
:1;
1753 /// [Bits 22:16] Pkg Threshold #2 Value.
1755 UINT32 Threshold2
:7;
1757 /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
1759 UINT32 Threshold2Enable
:1;
1761 /// [Bit 24] Pkg Power Limit Notification Enable.
1763 UINT32 PowerLimitNotificationEnable
:1;
1765 UINT32 Reserved4
:32;
1768 /// All bit fields as a 32-bit value
1772 /// All bit fields as a 64-bit value
1775 } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
;
1779 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
1782 @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
1783 @param EAX Lower 32-bits of MSR value.
1784 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1785 @param EDX Upper 32-bits of MSR value.
1786 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1788 <b>Example usage</b>
1790 MSR_IA32_DEBUGCTL_REGISTER Msr;
1792 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
1793 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
1795 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
1797 #define MSR_IA32_DEBUGCTL 0x000001D9
1800 MSR information returned for MSR index #MSR_IA32_DEBUGCTL
1804 /// Individual bit fields
1808 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
1809 /// running trace of the most recent branches taken by the processor in
1810 /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
1814 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
1815 /// EFLAGS.TF as single-step on branches instead of single-step on
1816 /// instructions. Introduced at Display Family / Display Model 06_01H.
1821 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
1822 /// sent. Introduced at Display Family / Display Model 06_0EH.
1826 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
1827 /// be logged in a BTS buffer. Introduced at Display Family / Display
1832 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
1833 /// fashion. When this bit is set, an interrupt is generated by the BTS
1834 /// facility when the BTS buffer is full. Introduced at Display Family /
1835 /// Display Model 06_0EH.
1839 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
1840 /// Introduced at Display Family / Display Model 06_0FH.
1842 UINT32 BTS_OFF_OS
:1;
1844 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
1845 /// Introduced at Display Family / Display Model 06_0FH.
1847 UINT32 BTS_OFF_USR
:1;
1849 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
1850 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1852 UINT32 FREEZE_LBRS_ON_PMI
:1;
1854 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
1855 /// global counter control MSR are frozen (address 38FH) on a PMI request.
1856 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1858 UINT32 FREEZE_PERFMON_ON_PMI
:1;
1860 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
1861 /// receive and generate PMI on behalf of the uncore. Introduced at
1862 /// Display Family / Display Model 06_1AH.
1864 UINT32 ENABLE_UNCORE_PMI
:1;
1866 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
1867 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
1869 UINT32 FREEZE_WHILE_SMM
:1;
1871 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
1872 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
1875 UINT32 Reserved2
:16;
1876 UINT32 Reserved3
:32;
1879 /// All bit fields as a 32-bit value
1883 /// All bit fields as a 64-bit value
1886 } MSR_IA32_DEBUGCTL_REGISTER
;
1890 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
1891 If IA32_MTRRCAP.SMRR[11] = 1.
1893 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
1894 @param EAX Lower 32-bits of MSR value.
1895 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1896 @param EDX Upper 32-bits of MSR value.
1897 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1899 <b>Example usage</b>
1901 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
1903 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
1904 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
1906 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
1908 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1911 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
1915 /// Individual bit fields
1919 /// [Bits 7:0] Type. Specifies memory type of the range.
1924 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
1927 UINT32 Reserved2
:32;
1930 /// All bit fields as a 32-bit value
1934 /// All bit fields as a 64-bit value
1937 } MSR_IA32_SMRR_PHYSBASE_REGISTER
;
1941 SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
1942 IA32_MTRRCAP[SMRR] = 1.
1944 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
1945 @param EAX Lower 32-bits of MSR value.
1946 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1947 @param EDX Upper 32-bits of MSR value.
1948 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1950 <b>Example usage</b>
1952 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
1954 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
1955 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
1957 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
1959 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1962 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
1966 /// Individual bit fields
1969 UINT32 Reserved1
:11;
1971 /// [Bit 11] Valid Enable range mask.
1975 /// [Bits 31:12] PhysMask SMRR address range mask.
1978 UINT32 Reserved2
:32;
1981 /// All bit fields as a 32-bit value
1985 /// All bit fields as a 64-bit value
1988 } MSR_IA32_SMRR_PHYSMASK_REGISTER
;
1992 DCA Capability (R). If CPUID.01H: ECX[18] = 1.
1994 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
1995 @param EAX Lower 32-bits of MSR value.
1996 @param EDX Upper 32-bits of MSR value.
1998 <b>Example usage</b>
2002 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
2004 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
2006 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
2010 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
2012 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
2013 @param EAX Lower 32-bits of MSR value.
2014 @param EDX Upper 32-bits of MSR value.
2016 <b>Example usage</b>
2020 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
2021 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
2023 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
2025 #define MSR_IA32_CPU_DCA_CAP 0x000001F9
2029 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
2031 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
2032 @param EAX Lower 32-bits of MSR value.
2033 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
2034 @param EDX Upper 32-bits of MSR value.
2035 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
2037 <b>Example usage</b>
2039 MSR_IA32_DCA_0_CAP_REGISTER Msr;
2041 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
2042 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
2044 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
2046 #define MSR_IA32_DCA_0_CAP 0x000001FA
2049 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
2053 /// Individual bit fields
2057 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
2058 /// defeatures are set.
2060 UINT32 DCA_ACTIVE
:1;
2062 /// [Bits 2:1] TRANSACTION.
2064 UINT32 TRANSACTION
:2;
2066 /// [Bits 6:3] DCA_TYPE.
2070 /// [Bits 10:7] DCA_QUEUE_SIZE.
2072 UINT32 DCA_QUEUE_SIZE
:4;
2075 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
2081 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
2086 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
2090 UINT32 Reserved5
:32;
2093 /// All bit fields as a 32-bit value
2097 /// All bit fields as a 64-bit value
2100 } MSR_IA32_DCA_0_CAP_REGISTER
;
2104 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
2105 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2107 @param ECX MSR_IA32_MTRR_PHYSBASEn
2108 @param EAX Lower 32-bits of MSR value.
2109 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2110 @param EDX Upper 32-bits of MSR value.
2111 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2113 <b>Example usage</b>
2115 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
2117 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
2118 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
2120 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
2121 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
2122 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
2123 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
2124 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
2125 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
2126 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
2127 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
2128 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
2129 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
2132 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2133 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2134 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2135 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2136 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2137 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2138 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2139 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2140 #define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2141 #define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2145 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
2146 #MSR_IA32_MTRR_PHYSBASE9
2150 /// Individual bit fields
2154 /// [Bits 7:0] Type. Specifies memory type of the range.
2159 /// [Bits 31:12] PhysBase. MTRR physical Base Address.
2163 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
2164 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2165 /// maximum physical address range supported by the processor. It is
2166 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2167 /// leaf 80000008H, the processor supports 36-bit physical address size,
2168 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2170 UINT32 PhysBaseHi
:32;
2173 /// All bit fields as a 64-bit value
2176 } MSR_IA32_MTRR_PHYSBASE_REGISTER
;
2180 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
2181 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2183 @param ECX MSR_IA32_MTRR_PHYSMASKn
2184 @param EAX Lower 32-bits of MSR value.
2185 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2186 @param EDX Upper 32-bits of MSR value.
2187 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2189 <b>Example usage</b>
2191 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
2193 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
2194 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
2196 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
2197 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
2198 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
2199 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
2200 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
2201 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
2202 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
2203 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
2204 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
2205 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
2208 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2209 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2210 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2211 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2212 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2213 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2214 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2215 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2216 #define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2217 #define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2221 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
2222 #MSR_IA32_MTRR_PHYSMASK9
2226 /// Individual bit fields
2229 UINT32 Reserved1
:11;
2231 /// [Bit 11] Valid Enable range mask.
2235 /// [Bits 31:12] PhysMask. MTRR address range mask.
2239 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
2240 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2241 /// maximum physical address range supported by the processor. It is
2242 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2243 /// leaf 80000008H, the processor supports 36-bit physical address size,
2244 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2246 UINT32 PhysMaskHi
:32;
2249 /// All bit fields as a 64-bit value
2252 } MSR_IA32_MTRR_PHYSMASK_REGISTER
;
2256 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
2258 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
2259 @param EAX Lower 32-bits of MSR value.
2260 @param EDX Upper 32-bits of MSR value.
2262 <b>Example usage</b>
2266 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
2267 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
2269 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
2271 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2275 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
2277 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
2278 @param EAX Lower 32-bits of MSR value.
2279 @param EDX Upper 32-bits of MSR value.
2281 <b>Example usage</b>
2285 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
2286 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
2288 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
2290 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2294 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
2296 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
2297 @param EAX Lower 32-bits of MSR value.
2298 @param EDX Upper 32-bits of MSR value.
2300 <b>Example usage</b>
2304 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
2305 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
2307 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
2309 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2313 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
2315 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
2316 @param EAX Lower 32-bits of MSR value.
2317 @param EDX Upper 32-bits of MSR value.
2319 <b>Example usage</b>
2323 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
2324 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
2326 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
2328 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2332 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
2334 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
2335 @param EAX Lower 32-bits of MSR value.
2336 @param EDX Upper 32-bits of MSR value.
2338 <b>Example usage</b>
2342 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
2343 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
2345 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
2347 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2351 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
2353 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
2354 @param EAX Lower 32-bits of MSR value.
2355 @param EDX Upper 32-bits of MSR value.
2357 <b>Example usage</b>
2361 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
2362 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
2364 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
2366 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2370 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
2372 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
2373 @param EAX Lower 32-bits of MSR value.
2374 @param EDX Upper 32-bits of MSR value.
2376 <b>Example usage</b>
2380 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
2381 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
2383 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
2385 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2389 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
2391 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
2392 @param EAX Lower 32-bits of MSR value.
2393 @param EDX Upper 32-bits of MSR value.
2395 <b>Example usage</b>
2399 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
2400 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
2402 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
2404 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2408 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
2410 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
2411 @param EAX Lower 32-bits of MSR value.
2412 @param EDX Upper 32-bits of MSR value.
2414 <b>Example usage</b>
2418 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
2419 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
2421 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
2423 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2427 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
2429 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
2430 @param EAX Lower 32-bits of MSR value.
2431 @param EDX Upper 32-bits of MSR value.
2433 <b>Example usage</b>
2437 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
2438 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
2440 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
2442 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2446 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
2448 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
2449 @param EAX Lower 32-bits of MSR value.
2450 @param EDX Upper 32-bits of MSR value.
2452 <b>Example usage</b>
2456 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
2457 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
2459 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
2461 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2465 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
2467 @param ECX MSR_IA32_PAT (0x00000277)
2468 @param EAX Lower 32-bits of MSR value.
2469 Described by the type MSR_IA32_PAT_REGISTER.
2470 @param EDX Upper 32-bits of MSR value.
2471 Described by the type MSR_IA32_PAT_REGISTER.
2473 <b>Example usage</b>
2475 MSR_IA32_PAT_REGISTER Msr;
2477 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
2478 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
2480 @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
2482 #define MSR_IA32_PAT 0x00000277
2485 MSR information returned for MSR index #MSR_IA32_PAT
2489 /// Individual bit fields
2498 /// [Bits 10:8] PA1.
2503 /// [Bits 18:16] PA2.
2508 /// [Bits 26:24] PA3.
2513 /// [Bits 34:32] PA4.
2518 /// [Bits 42:40] PA5.
2523 /// [Bits 50:48] PA6.
2528 /// [Bits 58:56] PA7.
2534 /// All bit fields as a 64-bit value
2537 } MSR_IA32_PAT_REGISTER
;
2541 Provides the programming interface to use corrected MC error signaling
2542 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
2544 @param ECX MSR_IA32_MCn_CTL2
2545 @param EAX Lower 32-bits of MSR value.
2546 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2547 @param EDX Upper 32-bits of MSR value.
2548 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2550 <b>Example usage</b>
2552 MSR_IA32_MC_CTL2_REGISTER Msr;
2554 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
2555 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
2557 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.
2558 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.
2559 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.
2560 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.
2561 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
2562 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.
2563 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.
2564 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.
2565 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.
2566 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.
2567 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
2568 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
2569 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
2570 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
2571 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
2572 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
2573 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
2574 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
2575 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
2576 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
2577 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
2578 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
2579 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
2580 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
2581 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
2582 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
2583 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
2584 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
2585 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
2586 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
2587 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
2588 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
2591 #define MSR_IA32_MC0_CTL2 0x00000280
2592 #define MSR_IA32_MC1_CTL2 0x00000281
2593 #define MSR_IA32_MC2_CTL2 0x00000282
2594 #define MSR_IA32_MC3_CTL2 0x00000283
2595 #define MSR_IA32_MC4_CTL2 0x00000284
2596 #define MSR_IA32_MC5_CTL2 0x00000285
2597 #define MSR_IA32_MC6_CTL2 0x00000286
2598 #define MSR_IA32_MC7_CTL2 0x00000287
2599 #define MSR_IA32_MC8_CTL2 0x00000288
2600 #define MSR_IA32_MC9_CTL2 0x00000289
2601 #define MSR_IA32_MC10_CTL2 0x0000028A
2602 #define MSR_IA32_MC11_CTL2 0x0000028B
2603 #define MSR_IA32_MC12_CTL2 0x0000028C
2604 #define MSR_IA32_MC13_CTL2 0x0000028D
2605 #define MSR_IA32_MC14_CTL2 0x0000028E
2606 #define MSR_IA32_MC15_CTL2 0x0000028F
2607 #define MSR_IA32_MC16_CTL2 0x00000290
2608 #define MSR_IA32_MC17_CTL2 0x00000291
2609 #define MSR_IA32_MC18_CTL2 0x00000292
2610 #define MSR_IA32_MC19_CTL2 0x00000293
2611 #define MSR_IA32_MC20_CTL2 0x00000294
2612 #define MSR_IA32_MC21_CTL2 0x00000295
2613 #define MSR_IA32_MC22_CTL2 0x00000296
2614 #define MSR_IA32_MC23_CTL2 0x00000297
2615 #define MSR_IA32_MC24_CTL2 0x00000298
2616 #define MSR_IA32_MC25_CTL2 0x00000299
2617 #define MSR_IA32_MC26_CTL2 0x0000029A
2618 #define MSR_IA32_MC27_CTL2 0x0000029B
2619 #define MSR_IA32_MC28_CTL2 0x0000029C
2620 #define MSR_IA32_MC29_CTL2 0x0000029D
2621 #define MSR_IA32_MC30_CTL2 0x0000029E
2622 #define MSR_IA32_MC31_CTL2 0x0000029F
2626 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
2627 to #MSR_IA32_MC31_CTL2
2631 /// Individual bit fields
2635 /// [Bits 14:0] Corrected error count threshold.
2637 UINT32 CorrectedErrorCountThreshold
:15;
2638 UINT32 Reserved1
:15;
2640 /// [Bit 30] CMCI_EN.
2644 UINT32 Reserved3
:32;
2647 /// All bit fields as a 32-bit value
2651 /// All bit fields as a 64-bit value
2654 } MSR_IA32_MC_CTL2_REGISTER
;
2658 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
2660 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
2661 @param EAX Lower 32-bits of MSR value.
2662 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2663 @param EDX Upper 32-bits of MSR value.
2664 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2666 <b>Example usage</b>
2668 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
2670 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
2671 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
2673 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
2675 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2678 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
2682 /// Individual bit fields
2686 /// [Bits 2:0] Default Memory Type.
2691 /// [Bit 10] Fixed Range MTRR Enable.
2695 /// [Bit 11] MTRR Enable.
2698 UINT32 Reserved2
:20;
2699 UINT32 Reserved3
:32;
2702 /// All bit fields as a 32-bit value
2706 /// All bit fields as a 64-bit value
2709 } MSR_IA32_MTRR_DEF_TYPE_REGISTER
;
2713 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
2714 CPUID.0AH: EDX[4:0] > 0.
2716 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
2717 @param EAX Lower 32-bits of MSR value.
2718 @param EDX Upper 32-bits of MSR value.
2720 <b>Example usage</b>
2724 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
2725 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
2727 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
2729 #define MSR_IA32_FIXED_CTR0 0x00000309
2733 Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
2734 CPUID.0AH: EDX[4:0] > 1.
2736 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
2737 @param EAX Lower 32-bits of MSR value.
2738 @param EDX Upper 32-bits of MSR value.
2740 <b>Example usage</b>
2744 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
2745 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
2747 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
2749 #define MSR_IA32_FIXED_CTR1 0x0000030A
2753 Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
2754 CPUID.0AH: EDX[4:0] > 2.
2756 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
2757 @param EAX Lower 32-bits of MSR value.
2758 @param EDX Upper 32-bits of MSR value.
2760 <b>Example usage</b>
2764 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
2765 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
2767 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
2769 #define MSR_IA32_FIXED_CTR2 0x0000030B
2773 RO. If CPUID.01H: ECX[15] = 1.
2775 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
2776 @param EAX Lower 32-bits of MSR value.
2777 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2778 @param EDX Upper 32-bits of MSR value.
2779 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2781 <b>Example usage</b>
2783 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
2785 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
2786 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
2788 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
2790 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
2793 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
2797 /// Individual bit fields
2801 /// [Bits 5:0] LBR format.
2805 /// [Bit 6] PEBS Trap.
2809 /// [Bit 7] PEBSSaveArchRegs.
2811 UINT32 PEBS_ARCH_REG
:1;
2813 /// [Bits 11:8] PEBS Record Format.
2815 UINT32 PEBS_REC_FMT
:4;
2817 /// [Bit 12] 1: Freeze while SMM is supported.
2819 UINT32 SMM_FREEZE
:1;
2821 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
2824 UINT32 Reserved1
:18;
2825 UINT32 Reserved2
:32;
2828 /// All bit fields as a 32-bit value
2832 /// All bit fields as a 64-bit value
2835 } MSR_IA32_PERF_CAPABILITIES_REGISTER
;
2839 Fixed-Function Performance Counter Control (R/W) Counter increments while
2840 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
2841 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
2844 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
2845 @param EAX Lower 32-bits of MSR value.
2846 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2847 @param EDX Upper 32-bits of MSR value.
2848 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2850 <b>Example usage</b>
2852 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
2854 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
2855 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
2857 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
2859 #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2862 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
2866 /// Individual bit fields
2870 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
2874 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
2878 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
2879 /// event conditions occurring across all logical processors sharing a
2880 /// processor core. When set to 0, the counter only increments the
2881 /// associated event conditions occurring in the logical processor which
2882 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2884 UINT32 AnyThread0
:1;
2886 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
2890 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
2894 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
2898 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
2899 /// event conditions occurring across all logical processors sharing a
2900 /// processor core. When set to 0, the counter only increments the
2901 /// associated event conditions occurring in the logical processor which
2902 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2904 UINT32 AnyThread1
:1;
2906 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
2910 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
2914 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
2918 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
2919 /// event conditions occurring across all logical processors sharing a
2920 /// processor core. When set to 0, the counter only increments the
2921 /// associated event conditions occurring in the logical processor which
2922 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2924 UINT32 AnyThread2
:1;
2926 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
2929 UINT32 Reserved1
:20;
2930 UINT32 Reserved2
:32;
2933 /// All bit fields as a 32-bit value
2937 /// All bit fields as a 64-bit value
2940 } MSR_IA32_FIXED_CTR_CTRL_REGISTER
;
2944 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
2946 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
2947 @param EAX Lower 32-bits of MSR value.
2948 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2949 @param EDX Upper 32-bits of MSR value.
2950 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2952 <b>Example usage</b>
2954 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
2956 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
2958 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
2960 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2963 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
2967 /// Individual bit fields
2971 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
2976 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
2981 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
2986 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
2990 UINT32 Reserved1
:28;
2992 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
2993 /// CPUID.0AH: EAX[7:0] > 1.
2995 UINT32 Ovf_FixedCtr0
:1;
2997 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
2998 /// CPUID.0AH: EAX[7:0] > 1.
3000 UINT32 Ovf_FixedCtr1
:1;
3002 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
3003 /// CPUID.0AH: EAX[7:0] > 1.
3005 UINT32 Ovf_FixedCtr2
:1;
3006 UINT32 Reserved2
:20;
3008 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
3009 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
3010 /// && IA32_RTIT_CTL.ToPA = 1.
3012 UINT32 Trace_ToPA_PMI
:1;
3015 /// [Bit 58] LBR_Frz: LBRs are frozen due to -
3016 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
3017 /// CPUID.0AH: EAX[7:0] > 3.
3021 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
3022 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
3023 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
3027 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
3028 /// include contributions from the direct or indirect operation intel SGX
3029 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
3033 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
3036 UINT32 Ovf_Uncore
:1;
3038 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
3043 /// [Bit 63] CondChgd: status bits of this register has changed. If
3044 /// CPUID.0AH: EAX[7:0] > 0.
3049 /// All bit fields as a 64-bit value
3052 } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
;
3056 Global Performance Counter Control (R/W) Counter increments while the result
3057 of ANDing respective enable bit in this MSR with the corresponding OS or USR
3058 bits in the general-purpose or fixed counter control MSR is true. If
3059 CPUID.0AH: EAX[7:0] > 0.
3061 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
3062 @param EAX Lower 32-bits of MSR value.
3063 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3064 @param EDX Upper 32-bits of MSR value.
3065 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3067 <b>Example usage</b>
3069 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
3071 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
3072 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
3074 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
3076 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3079 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
3083 /// Individual bit fields
3087 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
3088 /// Enable bitmask. Only the first n-1 bits are valid.
3089 /// Bits n..31 are reserved.
3093 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
3094 /// Enable bitmask. Only the first n-1 bits are valid.
3095 /// Bits 31:n are reserved.
3097 UINT32 EN_FIXED_CTRn
:32;
3100 /// All bit fields as a 64-bit value
3103 } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
;
3107 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
3108 0 && CPUID.0AH: EAX[7:0] <= 3.
3110 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
3111 @param EAX Lower 32-bits of MSR value.
3112 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3113 @param EDX Upper 32-bits of MSR value.
3114 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3116 <b>Example usage</b>
3118 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
3120 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
3121 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
3123 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
3125 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3128 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
3132 /// Individual bit fields
3136 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3137 /// Clear bitmask. Only the first n-1 bits are valid.
3138 /// Bits 31:n are reserved.
3142 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3143 /// If CPUID.0AH: EDX[4:0] > n.
3144 /// Clear bitmask. Only the first n-1 bits are valid.
3145 /// Bits 22:n are reserved.
3147 UINT32 Ovf_FIXED_CTRn
:23;
3149 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3150 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
3152 UINT32 Trace_ToPA_PMI
:1;
3155 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3156 /// Display Model 06_2EH.
3158 UINT32 Ovf_Uncore
:1;
3160 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3164 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3169 /// All bit fields as a 64-bit value
3172 } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
3176 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
3179 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
3180 @param EAX Lower 32-bits of MSR value.
3181 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3182 @param EDX Upper 32-bits of MSR value.
3183 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3185 <b>Example usage</b>
3187 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
3189 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
3190 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
3192 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
3194 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3197 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
3201 /// Individual bit fields
3205 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3206 /// Clear bitmask. Only the first n-1 bits are valid.
3207 /// Bits 31:n are reserved.
3211 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3212 /// If CPUID.0AH: EDX[4:0] > n.
3213 /// Clear bitmask. Only the first n-1 bits are valid.
3214 /// Bits 22:n are reserved.
3216 UINT32 Ovf_FIXED_CTRn
:23;
3218 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3219 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
3221 UINT32 Trace_ToPA_PMI
:1;
3224 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3228 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3232 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
3236 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3237 /// Display Model 06_2EH.
3239 UINT32 Ovf_Uncore
:1;
3241 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3245 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3250 /// All bit fields as a 64-bit value
3253 } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
3257 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
3260 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
3261 @param EAX Lower 32-bits of MSR value.
3262 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3263 @param EDX Upper 32-bits of MSR value.
3264 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3266 <b>Example usage</b>
3268 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
3270 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
3271 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
3273 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
3275 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3278 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
3282 /// Individual bit fields
3286 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
3287 /// Set bitmask. Only the first n-1 bits are valid.
3288 /// Bits 31:n are reserved.
3292 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
3293 /// If CPUID.0AH: EAX[7:0] > n.
3294 /// Set bitmask. Only the first n-1 bits are valid.
3295 /// Bits 22:n are reserved.
3297 UINT32 Ovf_FIXED_CTRn
:23;
3299 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
3301 UINT32 Trace_ToPA_PMI
:1;
3304 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3308 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3312 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
3316 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
3318 UINT32 Ovf_Uncore
:1;
3320 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
3326 /// All bit fields as a 64-bit value
3329 } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
3333 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3336 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
3337 @param EAX Lower 32-bits of MSR value.
3338 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3339 @param EDX Upper 32-bits of MSR value.
3340 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3342 <b>Example usage</b>
3344 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
3346 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
3348 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
3350 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3353 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
3357 /// Individual bit fields
3361 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
3362 /// Status bitmask. Only the first n-1 bits are valid.
3363 /// Bits 31:n are reserved.
3365 UINT32 IA32_PERFEVTSELn
:32;
3367 /// [Bits 62:32] IA32_FIXED_CTRn in use.
3368 /// If CPUID.0AH: EAX[7:0] > n.
3369 /// Status bitmask. Only the first n-1 bits are valid.
3370 /// Bits 30:n are reserved.
3372 UINT32 IA32_FIXED_CTRn
:31;
3374 /// [Bit 63] PMI in use.
3379 /// All bit fields as a 64-bit value
3382 } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
;
3388 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
3389 @param EAX Lower 32-bits of MSR value.
3390 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3391 @param EDX Upper 32-bits of MSR value.
3392 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3394 <b>Example usage</b>
3396 MSR_IA32_PEBS_ENABLE_REGISTER Msr;
3398 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
3399 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
3401 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
3403 #define MSR_IA32_PEBS_ENABLE 0x000003F1
3406 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
3410 /// Individual bit fields
3414 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
3415 /// Display Model 06_0FH.
3419 /// [Bits 3:1] Reserved or Model specific.
3422 UINT32 Reserved2
:28;
3424 /// [Bits 35:32] Reserved or Model specific.
3427 UINT32 Reserved4
:28;
3430 /// All bit fields as a 64-bit value
3433 } MSR_IA32_PEBS_ENABLE_REGISTER
;
3437 MCn_CTL. If IA32_MCG_CAP.CNT > n.
3439 @param ECX MSR_IA32_MCn_CTL
3440 @param EAX Lower 32-bits of MSR value.
3441 @param EDX Upper 32-bits of MSR value.
3443 <b>Example usage</b>
3447 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
3448 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
3450 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.
3451 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.
3452 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.
3453 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.
3454 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
3455 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.
3456 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.
3457 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.
3458 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.
3459 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.
3460 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
3461 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
3462 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
3463 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
3464 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
3465 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
3466 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
3467 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
3468 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
3469 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
3470 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
3471 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
3472 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
3473 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
3474 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
3475 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
3476 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
3477 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
3478 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
3481 #define MSR_IA32_MC0_CTL 0x00000400
3482 #define MSR_IA32_MC1_CTL 0x00000404
3483 #define MSR_IA32_MC2_CTL 0x00000408
3484 #define MSR_IA32_MC3_CTL 0x0000040C
3485 #define MSR_IA32_MC4_CTL 0x00000410
3486 #define MSR_IA32_MC5_CTL 0x00000414
3487 #define MSR_IA32_MC6_CTL 0x00000418
3488 #define MSR_IA32_MC7_CTL 0x0000041C
3489 #define MSR_IA32_MC8_CTL 0x00000420
3490 #define MSR_IA32_MC9_CTL 0x00000424
3491 #define MSR_IA32_MC10_CTL 0x00000428
3492 #define MSR_IA32_MC11_CTL 0x0000042C
3493 #define MSR_IA32_MC12_CTL 0x00000430
3494 #define MSR_IA32_MC13_CTL 0x00000434
3495 #define MSR_IA32_MC14_CTL 0x00000438
3496 #define MSR_IA32_MC15_CTL 0x0000043C
3497 #define MSR_IA32_MC16_CTL 0x00000440
3498 #define MSR_IA32_MC17_CTL 0x00000444
3499 #define MSR_IA32_MC18_CTL 0x00000448
3500 #define MSR_IA32_MC19_CTL 0x0000044C
3501 #define MSR_IA32_MC20_CTL 0x00000450
3502 #define MSR_IA32_MC21_CTL 0x00000454
3503 #define MSR_IA32_MC22_CTL 0x00000458
3504 #define MSR_IA32_MC23_CTL 0x0000045C
3505 #define MSR_IA32_MC24_CTL 0x00000460
3506 #define MSR_IA32_MC25_CTL 0x00000464
3507 #define MSR_IA32_MC26_CTL 0x00000468
3508 #define MSR_IA32_MC27_CTL 0x0000046C
3509 #define MSR_IA32_MC28_CTL 0x00000470
3514 MCn_STATUS. If IA32_MCG_CAP.CNT > n.
3516 @param ECX MSR_IA32_MCn_STATUS
3517 @param EAX Lower 32-bits of MSR value.
3518 @param EDX Upper 32-bits of MSR value.
3520 <b>Example usage</b>
3524 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
3525 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
3527 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.
3528 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.
3529 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.
3530 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.
3531 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.
3532 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.
3533 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.
3534 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.
3535 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.
3536 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.
3537 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
3538 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
3539 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
3540 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
3541 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
3542 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
3543 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
3544 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
3545 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
3546 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
3547 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
3548 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
3549 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
3550 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
3551 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
3552 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
3553 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
3554 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
3555 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
3558 #define MSR_IA32_MC0_STATUS 0x00000401
3559 #define MSR_IA32_MC1_STATUS 0x00000405
3560 #define MSR_IA32_MC2_STATUS 0x00000409
3561 #define MSR_IA32_MC3_STATUS 0x0000040D
3562 #define MSR_IA32_MC4_STATUS 0x00000411
3563 #define MSR_IA32_MC5_STATUS 0x00000415
3564 #define MSR_IA32_MC6_STATUS 0x00000419
3565 #define MSR_IA32_MC7_STATUS 0x0000041D
3566 #define MSR_IA32_MC8_STATUS 0x00000421
3567 #define MSR_IA32_MC9_STATUS 0x00000425
3568 #define MSR_IA32_MC10_STATUS 0x00000429
3569 #define MSR_IA32_MC11_STATUS 0x0000042D
3570 #define MSR_IA32_MC12_STATUS 0x00000431
3571 #define MSR_IA32_MC13_STATUS 0x00000435
3572 #define MSR_IA32_MC14_STATUS 0x00000439
3573 #define MSR_IA32_MC15_STATUS 0x0000043D
3574 #define MSR_IA32_MC16_STATUS 0x00000441
3575 #define MSR_IA32_MC17_STATUS 0x00000445
3576 #define MSR_IA32_MC18_STATUS 0x00000449
3577 #define MSR_IA32_MC19_STATUS 0x0000044D
3578 #define MSR_IA32_MC20_STATUS 0x00000451
3579 #define MSR_IA32_MC21_STATUS 0x00000455
3580 #define MSR_IA32_MC22_STATUS 0x00000459
3581 #define MSR_IA32_MC23_STATUS 0x0000045D
3582 #define MSR_IA32_MC24_STATUS 0x00000461
3583 #define MSR_IA32_MC25_STATUS 0x00000465
3584 #define MSR_IA32_MC26_STATUS 0x00000469
3585 #define MSR_IA32_MC27_STATUS 0x0000046D
3586 #define MSR_IA32_MC28_STATUS 0x00000471
3591 MCn_ADDR. If IA32_MCG_CAP.CNT > n.
3593 @param ECX MSR_IA32_MCn_ADDR
3594 @param EAX Lower 32-bits of MSR value.
3595 @param EDX Upper 32-bits of MSR value.
3597 <b>Example usage</b>
3601 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
3602 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
3604 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.
3605 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.
3606 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.
3607 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.
3608 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.
3609 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.
3610 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.
3611 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.
3612 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.
3613 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.
3614 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
3615 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
3616 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
3617 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
3618 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
3619 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
3620 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
3621 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
3622 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
3623 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
3624 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
3625 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
3626 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
3627 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
3628 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
3629 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
3630 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
3631 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
3632 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
3635 #define MSR_IA32_MC0_ADDR 0x00000402
3636 #define MSR_IA32_MC1_ADDR 0x00000406
3637 #define MSR_IA32_MC2_ADDR 0x0000040A
3638 #define MSR_IA32_MC3_ADDR 0x0000040E
3639 #define MSR_IA32_MC4_ADDR 0x00000412
3640 #define MSR_IA32_MC5_ADDR 0x00000416
3641 #define MSR_IA32_MC6_ADDR 0x0000041A
3642 #define MSR_IA32_MC7_ADDR 0x0000041E
3643 #define MSR_IA32_MC8_ADDR 0x00000422
3644 #define MSR_IA32_MC9_ADDR 0x00000426
3645 #define MSR_IA32_MC10_ADDR 0x0000042A
3646 #define MSR_IA32_MC11_ADDR 0x0000042E
3647 #define MSR_IA32_MC12_ADDR 0x00000432
3648 #define MSR_IA32_MC13_ADDR 0x00000436
3649 #define MSR_IA32_MC14_ADDR 0x0000043A
3650 #define MSR_IA32_MC15_ADDR 0x0000043E
3651 #define MSR_IA32_MC16_ADDR 0x00000442
3652 #define MSR_IA32_MC17_ADDR 0x00000446
3653 #define MSR_IA32_MC18_ADDR 0x0000044A
3654 #define MSR_IA32_MC19_ADDR 0x0000044E
3655 #define MSR_IA32_MC20_ADDR 0x00000452
3656 #define MSR_IA32_MC21_ADDR 0x00000456
3657 #define MSR_IA32_MC22_ADDR 0x0000045A
3658 #define MSR_IA32_MC23_ADDR 0x0000045E
3659 #define MSR_IA32_MC24_ADDR 0x00000462
3660 #define MSR_IA32_MC25_ADDR 0x00000466
3661 #define MSR_IA32_MC26_ADDR 0x0000046A
3662 #define MSR_IA32_MC27_ADDR 0x0000046E
3663 #define MSR_IA32_MC28_ADDR 0x00000472
3668 MCn_MISC. If IA32_MCG_CAP.CNT > n.
3670 @param ECX MSR_IA32_MCn_MISC
3671 @param EAX Lower 32-bits of MSR value.
3672 @param EDX Upper 32-bits of MSR value.
3674 <b>Example usage</b>
3678 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
3679 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
3681 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.
3682 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.
3683 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.
3684 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.
3685 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.
3686 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.
3687 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
3688 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.
3689 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.
3690 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.
3691 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
3692 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
3693 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
3694 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
3695 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
3696 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
3697 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
3698 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
3699 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
3700 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
3701 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
3702 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
3703 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
3704 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
3705 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
3706 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
3707 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
3708 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
3709 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
3712 #define MSR_IA32_MC0_MISC 0x00000403
3713 #define MSR_IA32_MC1_MISC 0x00000407
3714 #define MSR_IA32_MC2_MISC 0x0000040B
3715 #define MSR_IA32_MC3_MISC 0x0000040F
3716 #define MSR_IA32_MC4_MISC 0x00000413
3717 #define MSR_IA32_MC5_MISC 0x00000417
3718 #define MSR_IA32_MC6_MISC 0x0000041B
3719 #define MSR_IA32_MC7_MISC 0x0000041F
3720 #define MSR_IA32_MC8_MISC 0x00000423
3721 #define MSR_IA32_MC9_MISC 0x00000427
3722 #define MSR_IA32_MC10_MISC 0x0000042B
3723 #define MSR_IA32_MC11_MISC 0x0000042F
3724 #define MSR_IA32_MC12_MISC 0x00000433
3725 #define MSR_IA32_MC13_MISC 0x00000437
3726 #define MSR_IA32_MC14_MISC 0x0000043B
3727 #define MSR_IA32_MC15_MISC 0x0000043F
3728 #define MSR_IA32_MC16_MISC 0x00000443
3729 #define MSR_IA32_MC17_MISC 0x00000447
3730 #define MSR_IA32_MC18_MISC 0x0000044B
3731 #define MSR_IA32_MC19_MISC 0x0000044F
3732 #define MSR_IA32_MC20_MISC 0x00000453
3733 #define MSR_IA32_MC21_MISC 0x00000457
3734 #define MSR_IA32_MC22_MISC 0x0000045B
3735 #define MSR_IA32_MC23_MISC 0x0000045F
3736 #define MSR_IA32_MC24_MISC 0x00000463
3737 #define MSR_IA32_MC25_MISC 0x00000467
3738 #define MSR_IA32_MC26_MISC 0x0000046B
3739 #define MSR_IA32_MC27_MISC 0x0000046F
3740 #define MSR_IA32_MC28_MISC 0x00000473
3745 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
3746 VMX Information.". If CPUID.01H:ECX.[5] = 1.
3748 @param ECX MSR_IA32_VMX_BASIC (0x00000480)
3749 @param EAX Lower 32-bits of MSR value.
3750 @param EDX Upper 32-bits of MSR value.
3752 <b>Example usage</b>
3754 MSR_IA32_VMX_BASIC_REGISTER Msr;
3756 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
3758 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
3760 #define MSR_IA32_VMX_BASIC 0x00000480
3763 MSR information returned for MSR index #MSR_IA32_VMX_BASIC
3767 /// Individual bit fields
3771 /// [Bits 30:0] VMCS revision identifier used by the processor. Processors
3772 /// that use the same VMCS revision identifier use the same size for VMCS
3773 /// regions (see subsequent item on bits 44:32).
3775 /// @note Earlier versions of this manual specified that the VMCS revision
3776 /// identifier was a 32-bit field in bits 31:0 of this MSR. For all
3777 /// processors produced prior to this change, bit 31 of this MSR was read
3780 UINT32 VmcsRevisonId
:31;
3781 UINT32 MustBeZero
:1;
3783 /// [Bit 44:32] Reports the number of bytes that software should allocate
3784 /// for the VMXON region and any VMCS region. It is a value greater than
3785 /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
3790 /// [Bit 48] Indicates the width of the physical addresses that may be used
3791 /// for the VMXON region, each VMCS, and data structures referenced by
3792 /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
3793 /// transitions). If the bit is 0, these addresses are limited to the
3794 /// processor's physical-address width. If the bit is 1, these addresses
3795 /// are limited to 32 bits. This bit is always 0 for processors that
3796 /// support Intel 64 architecture.
3798 /// @note On processors that support Intel 64 architecture, the pointer
3799 /// must not set bits beyond the processor's physical address width.
3801 UINT32 VmcsAddressWidth
:1;
3803 /// [Bit 49] If bit 49 is read as 1, the logical processor supports the
3804 /// dual-monitor treatment of system-management interrupts and
3805 /// system-management mode. See Section 34.15 for details of this treatment.
3807 UINT32 DualMonitor
:1;
3809 /// [Bit 53:50] report the memory type that should be used for the VMCS,
3810 /// for data structures referenced by pointers in the VMCS (I/O bitmaps,
3811 /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
3812 /// header. If software needs to access these data structures (e.g., to
3813 /// modify the contents of the MSR bitmaps), it can configure the paging
3814 /// structures to map them into the linear-address space. If it does so,
3815 /// it should establish mappings that use the memory type reported bits
3816 /// 53:50 in this MSR.
3818 /// As of this writing, all processors that support VMX operation indicate
3819 /// the write-back type.
3821 /// If software needs to access these data structures (e.g., to modify
3822 /// the contents of the MSR bitmaps), it can configure the paging
3823 /// structures to map them into the linear-address space. If it does so,
3824 /// it should establish mappings that use the memory type reported in this
3827 /// @note Alternatively, software may map any of these regions or
3828 /// structures with the UC memory type. (This may be necessary for the MSEG
3829 /// header.) Doing so is discouraged unless necessary as it will cause the
3830 /// performance of software accesses to those structures to suffer.
3833 UINT32 MemoryType
:4;
3835 /// [Bit 54] If bit 54 is read as 1, the processor reports information in
3836 /// the VM-exit instruction-information field on VM exitsdue to execution
3837 /// of the INS and OUTS instructions (see Section 27.2.4). This reporting
3838 /// is done only if this bit is read as 1.
3840 UINT32 InsOutsReporting
:1;
3842 /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
3843 /// be cleared to 0. See Appendix A.2 for details. It also reports support
3844 /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
3845 /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
3846 /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
3847 /// Appendix A.4, and Appendix A.5 for details.
3849 UINT32 VmxControls
:1;
3853 /// All bit fields as a 64-bit value
3856 } MSR_IA32_VMX_BASIC_REGISTER
;
3859 /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType
3861 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3862 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3869 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
3870 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
3872 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
3873 @param EAX Lower 32-bits of MSR value.
3874 @param EDX Upper 32-bits of MSR value.
3876 <b>Example usage</b>
3880 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
3882 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
3884 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3888 Capability Reporting Register of Primary Processor-based VM-execution
3889 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3890 Controls.". If CPUID.01H:ECX.[5] = 1.
3892 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
3893 @param EAX Lower 32-bits of MSR value.
3894 @param EDX Upper 32-bits of MSR value.
3896 <b>Example usage</b>
3900 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
3902 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
3904 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3908 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
3909 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
3911 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
3912 @param EAX Lower 32-bits of MSR value.
3913 @param EDX Upper 32-bits of MSR value.
3915 <b>Example usage</b>
3919 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
3921 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
3923 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3927 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
3928 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
3930 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
3931 @param EAX Lower 32-bits of MSR value.
3932 @param EDX Upper 32-bits of MSR value.
3934 <b>Example usage</b>
3938 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
3940 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
3942 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3946 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
3947 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
3949 @param ECX MSR_IA32_VMX_MISC (0x00000485)
3950 @param EAX Lower 32-bits of MSR value.
3951 @param EDX Upper 32-bits of MSR value.
3953 <b>Example usage</b>
3955 IA32_VMX_MISC_REGISTER Msr;
3957 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
3959 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
3961 #define MSR_IA32_VMX_MISC 0x00000485
3964 MSR information returned for MSR index #IA32_VMX_MISC
3968 /// Individual bit fields
3972 /// [Bits 4:0] Reports a value X that specifies the relationship between the
3973 /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).
3974 /// Specifically, the VMX-preemption timer (if it is active) counts down by
3975 /// 1 every time bit X in the TSC changes due to a TSC increment.
3977 UINT32 VmxTimerRatio
:5;
3979 /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
3980 /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
3981 /// details. This bit is read as 1 on any logical processor that supports
3982 /// the 1-setting of the "unrestricted guest" VM-execution control.
3984 UINT32 VmExitEferLma
:1;
3986 /// [Bit 6] reports (if set) the support for activity state 1 (HLT).
3988 UINT32 HltActivityStateSupported
:1;
3990 /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
3992 UINT32 ShutdownActivityStateSupported
:1;
3994 /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
3996 UINT32 WaitForSipiActivityStateSupported
:1;
3999 /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
4000 /// in VMX operation. If the processor supports Intel PT but does not allow
4001 /// it to be used in VMX operation, execution of VMXON clears
4002 /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);
4003 /// any attempt to set that bit while in VMX operation (including VMX root
4004 /// operation) using the WRMSR instruction causes a general-protection
4007 UINT32 ProcessorTraceSupported
:1;
4009 /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
4010 /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
4011 /// See Section 34.15.6.3.
4013 UINT32 SmBaseMsrSupported
:1;
4015 /// [Bits 24:16] Indicate the number of CR3-target values supported by the
4016 /// processor. This number is a value between 0 and 256, inclusive (bit 24
4017 /// is set if and only if bits 23:16 are clear).
4019 UINT32 NumberOfCr3TargetValues
:9;
4021 /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
4022 /// number of MSRs that should appear in the VM-exit MSR-store list, the
4023 /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if
4024 /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the
4025 /// recommended maximum number of MSRs to be included in each list. If the
4026 /// limit is exceeded, undefined processor behavior may result (including a
4027 /// machine check during the VMX transition).
4029 UINT32 MsrStoreListMaximum
:3;
4031 /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
4032 /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
4033 /// (see Section 34.14.4).
4035 UINT32 BlockSmiSupported
:1;
4037 /// [Bit 29] read as 1, software can use VMWRITE to write to any supported
4038 /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
4039 /// information fields.
4041 UINT32 VmWriteSupported
:1;
4043 /// [Bit 30] If read as 1, VM entry allows injection of a software
4044 /// interrupt, software exception, or privileged software exception with an
4045 /// instruction length of 0.
4047 UINT32 VmInjectSupported
:1;
4050 /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
4053 UINT32 MsegRevisionIdentifier
:32;
4056 /// All bit fields as a 64-bit value
4059 } IA32_VMX_MISC_REGISTER
;
4063 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
4064 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4066 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
4067 @param EAX Lower 32-bits of MSR value.
4068 @param EDX Upper 32-bits of MSR value.
4070 <b>Example usage</b>
4074 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
4076 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
4078 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4082 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
4083 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4085 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
4086 @param EAX Lower 32-bits of MSR value.
4087 @param EDX Upper 32-bits of MSR value.
4089 <b>Example usage</b>
4093 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
4095 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
4097 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4101 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
4102 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4104 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
4105 @param EAX Lower 32-bits of MSR value.
4106 @param EDX Upper 32-bits of MSR value.
4108 <b>Example usage</b>
4112 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
4114 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
4116 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4120 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
4121 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4123 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
4124 @param EAX Lower 32-bits of MSR value.
4125 @param EDX Upper 32-bits of MSR value.
4127 <b>Example usage</b>
4131 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
4133 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
4135 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4139 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
4140 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
4142 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
4143 @param EAX Lower 32-bits of MSR value.
4144 @param EDX Upper 32-bits of MSR value.
4146 <b>Example usage</b>
4150 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
4152 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
4154 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4158 Capability Reporting Register of Secondary Processor-based VM-execution
4159 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
4160 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
4162 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
4163 @param EAX Lower 32-bits of MSR value.
4164 @param EDX Upper 32-bits of MSR value.
4166 <b>Example usage</b>
4170 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
4172 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
4174 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4178 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
4179 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
4180 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
4182 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
4183 @param EAX Lower 32-bits of MSR value.
4184 @param EDX Upper 32-bits of MSR value.
4186 <b>Example usage</b>
4190 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
4192 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
4194 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4198 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
4199 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
4200 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4202 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
4203 @param EAX Lower 32-bits of MSR value.
4204 @param EDX Upper 32-bits of MSR value.
4206 <b>Example usage</b>
4210 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
4212 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
4214 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4218 Capability Reporting Register of Primary Processor-based VM-execution Flex
4219 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
4220 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4222 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
4223 @param EAX Lower 32-bits of MSR value.
4224 @param EDX Upper 32-bits of MSR value.
4226 <b>Example usage</b>
4230 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
4232 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
4234 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4238 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
4239 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4241 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
4242 @param EAX Lower 32-bits of MSR value.
4243 @param EDX Upper 32-bits of MSR value.
4245 <b>Example usage</b>
4249 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
4251 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
4253 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4257 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
4258 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4260 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
4261 @param EAX Lower 32-bits of MSR value.
4262 @param EDX Upper 32-bits of MSR value.
4264 <b>Example usage</b>
4268 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
4270 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
4272 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4276 Capability Reporting Register of VMfunction Controls (R/O). If(
4277 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4279 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
4280 @param EAX Lower 32-bits of MSR value.
4281 @param EDX Upper 32-bits of MSR value.
4283 <b>Example usage</b>
4287 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
4289 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
4291 #define MSR_IA32_VMX_VMFUNC 0x00000491
4295 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
4296 IA32_PERF_CAPABILITIES[ 13] = 1.
4298 @param ECX MSR_IA32_A_PMCn
4299 @param EAX Lower 32-bits of MSR value.
4300 @param EDX Upper 32-bits of MSR value.
4302 <b>Example usage</b>
4306 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
4307 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
4309 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
4310 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
4311 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
4312 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
4313 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
4314 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
4315 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
4316 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
4319 #define MSR_IA32_A_PMC0 0x000004C1
4320 #define MSR_IA32_A_PMC1 0x000004C2
4321 #define MSR_IA32_A_PMC2 0x000004C3
4322 #define MSR_IA32_A_PMC3 0x000004C4
4323 #define MSR_IA32_A_PMC4 0x000004C5
4324 #define MSR_IA32_A_PMC5 0x000004C6
4325 #define MSR_IA32_A_PMC6 0x000004C7
4326 #define MSR_IA32_A_PMC7 0x000004C8
4331 (R/W). If IA32_MCG_CAP.LMCE_P =1.
4333 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
4334 @param EAX Lower 32-bits of MSR value.
4335 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4336 @param EDX Upper 32-bits of MSR value.
4337 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4339 <b>Example usage</b>
4341 MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
4343 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
4344 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
4346 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
4348 #define MSR_IA32_MCG_EXT_CTL 0x000004D0
4351 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
4355 /// Individual bit fields
4359 /// [Bit 0] LMCE_EN.
4362 UINT32 Reserved1
:31;
4363 UINT32 Reserved2
:32;
4366 /// All bit fields as a 32-bit value
4370 /// All bit fields as a 64-bit value
4373 } MSR_IA32_MCG_EXT_CTL_REGISTER
;
4377 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
4378 ECX=0H): EBX[2] = 1.
4380 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
4381 @param EAX Lower 32-bits of MSR value.
4382 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4383 @param EDX Upper 32-bits of MSR value.
4384 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4386 <b>Example usage</b>
4388 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
4390 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
4392 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
4394 #define MSR_IA32_SGX_SVN_STATUS 0x00000500
4397 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
4401 /// Individual bit fields
4405 /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
4406 /// Code Modules (ACMs)".
4409 UINT32 Reserved1
:15;
4411 /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
4412 /// Authenticated Code Modules (ACMs)".
4414 UINT32 SGX_SVN_SINIT
:8;
4416 UINT32 Reserved3
:32;
4419 /// All bit fields as a 32-bit value
4423 /// All bit fields as a 64-bit value
4426 } MSR_IA32_SGX_SVN_STATUS_REGISTER
;
4430 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
4431 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
4434 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
4435 @param EAX Lower 32-bits of MSR value.
4436 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4437 @param EDX Upper 32-bits of MSR value.
4438 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4440 <b>Example usage</b>
4442 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
4444 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
4445 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
4447 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
4449 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4452 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
4456 /// Individual bit fields
4461 /// [Bits 31:7] Base physical address.
4465 /// [Bits 63:32] Base physical address.
4470 /// All bit fields as a 64-bit value
4473 } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
;
4477 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
4478 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
4479 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
4481 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
4482 @param EAX Lower 32-bits of MSR value.
4483 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4484 @param EDX Upper 32-bits of MSR value.
4485 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4487 <b>Example usage</b>
4489 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
4491 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
4492 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
4494 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
4496 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4499 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
4503 /// Individual bit fields
4508 /// [Bits 31:7] MaskOrTableOffset.
4510 UINT32 MaskOrTableOffset
:25;
4512 /// [Bits 63:32] Output Offset.
4514 UINT32 OutputOffset
:32;
4517 /// All bit fields as a 64-bit value
4520 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
;
4523 Format of ToPA table entries.
4527 /// Individual bit fields
4531 /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4536 /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4541 /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4546 /// [Bit 6:9] Indicates the size of the associated output region. See Section
4547 /// 35.2.6.2, "Table of Physical Addresses (ToPA)".
4552 /// [Bit 12:31] Output Region Base Physical Address low part.
4553 /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.
4554 /// ATTENTION: The size of the address field is determined by the processor's
4555 /// physical-address width (MAXPHYADDR) in bits, as reported in
4556 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
4557 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
4558 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4562 /// [Bit 32:63] Output Region Base Physical Address high part.
4563 /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.
4564 /// ATTENTION: The size of the address field is determined by the processor's
4565 /// physical-address width (MAXPHYADDR) in bits, as reported in
4566 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
4567 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
4568 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4573 /// All bit fields as a 64-bit value
4576 } RTIT_TOPA_TABLE_ENTRY
;
4579 /// The size of the associated output region usd by Topa.
4582 RtitTopaMemorySize4K
= 0,
4583 RtitTopaMemorySize8K
,
4584 RtitTopaMemorySize16K
,
4585 RtitTopaMemorySize32K
,
4586 RtitTopaMemorySize64K
,
4587 RtitTopaMemorySize128K
,
4588 RtitTopaMemorySize256K
,
4589 RtitTopaMemorySize512K
,
4590 RtitTopaMemorySize1M
,
4591 RtitTopaMemorySize2M
,
4592 RtitTopaMemorySize4M
,
4593 RtitTopaMemorySize8M
,
4594 RtitTopaMemorySize16M
,
4595 RtitTopaMemorySize32M
,
4596 RtitTopaMemorySize64M
,
4597 RtitTopaMemorySize128M
4598 } RTIT_TOPA_MEMORY_SIZE
;
4601 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4603 @param ECX MSR_IA32_RTIT_CTL (0x00000570)
4604 @param EAX Lower 32-bits of MSR value.
4605 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4606 @param EDX Upper 32-bits of MSR value.
4607 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4609 <b>Example usage</b>
4611 MSR_IA32_RTIT_CTL_REGISTER Msr;
4613 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
4614 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
4616 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
4618 #define MSR_IA32_RTIT_CTL 0x00000570
4621 MSR information returned for MSR index #MSR_IA32_RTIT_CTL
4625 /// Individual bit fields
4629 /// [Bit 0] TraceEn.
4633 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4645 /// [Bit 4] PwrEvtEn.
4649 /// [Bit 5] FUPonPTW.
4653 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
4657 /// [Bit 7] CR3 filter.
4665 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4673 /// [Bit 11] DisRETC.
4681 /// [Bit 13] BranchEn.
4685 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4690 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4695 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4700 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
4704 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
4708 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
4712 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
4715 UINT32 Reserved6
:16;
4718 /// All bit fields as a 64-bit value
4721 } MSR_IA32_RTIT_CTL_REGISTER
;
4725 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4727 @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
4728 @param EAX Lower 32-bits of MSR value.
4729 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4730 @param EDX Upper 32-bits of MSR value.
4731 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4733 <b>Example usage</b>
4735 MSR_IA32_RTIT_STATUS_REGISTER Msr;
4737 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
4738 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
4740 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
4742 #define MSR_IA32_RTIT_STATUS 0x00000571
4745 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
4749 /// Individual bit fields
4753 /// [Bit 0] FilterEn, (writes ignored).
4754 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
4758 /// [Bit 1] ContexEn, (writes ignored).
4762 /// [Bit 2] TriggerEn, (writes ignored).
4771 /// [Bit 5] Stopped.
4774 UINT32 Reserved2
:26;
4776 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
4778 UINT32 PacketByteCnt
:17;
4779 UINT32 Reserved3
:15;
4782 /// All bit fields as a 64-bit value
4785 } MSR_IA32_RTIT_STATUS_REGISTER
;
4789 Trace Filter CR3 Match Register (R/W).
4790 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4792 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
4793 @param EAX Lower 32-bits of MSR value.
4794 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4795 @param EDX Upper 32-bits of MSR value.
4796 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4798 <b>Example usage</b>
4800 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
4802 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
4803 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
4805 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
4807 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4810 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
4814 /// Individual bit fields
4819 /// [Bits 31:5] CR3[63:5] value to match.
4823 /// [Bits 63:32] CR3[63:5] value to match.
4828 /// All bit fields as a 64-bit value
4831 } MSR_IA32_RTIT_CR3_MATCH_REGISTER
;
4835 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4837 @param ECX MSR_IA32_RTIT_ADDRn_A
4838 @param EAX Lower 32-bits of MSR value.
4839 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4840 @param EDX Upper 32-bits of MSR value.
4841 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4843 <b>Example usage</b>
4845 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4847 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
4848 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
4850 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
4851 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
4852 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
4853 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
4856 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
4857 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
4858 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
4859 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
4864 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4866 @param ECX MSR_IA32_RTIT_ADDRn_B
4867 @param EAX Lower 32-bits of MSR value.
4868 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4869 @param EDX Upper 32-bits of MSR value.
4870 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4872 <b>Example usage</b>
4874 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4876 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
4877 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
4879 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
4880 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
4881 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
4882 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
4885 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
4886 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
4887 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
4888 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
4893 MSR information returned for MSR indexes
4894 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
4895 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
4899 /// Individual bit fields
4903 /// [Bits 31:0] Virtual Address.
4905 UINT32 VirtualAddress
:32;
4907 /// [Bits 47:32] Virtual Address.
4909 UINT32 VirtualAddressHi
:16;
4911 /// [Bits 63:48] SignExt_VA.
4913 UINT32 SignExt_VA
:16;
4916 /// All bit fields as a 64-bit value
4919 } MSR_IA32_RTIT_ADDR_REGISTER
;
4923 DS Save Area (R/W) Points to the linear address of the first byte of the DS
4924 buffer management area, which is used to manage the BTS and PEBS buffers.
4925 See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(
4926 CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS
4927 buffer management area, if IA-32e mode is active.
4929 @param ECX MSR_IA32_DS_AREA (0x00000600)
4930 @param EAX Lower 32-bits of MSR value.
4931 Described by the type MSR_IA32_DS_AREA_REGISTER.
4932 @param EDX Upper 32-bits of MSR value.
4933 Described by the type MSR_IA32_DS_AREA_REGISTER.
4935 <b>Example usage</b>
4939 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
4940 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
4942 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
4944 #define MSR_IA32_DS_AREA 0x00000600
4948 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
4951 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
4952 @param EAX Lower 32-bits of MSR value.
4953 @param EDX Upper 32-bits of MSR value.
4955 <b>Example usage</b>
4959 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
4960 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
4962 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
4964 #define MSR_IA32_TSC_DEADLINE 0x000006E0
4968 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
4970 @param ECX MSR_IA32_PM_ENABLE (0x00000770)
4971 @param EAX Lower 32-bits of MSR value.
4972 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4973 @param EDX Upper 32-bits of MSR value.
4974 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4976 <b>Example usage</b>
4978 MSR_IA32_PM_ENABLE_REGISTER Msr;
4980 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
4981 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
4983 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
4985 #define MSR_IA32_PM_ENABLE 0x00000770
4988 MSR information returned for MSR index #MSR_IA32_PM_ENABLE
4992 /// Individual bit fields
4996 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
4997 /// CPUID.06H:EAX.[7] = 1.
4999 UINT32 HWP_ENABLE
:1;
5000 UINT32 Reserved1
:31;
5001 UINT32 Reserved2
:32;
5004 /// All bit fields as a 32-bit value
5008 /// All bit fields as a 64-bit value
5011 } MSR_IA32_PM_ENABLE_REGISTER
;
5015 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
5017 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
5018 @param EAX Lower 32-bits of MSR value.
5019 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
5020 @param EDX Upper 32-bits of MSR value.
5021 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
5023 <b>Example usage</b>
5025 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
5027 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
5029 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
5031 #define MSR_IA32_HWP_CAPABILITIES 0x00000771
5034 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
5038 /// Individual bit fields
5042 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
5043 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
5045 UINT32 Highest_Performance
:8;
5047 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
5048 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
5050 UINT32 Guaranteed_Performance
:8;
5052 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
5053 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
5055 UINT32 Most_Efficient_Performance
:8;
5057 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
5058 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
5060 UINT32 Lowest_Performance
:8;
5064 /// All bit fields as a 32-bit value
5068 /// All bit fields as a 64-bit value
5071 } MSR_IA32_HWP_CAPABILITIES_REGISTER
;
5075 Power Management Control Hints for All Logical Processors in a Package
5076 (R/W). If CPUID.06H:EAX.[11] = 1.
5078 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
5079 @param EAX Lower 32-bits of MSR value.
5080 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
5081 @param EDX Upper 32-bits of MSR value.
5082 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
5084 <b>Example usage</b>
5086 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
5088 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
5089 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
5091 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
5093 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772
5096 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
5100 /// Individual bit fields
5104 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5105 /// CPUID.06H:EAX.[11] = 1.
5107 UINT32 Minimum_Performance
:8;
5109 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5110 /// CPUID.06H:EAX.[11] = 1.
5112 UINT32 Maximum_Performance
:8;
5114 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5115 /// If CPUID.06H:EAX.[11] = 1.
5117 UINT32 Desired_Performance
:8;
5119 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5120 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
5122 UINT32 Energy_Performance_Preference
:8;
5124 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5125 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
5127 UINT32 Activity_Window
:10;
5131 /// All bit fields as a 64-bit value
5134 } MSR_IA32_HWP_REQUEST_PKG_REGISTER
;
5138 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
5140 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
5141 @param EAX Lower 32-bits of MSR value.
5142 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5143 @param EDX Upper 32-bits of MSR value.
5144 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5146 <b>Example usage</b>
5148 MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
5150 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
5151 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
5153 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
5155 #define MSR_IA32_HWP_INTERRUPT 0x00000773
5158 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
5162 /// Individual bit fields
5166 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
5167 /// Notifications". If CPUID.06H:EAX.[8] = 1.
5169 UINT32 EN_Guaranteed_Performance_Change
:1;
5171 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
5172 /// If CPUID.06H:EAX.[8] = 1.
5174 UINT32 EN_Excursion_Minimum
:1;
5175 UINT32 Reserved1
:30;
5176 UINT32 Reserved2
:32;
5179 /// All bit fields as a 32-bit value
5183 /// All bit fields as a 64-bit value
5186 } MSR_IA32_HWP_INTERRUPT_REGISTER
;
5190 Power Management Control Hints to a Logical Processor (R/W). If
5191 CPUID.06H:EAX.[7] = 1.
5193 @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
5194 @param EAX Lower 32-bits of MSR value.
5195 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5196 @param EDX Upper 32-bits of MSR value.
5197 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5199 <b>Example usage</b>
5201 MSR_IA32_HWP_REQUEST_REGISTER Msr;
5203 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
5204 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
5206 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
5208 #define MSR_IA32_HWP_REQUEST 0x00000774
5211 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
5215 /// Individual bit fields
5219 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5220 /// CPUID.06H:EAX.[7] = 1.
5222 UINT32 Minimum_Performance
:8;
5224 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5225 /// CPUID.06H:EAX.[7] = 1.
5227 UINT32 Maximum_Performance
:8;
5229 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5230 /// If CPUID.06H:EAX.[7] = 1.
5232 UINT32 Desired_Performance
:8;
5234 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5235 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
5237 UINT32 Energy_Performance_Preference
:8;
5239 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5240 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
5242 UINT32 Activity_Window
:10;
5244 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
5245 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
5247 UINT32 Package_Control
:1;
5251 /// All bit fields as a 64-bit value
5254 } MSR_IA32_HWP_REQUEST_REGISTER
;
5258 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
5259 CPUID.06H:EAX.[7] = 1.
5261 @param ECX MSR_IA32_HWP_STATUS (0x00000777)
5262 @param EAX Lower 32-bits of MSR value.
5263 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5264 @param EDX Upper 32-bits of MSR value.
5265 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5267 <b>Example usage</b>
5269 MSR_IA32_HWP_STATUS_REGISTER Msr;
5271 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
5272 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
5274 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
5276 #define MSR_IA32_HWP_STATUS 0x00000777
5279 MSR information returned for MSR index #MSR_IA32_HWP_STATUS
5283 /// Individual bit fields
5287 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
5288 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
5290 UINT32 Guaranteed_Performance_Change
:1;
5293 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
5294 /// Feedback". If CPUID.06H:EAX.[7] = 1.
5296 UINT32 Excursion_To_Minimum
:1;
5297 UINT32 Reserved2
:29;
5298 UINT32 Reserved3
:32;
5301 /// All bit fields as a 32-bit value
5305 /// All bit fields as a 64-bit value
5308 } MSR_IA32_HWP_STATUS_REGISTER
;
5312 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
5313 && IA32_APIC_BASE.[10] = 1.
5315 @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
5316 @param EAX Lower 32-bits of MSR value.
5317 @param EDX Upper 32-bits of MSR value.
5319 <b>Example usage</b>
5323 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
5325 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
5327 #define MSR_IA32_X2APIC_APICID 0x00000802
5331 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5332 IA32_APIC_BASE.[10] = 1.
5334 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
5335 @param EAX Lower 32-bits of MSR value.
5336 @param EDX Upper 32-bits of MSR value.
5338 <b>Example usage</b>
5342 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
5344 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
5346 #define MSR_IA32_X2APIC_VERSION 0x00000803
5350 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5351 IA32_APIC_BASE.[10] = 1.
5353 @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
5354 @param EAX Lower 32-bits of MSR value.
5355 @param EDX Upper 32-bits of MSR value.
5357 <b>Example usage</b>
5361 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
5362 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
5364 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
5366 #define MSR_IA32_X2APIC_TPR 0x00000808
5370 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5371 IA32_APIC_BASE.[10] = 1.
5373 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
5374 @param EAX Lower 32-bits of MSR value.
5375 @param EDX Upper 32-bits of MSR value.
5377 <b>Example usage</b>
5381 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
5383 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
5385 #define MSR_IA32_X2APIC_PPR 0x0000080A
5389 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
5392 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
5393 @param EAX Lower 32-bits of MSR value.
5394 @param EDX Upper 32-bits of MSR value.
5396 <b>Example usage</b>
5401 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
5403 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
5405 #define MSR_IA32_X2APIC_EOI 0x0000080B
5409 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5410 IA32_APIC_BASE.[10] = 1.
5412 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
5413 @param EAX Lower 32-bits of MSR value.
5414 @param EDX Upper 32-bits of MSR value.
5416 <b>Example usage</b>
5420 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
5422 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
5424 #define MSR_IA32_X2APIC_LDR 0x0000080D
5428 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
5429 && IA32_APIC_BASE.[10] = 1.
5431 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
5432 @param EAX Lower 32-bits of MSR value.
5433 @param EDX Upper 32-bits of MSR value.
5435 <b>Example usage</b>
5439 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
5440 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
5442 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
5444 #define MSR_IA32_X2APIC_SIVR 0x0000080F
5448 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
5449 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5451 @param ECX MSR_IA32_X2APIC_ISRn
5452 @param EAX Lower 32-bits of MSR value.
5453 @param EDX Upper 32-bits of MSR value.
5455 <b>Example usage</b>
5459 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
5461 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
5462 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
5463 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
5464 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
5465 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
5466 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
5467 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
5468 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
5471 #define MSR_IA32_X2APIC_ISR0 0x00000810
5472 #define MSR_IA32_X2APIC_ISR1 0x00000811
5473 #define MSR_IA32_X2APIC_ISR2 0x00000812
5474 #define MSR_IA32_X2APIC_ISR3 0x00000813
5475 #define MSR_IA32_X2APIC_ISR4 0x00000814
5476 #define MSR_IA32_X2APIC_ISR5 0x00000815
5477 #define MSR_IA32_X2APIC_ISR6 0x00000816
5478 #define MSR_IA32_X2APIC_ISR7 0x00000817
5483 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
5484 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5486 @param ECX MSR_IA32_X2APIC_TMRn
5487 @param EAX Lower 32-bits of MSR value.
5488 @param EDX Upper 32-bits of MSR value.
5490 <b>Example usage</b>
5494 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
5496 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
5497 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
5498 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
5499 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
5500 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
5501 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
5502 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
5503 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
5506 #define MSR_IA32_X2APIC_TMR0 0x00000818
5507 #define MSR_IA32_X2APIC_TMR1 0x00000819
5508 #define MSR_IA32_X2APIC_TMR2 0x0000081A
5509 #define MSR_IA32_X2APIC_TMR3 0x0000081B
5510 #define MSR_IA32_X2APIC_TMR4 0x0000081C
5511 #define MSR_IA32_X2APIC_TMR5 0x0000081D
5512 #define MSR_IA32_X2APIC_TMR6 0x0000081E
5513 #define MSR_IA32_X2APIC_TMR7 0x0000081F
5518 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
5519 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5521 @param ECX MSR_IA32_X2APIC_IRRn
5522 @param EAX Lower 32-bits of MSR value.
5523 @param EDX Upper 32-bits of MSR value.
5525 <b>Example usage</b>
5529 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
5531 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
5532 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
5533 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
5534 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
5535 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
5536 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
5537 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
5538 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
5541 #define MSR_IA32_X2APIC_IRR0 0x00000820
5542 #define MSR_IA32_X2APIC_IRR1 0x00000821
5543 #define MSR_IA32_X2APIC_IRR2 0x00000822
5544 #define MSR_IA32_X2APIC_IRR3 0x00000823
5545 #define MSR_IA32_X2APIC_IRR4 0x00000824
5546 #define MSR_IA32_X2APIC_IRR5 0x00000825
5547 #define MSR_IA32_X2APIC_IRR6 0x00000826
5548 #define MSR_IA32_X2APIC_IRR7 0x00000827
5553 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5554 IA32_APIC_BASE.[10] = 1.
5556 @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
5557 @param EAX Lower 32-bits of MSR value.
5558 @param EDX Upper 32-bits of MSR value.
5560 <b>Example usage</b>
5564 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
5565 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
5567 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
5569 #define MSR_IA32_X2APIC_ESR 0x00000828
5573 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
5574 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5576 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
5577 @param EAX Lower 32-bits of MSR value.
5578 @param EDX Upper 32-bits of MSR value.
5580 <b>Example usage</b>
5584 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
5585 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
5587 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
5589 #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5593 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5594 IA32_APIC_BASE.[10] = 1.
5596 @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
5597 @param EAX Lower 32-bits of MSR value.
5598 @param EDX Upper 32-bits of MSR value.
5600 <b>Example usage</b>
5604 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
5605 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
5607 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
5609 #define MSR_IA32_X2APIC_ICR 0x00000830
5613 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5614 IA32_APIC_BASE.[10] = 1.
5616 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
5617 @param EAX Lower 32-bits of MSR value.
5618 @param EDX Upper 32-bits of MSR value.
5620 <b>Example usage</b>
5624 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
5625 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
5627 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
5629 #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5633 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
5634 1 && IA32_APIC_BASE.[10] = 1.
5636 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
5637 @param EAX Lower 32-bits of MSR value.
5638 @param EDX Upper 32-bits of MSR value.
5640 <b>Example usage</b>
5644 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
5645 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
5647 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
5649 #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5653 x2APIC LVT Performance Monitor Interrupt Register (R/W). If
5654 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5656 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
5657 @param EAX Lower 32-bits of MSR value.
5658 @param EDX Upper 32-bits of MSR value.
5660 <b>Example usage</b>
5664 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
5665 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
5667 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
5669 #define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5673 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5674 IA32_APIC_BASE.[10] = 1.
5676 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
5677 @param EAX Lower 32-bits of MSR value.
5678 @param EDX Upper 32-bits of MSR value.
5680 <b>Example usage</b>
5684 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
5685 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
5687 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
5689 #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5693 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5694 IA32_APIC_BASE.[10] = 1.
5696 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
5697 @param EAX Lower 32-bits of MSR value.
5698 @param EDX Upper 32-bits of MSR value.
5700 <b>Example usage</b>
5704 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
5705 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
5707 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
5709 #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5713 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5714 IA32_APIC_BASE.[10] = 1.
5716 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
5717 @param EAX Lower 32-bits of MSR value.
5718 @param EDX Upper 32-bits of MSR value.
5720 <b>Example usage</b>
5724 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
5725 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
5727 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
5729 #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5733 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5734 IA32_APIC_BASE.[10] = 1.
5736 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
5737 @param EAX Lower 32-bits of MSR value.
5738 @param EDX Upper 32-bits of MSR value.
5740 <b>Example usage</b>
5744 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
5745 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
5747 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
5749 #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5753 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5754 IA32_APIC_BASE.[10] = 1.
5756 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
5757 @param EAX Lower 32-bits of MSR value.
5758 @param EDX Upper 32-bits of MSR value.
5760 <b>Example usage</b>
5764 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
5766 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
5768 #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5772 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5773 IA32_APIC_BASE.[10] = 1.
5775 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
5776 @param EAX Lower 32-bits of MSR value.
5777 @param EDX Upper 32-bits of MSR value.
5779 <b>Example usage</b>
5783 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
5784 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
5786 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
5788 #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5792 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
5793 IA32_APIC_BASE.[10] = 1.
5795 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
5796 @param EAX Lower 32-bits of MSR value.
5797 @param EDX Upper 32-bits of MSR value.
5799 <b>Example usage</b>
5804 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
5806 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
5808 #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5812 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
5814 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
5815 @param EAX Lower 32-bits of MSR value.
5816 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5817 @param EDX Upper 32-bits of MSR value.
5818 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5820 <b>Example usage</b>
5822 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
5824 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
5825 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
5827 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
5829 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5832 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
5836 /// Individual bit fields
5840 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
5841 /// Default is 0. If CPUID.01H:ECX.[11] = 1.
5844 UINT32 Reserved1
:29;
5846 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
5847 /// lock bit is set automatically on the first SMI assertion even if not
5848 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
5852 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
5853 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
5855 UINT32 DebugOccurred
:1;
5856 UINT32 Reserved2
:32;
5859 /// All bit fields as a 32-bit value
5863 /// All bit fields as a 64-bit value
5866 } MSR_IA32_DEBUG_INTERFACE_REGISTER
;
5870 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
5872 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
5873 @param EAX Lower 32-bits of MSR value.
5874 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5875 @param EDX Upper 32-bits of MSR value.
5876 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5878 <b>Example usage</b>
5880 MSR_IA32_L3_QOS_CFG_REGISTER Msr;
5882 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
5883 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
5885 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
5887 #define MSR_IA32_L3_QOS_CFG 0x00000C81
5890 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
5894 /// Individual bit fields
5898 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
5899 /// in Code and Data Prioritization (CDP) mode.
5902 UINT32 Reserved1
:31;
5903 UINT32 Reserved2
:32;
5906 /// All bit fields as a 32-bit value
5910 /// All bit fields as a 64-bit value
5913 } MSR_IA32_L3_QOS_CFG_REGISTER
;
5916 L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).
5918 @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)
5919 @param EAX Lower 32-bits of MSR value.
5920 Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
5921 @param EDX Upper 32-bits of MSR value.
5922 Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
5924 <b>Example usage</b>
5926 MSR_IA32_L2_QOS_CFG_REGISTER Msr;
5928 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
5929 AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);
5931 @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
5933 #define MSR_IA32_L2_QOS_CFG 0x00000C82
5936 MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
5940 /// Individual bit fields
5944 /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
5945 /// in Code and Data Prioritization (CDP) mode.
5948 UINT32 Reserved1
:31;
5949 UINT32 Reserved2
:32;
5952 /// All bit fields as a 32-bit value
5956 /// All bit fields as a 64-bit value
5959 } MSR_IA32_L2_QOS_CFG_REGISTER
;
5962 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
5965 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
5966 @param EAX Lower 32-bits of MSR value.
5967 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5968 @param EDX Upper 32-bits of MSR value.
5969 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5971 <b>Example usage</b>
5973 MSR_IA32_QM_EVTSEL_REGISTER Msr;
5975 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
5976 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
5978 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
5980 #define MSR_IA32_QM_EVTSEL 0x00000C8D
5983 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
5987 /// Individual bit fields
5991 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
5997 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
5998 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
5999 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
6001 UINT32 ResourceMonitoringID
:32;
6004 /// All bit fields as a 64-bit value
6007 } MSR_IA32_QM_EVTSEL_REGISTER
;
6011 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
6014 @param ECX MSR_IA32_QM_CTR (0x00000C8E)
6015 @param EAX Lower 32-bits of MSR value.
6016 Described by the type MSR_IA32_QM_CTR_REGISTER.
6017 @param EDX Upper 32-bits of MSR value.
6018 Described by the type MSR_IA32_QM_CTR_REGISTER.
6020 <b>Example usage</b>
6022 MSR_IA32_QM_CTR_REGISTER Msr;
6024 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
6026 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
6028 #define MSR_IA32_QM_CTR 0x00000C8E
6031 MSR information returned for MSR index #MSR_IA32_QM_CTR
6035 /// Individual bit fields
6039 /// [Bits 31:0] Resource Monitored Data.
6041 UINT32 ResourceMonitoredData
:32;
6043 /// [Bits 61:32] Resource Monitored Data.
6045 UINT32 ResourceMonitoredDataHi
:30;
6047 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
6048 /// available or not monitored for this resource or RMID.
6050 UINT32 Unavailable
:1;
6052 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
6053 /// written to IA32_PQR_QM_EVTSEL.
6058 /// All bit fields as a 64-bit value
6061 } MSR_IA32_QM_CTR_REGISTER
;
6065 Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
6066 =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
6068 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
6069 @param EAX Lower 32-bits of MSR value.
6070 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
6071 @param EDX Upper 32-bits of MSR value.
6072 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
6074 <b>Example usage</b>
6076 MSR_IA32_PQR_ASSOC_REGISTER Msr;
6078 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
6079 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
6081 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
6083 #define MSR_IA32_PQR_ASSOC 0x00000C8F
6086 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
6090 /// Individual bit fields
6094 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
6095 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
6096 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
6098 UINT32 ResourceMonitoringID
:32;
6100 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
6101 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
6102 /// ECX=0):EBX.[15] = 1 ).
6107 /// All bit fields as a 64-bit value
6110 } MSR_IA32_PQR_ASSOC_REGISTER
;
6114 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
6115 ECX=0H):EBX[14] = 1).
6117 @param ECX MSR_IA32_BNDCFGS (0x00000D90)
6118 @param EAX Lower 32-bits of MSR value.
6119 Described by the type MSR_IA32_BNDCFGS_REGISTER.
6120 @param EDX Upper 32-bits of MSR value.
6121 Described by the type MSR_IA32_BNDCFGS_REGISTER.
6123 <b>Example usage</b>
6125 MSR_IA32_BNDCFGS_REGISTER Msr;
6127 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
6128 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
6130 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
6132 #define MSR_IA32_BNDCFGS 0x00000D90
6135 MSR information returned for MSR index #MSR_IA32_BNDCFGS
6139 /// Individual bit fields
6143 /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
6147 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
6148 /// instructions in the absence of the BND prefix.
6150 UINT32 BNDPRESERVE
:1;
6153 /// [Bits 31:12] Base Address of Bound Directory.
6157 /// [Bits 63:32] Base Address of Bound Directory.
6162 /// All bit fields as a 64-bit value
6165 } MSR_IA32_BNDCFGS_REGISTER
;
6169 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
6171 @param ECX MSR_IA32_XSS (0x00000DA0)
6172 @param EAX Lower 32-bits of MSR value.
6173 Described by the type MSR_IA32_XSS_REGISTER.
6174 @param EDX Upper 32-bits of MSR value.
6175 Described by the type MSR_IA32_XSS_REGISTER.
6177 <b>Example usage</b>
6179 MSR_IA32_XSS_REGISTER Msr;
6181 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
6182 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
6184 @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
6186 #define MSR_IA32_XSS 0x00000DA0
6189 MSR information returned for MSR index #MSR_IA32_XSS
6193 /// Individual bit fields
6198 /// [Bit 8] Trace Packet Configuration State (R/W).
6200 UINT32 TracePacketConfigurationState
:1;
6201 UINT32 Reserved2
:23;
6202 UINT32 Reserved3
:32;
6205 /// All bit fields as a 32-bit value
6209 /// All bit fields as a 64-bit value
6212 } MSR_IA32_XSS_REGISTER
;
6216 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
6218 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
6219 @param EAX Lower 32-bits of MSR value.
6220 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6221 @param EDX Upper 32-bits of MSR value.
6222 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6224 <b>Example usage</b>
6226 MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
6228 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
6229 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
6231 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
6233 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6236 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
6240 /// Individual bit fields
6244 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
6245 /// logical processors in the package. See Section 14.5.2, "Package level
6246 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
6248 UINT32 HDC_Pkg_Enable
:1;
6249 UINT32 Reserved1
:31;
6250 UINT32 Reserved2
:32;
6253 /// All bit fields as a 32-bit value
6257 /// All bit fields as a 64-bit value
6260 } MSR_IA32_PKG_HDC_CTL_REGISTER
;
6264 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
6266 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
6267 @param EAX Lower 32-bits of MSR value.
6268 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6269 @param EDX Upper 32-bits of MSR value.
6270 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6272 <b>Example usage</b>
6274 MSR_IA32_PM_CTL1_REGISTER Msr;
6276 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
6277 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
6279 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
6281 #define MSR_IA32_PM_CTL1 0x00000DB1
6284 MSR information returned for MSR index #MSR_IA32_PM_CTL1
6288 /// Individual bit fields
6292 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
6293 /// package level HDC control. See Section 14.5.3.
6294 /// If CPUID.06H:EAX.[13] = 1.
6296 UINT32 HDC_Allow_Block
:1;
6297 UINT32 Reserved1
:31;
6298 UINT32 Reserved2
:32;
6301 /// All bit fields as a 32-bit value
6305 /// All bit fields as a 64-bit value
6308 } MSR_IA32_PM_CTL1_REGISTER
;
6312 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
6313 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
6314 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
6316 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
6317 @param EAX Lower 32-bits of MSR value.
6318 @param EDX Upper 32-bits of MSR value.
6320 <b>Example usage</b>
6324 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
6326 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
6328 #define MSR_IA32_THREAD_STALL 0x00000DB2
6332 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
6333 CPUID.80000001H:EDX.[2 9]).
6335 @param ECX MSR_IA32_EFER (0xC0000080)
6336 @param EAX Lower 32-bits of MSR value.
6337 Described by the type MSR_IA32_EFER_REGISTER.
6338 @param EDX Upper 32-bits of MSR value.
6339 Described by the type MSR_IA32_EFER_REGISTER.
6341 <b>Example usage</b>
6343 MSR_IA32_EFER_REGISTER Msr;
6345 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
6346 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
6348 @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
6350 #define MSR_IA32_EFER 0xC0000080
6353 MSR information returned for MSR index #MSR_IA32_EFER
6357 /// Individual bit fields
6361 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
6362 /// instructions in 64-bit mode.
6367 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
6373 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
6374 /// is active when set.
6378 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
6381 UINT32 Reserved3
:20;
6382 UINT32 Reserved4
:32;
6385 /// All bit fields as a 32-bit value
6389 /// All bit fields as a 64-bit value
6392 } MSR_IA32_EFER_REGISTER
;
6396 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6398 @param ECX MSR_IA32_STAR (0xC0000081)
6399 @param EAX Lower 32-bits of MSR value.
6400 @param EDX Upper 32-bits of MSR value.
6402 <b>Example usage</b>
6406 Msr = AsmReadMsr64 (MSR_IA32_STAR);
6407 AsmWriteMsr64 (MSR_IA32_STAR, Msr);
6409 @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
6411 #define MSR_IA32_STAR 0xC0000081
6415 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6417 @param ECX MSR_IA32_LSTAR (0xC0000082)
6418 @param EAX Lower 32-bits of MSR value.
6419 @param EDX Upper 32-bits of MSR value.
6421 <b>Example usage</b>
6425 Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
6426 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
6428 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
6430 #define MSR_IA32_LSTAR 0xC0000082
6433 IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
6434 instruction is not recognized in compatibility mode. If
6435 CPUID.80000001:EDX.[29] = 1.
6437 @param ECX MSR_IA32_CSTAR (0xC0000083)
6438 @param EAX Lower 32-bits of MSR value.
6439 @param EDX Upper 32-bits of MSR value.
6441 <b>Example usage</b>
6445 Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
6446 AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);
6448 @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
6450 #define MSR_IA32_CSTAR 0xC0000083
6453 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
6455 @param ECX MSR_IA32_FMASK (0xC0000084)
6456 @param EAX Lower 32-bits of MSR value.
6457 @param EDX Upper 32-bits of MSR value.
6459 <b>Example usage</b>
6463 Msr = AsmReadMsr64 (MSR_IA32_FMASK);
6464 AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
6466 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
6468 #define MSR_IA32_FMASK 0xC0000084
6472 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
6474 @param ECX MSR_IA32_FS_BASE (0xC0000100)
6475 @param EAX Lower 32-bits of MSR value.
6476 @param EDX Upper 32-bits of MSR value.
6478 <b>Example usage</b>
6482 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
6483 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
6485 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
6487 #define MSR_IA32_FS_BASE 0xC0000100
6491 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6493 @param ECX MSR_IA32_GS_BASE (0xC0000101)
6494 @param EAX Lower 32-bits of MSR value.
6495 @param EDX Upper 32-bits of MSR value.
6497 <b>Example usage</b>
6501 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
6502 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
6504 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
6506 #define MSR_IA32_GS_BASE 0xC0000101
6510 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6512 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
6513 @param EAX Lower 32-bits of MSR value.
6514 @param EDX Upper 32-bits of MSR value.
6516 <b>Example usage</b>
6520 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
6521 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
6523 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
6525 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6529 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
6531 @param ECX MSR_IA32_TSC_AUX (0xC0000103)
6532 @param EAX Lower 32-bits of MSR value.
6533 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6534 @param EDX Upper 32-bits of MSR value.
6535 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6537 <b>Example usage</b>
6539 MSR_IA32_TSC_AUX_REGISTER Msr;
6541 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
6542 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
6544 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
6546 #define MSR_IA32_TSC_AUX 0xC0000103
6549 MSR information returned for MSR index #MSR_IA32_TSC_AUX
6553 /// Individual bit fields
6557 /// [Bits 31:0] AUX: Auxiliary signature of TSC.
6563 /// All bit fields as a 32-bit value
6567 /// All bit fields as a 64-bit value
6570 } MSR_IA32_TSC_AUX_REGISTER
;