2 MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __CORE2_MSR_H__
19 #define __CORE2_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel(R) Core(TM) 2 Processor Family?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x0F || \
36 DisplayModel == 0x17 \
41 Shared. Model Specific Platform ID (R).
43 @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)
44 @param EAX Lower 32-bits of MSR value.
45 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
46 @param EDX Upper 32-bits of MSR value.
47 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
51 MSR_CORE2_PLATFORM_ID_REGISTER Msr;
53 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
55 @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
57 #define MSR_CORE2_PLATFORM_ID 0x00000017
60 MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
64 /// Individual bit fields
69 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
71 UINT32 MaximumQualifiedRatio
: 5;
72 UINT32 Reserved2
: 19;
73 UINT32 Reserved3
: 18;
75 /// [Bits 52:50] See Table 2-2.
77 UINT32 PlatformId
: 3;
78 UINT32 Reserved4
: 11;
81 /// All bit fields as a 64-bit value
84 } MSR_CORE2_PLATFORM_ID_REGISTER
;
87 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
88 processor features; (R) indicates current processor configuration.
90 @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)
91 @param EAX Lower 32-bits of MSR value.
92 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
93 @param EDX Upper 32-bits of MSR value.
94 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
98 MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;
100 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
101 AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
103 @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
105 #define MSR_CORE2_EBL_CR_POWERON 0x0000002A
108 MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
112 /// Individual bit fields
115 UINT32 Reserved1
: 1;
117 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
118 /// Note: Not all processor implements R/W.
120 UINT32 DataErrorCheckingEnable
: 1;
122 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
123 /// Note: Not all processor implements R/W.
125 UINT32 ResponseErrorCheckingEnable
: 1;
127 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
128 /// all processor implements R/W.
130 UINT32 MCERR_DriveEnable
: 1;
132 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
133 /// Not all processor implements R/W.
135 UINT32 AddressParityEnable
: 1;
136 UINT32 Reserved2
: 1;
137 UINT32 Reserved3
: 1;
139 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
140 /// all processor implements R/W.
142 UINT32 BINIT_DriverEnable
: 1;
144 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
146 UINT32 OutputTriStateEnable
: 1;
148 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
150 UINT32 ExecuteBIST
: 1;
152 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
154 UINT32 MCERR_ObservationEnabled
: 1;
156 /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.
158 UINT32 IntelTXTCapableChipset
: 1;
160 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
162 UINT32 BINIT_ObservationEnabled
: 1;
163 UINT32 Reserved4
: 1;
165 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
167 UINT32 ResetVector
: 1;
168 UINT32 Reserved5
: 1;
170 /// [Bits 17:16] APIC Cluster ID (R/O).
172 UINT32 APICClusterID
: 2;
174 /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =
175 /// Non-integer ratio.
177 UINT32 NonIntegerBusRatio
: 1;
178 UINT32 Reserved6
: 1;
180 /// [Bits 21:20] Symmetric Arbitration ID (R/O).
182 UINT32 SymmetricArbitrationID
: 2;
184 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
186 UINT32 IntegerBusFrequencyRatio
: 5;
187 UINT32 Reserved7
: 5;
188 UINT32 Reserved8
: 32;
191 /// All bit fields as a 32-bit value
195 /// All bit fields as a 64-bit value
198 } MSR_CORE2_EBL_CR_POWERON_REGISTER
;
201 Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.
203 @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)
204 @param EAX Lower 32-bits of MSR value.
205 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
206 @param EDX Upper 32-bits of MSR value.
207 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
211 MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;
213 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
214 AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
216 @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
218 #define MSR_CORE2_FEATURE_CONTROL 0x0000003A
221 MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL
225 /// Individual bit fields
228 UINT32 Reserved1
: 3;
230 /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock
231 /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read
232 /// visible and writeable while in SMM.
234 UINT32 SMRREnable
: 1;
235 UINT32 Reserved2
: 28;
236 UINT32 Reserved3
: 32;
239 /// All bit fields as a 32-bit value
243 /// All bit fields as a 64-bit value
246 } MSR_CORE2_FEATURE_CONTROL_REGISTER
;
249 Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
250 record registers on the last branch record stack. The From_IP part of the
251 stack contains pointers to the source instruction. See also: - Last Branch
252 Record Stack TOS at 1C9H - Section 17.5.
254 @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP
255 @param EAX Lower 32-bits of MSR value.
256 @param EDX Upper 32-bits of MSR value.
262 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
263 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
265 @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
266 MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
267 MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
268 MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
271 #define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040
272 #define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041
273 #define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042
274 #define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043
278 Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
279 record registers on the last branch record stack. This To_IP part of the
280 stack contains pointers to the destination instruction.
282 @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP
283 @param EAX Lower 32-bits of MSR value.
284 @param EDX Upper 32-bits of MSR value.
290 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
291 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
293 @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
294 MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
295 MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
296 MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
299 #define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060
300 #define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061
301 #define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062
302 #define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063
306 Unique. System Management Mode Base Address register (WO in SMM)
307 Model-specific implementation of SMRR-like interface, read visible and write
310 @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)
311 @param EAX Lower 32-bits of MSR value.
312 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
313 @param EDX Upper 32-bits of MSR value.
314 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
318 MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;
321 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
323 @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
325 #define MSR_CORE2_SMRR_PHYSBASE 0x000000A0
328 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE
332 /// Individual bit fields
335 UINT32 Reserved1
: 12;
337 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
339 UINT32 PhysBase
: 20;
340 UINT32 Reserved2
: 32;
343 /// All bit fields as a 32-bit value
347 /// All bit fields as a 64-bit value
350 } MSR_CORE2_SMRR_PHYSBASE_REGISTER
;
353 Unique. System Management Mode Physical Address Mask register (WO in SMM)
354 Model-specific implementation of SMRR-like interface, read visible and write
357 @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)
358 @param EAX Lower 32-bits of MSR value.
359 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
360 @param EDX Upper 32-bits of MSR value.
361 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
365 MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;
368 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
370 @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
372 #define MSR_CORE2_SMRR_PHYSMASK 0x000000A1
375 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK
379 /// Individual bit fields
382 UINT32 Reserved1
: 11;
384 /// [Bit 11] Valid. Physical address base and range mask are valid.
388 /// [Bits 31:12] PhysMask. SMRR physical address range mask.
390 UINT32 PhysMask
: 20;
391 UINT32 Reserved2
: 32;
394 /// All bit fields as a 32-bit value
398 /// All bit fields as a 64-bit value
401 } MSR_CORE2_SMRR_PHYSMASK_REGISTER
;
404 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
405 bus clock speed for processors based on Intel Core microarchitecture:.
407 @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)
408 @param EAX Lower 32-bits of MSR value.
409 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
410 @param EDX Upper 32-bits of MSR value.
411 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
415 MSR_CORE2_FSB_FREQ_REGISTER Msr;
417 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
419 @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
421 #define MSR_CORE2_FSB_FREQ 0x000000CD
424 MSR information returned for MSR index #MSR_CORE2_FSB_FREQ
428 /// Individual bit fields
432 /// [Bits 2:0] - Scalable Bus Speed
433 /// 101B: 100 MHz (FSB 400)
434 /// 001B: 133 MHz (FSB 533)
435 /// 011B: 167 MHz (FSB 667)
436 /// 010B: 200 MHz (FSB 800)
437 /// 000B: 267 MHz (FSB 1067)
438 /// 100B: 333 MHz (FSB 1333)
440 /// 133.33 MHz should be utilized if performing calculation with System
441 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
442 /// performing calculation with System Bus Speed when encoding is 011B.
443 /// 266.67 MHz should be utilized if performing calculation with System
444 /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if
445 /// performing calculation with System Bus Speed when encoding is 100B.
447 UINT32 ScalableBusSpeed
: 3;
448 UINT32 Reserved1
: 29;
449 UINT32 Reserved2
: 32;
452 /// All bit fields as a 32-bit value
456 /// All bit fields as a 64-bit value
459 } MSR_CORE2_FSB_FREQ_REGISTER
;
464 @param ECX MSR_CORE2_PERF_STATUS (0x00000198)
465 @param EAX Lower 32-bits of MSR value.
466 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
467 @param EDX Upper 32-bits of MSR value.
468 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
472 MSR_CORE2_PERF_STATUS_REGISTER Msr;
474 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
475 AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
477 @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
479 #define MSR_CORE2_PERF_STATUS 0x00000198
482 MSR information returned for MSR index #MSR_CORE2_PERF_STATUS
486 /// Individual bit fields
490 /// [Bits 15:0] Current Performance State Value.
492 UINT32 CurrentPerformanceStateValue
: 16;
493 UINT32 Reserved1
: 15;
495 /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default
498 UINT32 XEOperation
: 1;
499 UINT32 Reserved2
: 8;
501 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
502 /// configured for the processor.
504 UINT32 MaximumBusRatio
: 5;
505 UINT32 Reserved3
: 1;
507 /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio
508 /// is enabled. Applies processors based on Enhanced Intel Core
509 /// microarchitecture.
511 UINT32 NonIntegerBusRatio
: 1;
512 UINT32 Reserved4
: 17;
515 /// All bit fields as a 64-bit value
518 } MSR_CORE2_PERF_STATUS_REGISTER
;
523 @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)
524 @param EAX Lower 32-bits of MSR value.
525 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
526 @param EDX Upper 32-bits of MSR value.
527 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
531 MSR_CORE2_THERM2_CTL_REGISTER Msr;
533 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
534 AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
536 @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
538 #define MSR_CORE2_THERM2_CTL 0x0000019D
541 MSR information returned for MSR index #MSR_CORE2_THERM2_CTL
545 /// Individual bit fields
548 UINT32 Reserved1
: 16;
550 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
551 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
552 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
553 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
554 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
556 UINT32 TM_SELECT
: 1;
557 UINT32 Reserved2
: 15;
558 UINT32 Reserved3
: 32;
561 /// All bit fields as a 32-bit value
565 /// All bit fields as a 64-bit value
568 } MSR_CORE2_THERM2_CTL_REGISTER
;
571 Enable Misc. Processor Features (R/W) Allows a variety of processor
572 functions to be enabled and disabled.
574 @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
575 @param EAX Lower 32-bits of MSR value.
576 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
577 @param EDX Upper 32-bits of MSR value.
578 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
582 MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;
584 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
585 AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
587 @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
589 #define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0
592 MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE
596 /// Individual bit fields
600 /// [Bit 0] Fast-Strings Enable See Table 2-2.
602 UINT32 FastStrings
: 1;
603 UINT32 Reserved1
: 2;
605 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
608 UINT32 AutomaticThermalControlCircuit
: 1;
609 UINT32 Reserved2
: 3;
611 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
613 UINT32 PerformanceMonitoring
: 1;
614 UINT32 Reserved3
: 1;
616 /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the
617 /// hardware prefetcher operation on streams of data. When clear
618 /// (default), enables the prefetch queue. Disabling of the hardware
619 /// prefetcher may impact processor performance.
621 UINT32 HardwarePrefetcherDisable
: 1;
623 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
624 /// the processor to indicate a pending break event within the processor 0
625 /// = Indicates compatible FERR# signaling behavior This bit must be set
626 /// to 1 to support XAPIC interrupt model usage.
630 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
634 /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
639 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
640 /// thermal sensor indicates that the die temperature is at the
641 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
642 /// TM2 will reduce the bus to core ratio and voltage according to the
643 /// value last written to MSR_THERM2_CTL bits 15:0.
644 /// When this bit is clear (0, default), the processor does not change
645 /// the VID signals or the bus to core ratio when the processor enters a
646 /// thermally managed state. The BIOS must enable this feature if the
647 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
648 /// not set, this feature is not supported and BIOS must not alter the
649 /// contents of the TM2 bit location. The processor is operating out of
650 /// specification if both this bit and the TM1 bit are set to 0.
653 UINT32 Reserved4
: 2;
655 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
659 UINT32 Reserved5
: 1;
661 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
665 /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set
666 /// to 1, the processor fetches the cache line that contains data
667 /// currently required by the processor. When set to 0, the processor
668 /// fetches cache lines that comprise a cache line pair (128 bytes).
669 /// Single processor platforms should not set this bit. Server platforms
670 /// should set or clear this bit based on platform performance observed in
671 /// validation and testing. BIOS may contain a setup option that controls
672 /// the setting of this bit.
674 UINT32 AdjacentCacheLinePrefetchDisable
: 1;
676 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
677 /// (R/WO) When set, this bit causes the following bits to become
678 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
679 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
680 /// be set before an Enhanced Intel SpeedStep Technology transition is
681 /// requested. This bit is cleared on reset.
684 UINT32 Reserved6
: 1;
686 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.
688 UINT32 LimitCpuidMaxval
: 1;
690 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
692 UINT32 xTPR_Message_Disable
: 1;
693 UINT32 Reserved7
: 8;
694 UINT32 Reserved8
: 2;
696 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
699 UINT32 Reserved9
: 2;
701 /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU
702 /// L1 data cache prefetcher is disabled. The default value after reset is
703 /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is
704 /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple
705 /// loads from the same line done within a time limit, the DCU prefetcher
706 /// assumes the next line will be required. The next line is prefetched in
707 /// to the L1 data cache from memory or L2.
709 UINT32 DCUPrefetcherDisable
: 1;
711 /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that
712 /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled
713 /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
714 /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
715 /// reports the processor's support of IDA is enabled. Note: the power-on
716 /// default value is used by BIOS to detect hardware support of IDA. If
717 /// power-on default value is 1, IDA is available in the processor. If
718 /// power-on default value is 0, IDA is not available.
720 UINT32 IDADisable
: 1;
722 /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP
723 /// prefetcher is disabled. The default value after reset is 0. BIOS may
724 /// write '1' to disable this feature. The IP prefetcher is an L1 data
725 /// cache prefetcher. The IP prefetcher looks for sequential load history
726 /// to determine whether to prefetch the next expected data into the L1
727 /// cache from memory or L2.
729 UINT32 IPPrefetcherDisable
: 1;
730 UINT32 Reserved10
: 24;
733 /// All bit fields as a 64-bit value
736 } MSR_CORE2_IA32_MISC_ENABLE_REGISTER
;
739 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
740 that points to the MSR containing the most recent branch record. See
741 MSR_LASTBRANCH_0_FROM_IP (at 40H).
743 @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)
744 @param EAX Lower 32-bits of MSR value.
745 @param EDX Upper 32-bits of MSR value.
751 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
752 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
754 @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
756 #define MSR_CORE2_LASTBRANCH_TOS 0x000001C9
759 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
760 last branch instruction that the processor executed prior to the last
761 exception that was generated or the last interrupt that was handled.
763 @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)
764 @param EAX Lower 32-bits of MSR value.
765 @param EDX Upper 32-bits of MSR value.
771 Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
773 @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
775 #define MSR_CORE2_LER_FROM_LIP 0x000001DD
778 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
779 to the target of the last branch instruction that the processor executed
780 prior to the last exception that was generated or the last interrupt that
783 @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)
784 @param EAX Lower 32-bits of MSR value.
785 @param EDX Upper 32-bits of MSR value.
791 Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
793 @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
795 #define MSR_CORE2_LER_TO_LIP 0x000001DE
798 Unique. Fixed-Function Performance Counter Register n (R/W).
800 @param ECX MSR_CORE2_PERF_FIXED_CTRn
801 @param EAX Lower 32-bits of MSR value.
802 @param EDX Upper 32-bits of MSR value.
808 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
809 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
811 @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.
812 MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.
813 MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.
816 #define MSR_CORE2_PERF_FIXED_CTR0 0x00000309
817 #define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A
818 #define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B
822 Unique. RO. This applies to processors that do not support architectural
825 @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)
826 @param EAX Lower 32-bits of MSR value.
827 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
828 @param EDX Upper 32-bits of MSR value.
829 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
833 MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;
835 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
836 AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
838 @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.
840 #define MSR_CORE2_PERF_CAPABILITIES 0x00000345
843 MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES
847 /// Individual bit fields
851 /// [Bits 5:0] LBR Format. See Table 2-2.
855 /// [Bit 6] PEBS Record Format.
859 /// [Bit 7] PEBSSaveArchRegs. See Table 2-2.
861 UINT32 PEBS_ARCH_REG
: 1;
862 UINT32 Reserved1
: 24;
863 UINT32 Reserved2
: 32;
866 /// All bit fields as a 32-bit value
870 /// All bit fields as a 64-bit value
873 } MSR_CORE2_PERF_CAPABILITIES_REGISTER
;
876 Unique. Fixed-Function-Counter Control Register (R/W).
878 @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
879 @param EAX Lower 32-bits of MSR value.
880 @param EDX Upper 32-bits of MSR value.
886 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
887 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
889 @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.
891 #define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D
894 Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
896 @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
897 @param EAX Lower 32-bits of MSR value.
898 @param EDX Upper 32-bits of MSR value.
904 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);
905 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);
907 @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
909 #define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E
912 Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
914 @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
915 @param EAX Lower 32-bits of MSR value.
916 @param EDX Upper 32-bits of MSR value.
922 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
923 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
925 @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.
927 #define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F
930 Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
932 @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
933 @param EAX Lower 32-bits of MSR value.
934 @param EDX Upper 32-bits of MSR value.
940 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
941 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
943 @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
945 #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390
948 Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
951 @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)
952 @param EAX Lower 32-bits of MSR value.
953 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
954 @param EDX Upper 32-bits of MSR value.
955 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
959 MSR_CORE2_PEBS_ENABLE_REGISTER Msr;
961 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
962 AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
964 @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
966 #define MSR_CORE2_PEBS_ENABLE 0x000003F1
969 MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE
973 /// Individual bit fields
977 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
980 UINT32 Reserved1
: 31;
981 UINT32 Reserved2
: 32;
984 /// All bit fields as a 32-bit value
988 /// All bit fields as a 64-bit value
991 } MSR_CORE2_PEBS_ENABLE_REGISTER
;
994 Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
995 processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
997 @param ECX MSR_CORE2_EMON_L3_CTR_CTLn
998 @param EAX Lower 32-bits of MSR value.
999 @param EDX Upper 32-bits of MSR value.
1001 <b>Example usage</b>
1005 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
1006 AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
1008 @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
1009 MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
1010 MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
1011 MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
1012 MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
1013 MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
1014 MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
1015 MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
1018 #define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC
1019 #define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD
1020 #define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE
1021 #define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF
1022 #define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0
1023 #define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1
1024 #define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2
1025 #define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3
1029 Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor
1030 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1032 @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
1033 @param EAX Lower 32-bits of MSR value.
1034 @param EDX Upper 32-bits of MSR value.
1036 <b>Example usage</b>
1040 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
1041 AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
1043 @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.
1045 #define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8