2 MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __CORE2_MSR_H__
19 #define __CORE2_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel(R) Core(TM) 2 Processor Family?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x0F || \
36 DisplayModel == 0x17 \
41 Shared. Model Specific Platform ID (R).
43 @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)
44 @param EAX Lower 32-bits of MSR value.
45 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
46 @param EDX Upper 32-bits of MSR value.
47 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
51 MSR_CORE2_PLATFORM_ID_REGISTER Msr;
53 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
55 @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
57 #define MSR_CORE2_PLATFORM_ID 0x00000017
60 MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
64 /// Individual bit fields
69 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
71 UINT32 MaximumQualifiedRatio
:5;
75 /// [Bits 52:50] See Table 2-2.
81 /// All bit fields as a 64-bit value
84 } MSR_CORE2_PLATFORM_ID_REGISTER
;
88 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
89 processor features; (R) indicates current processor configuration.
91 @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)
92 @param EAX Lower 32-bits of MSR value.
93 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
94 @param EDX Upper 32-bits of MSR value.
95 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
99 MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;
101 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
102 AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
104 @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
106 #define MSR_CORE2_EBL_CR_POWERON 0x0000002A
109 MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
113 /// Individual bit fields
118 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
119 /// Note: Not all processor implements R/W.
121 UINT32 DataErrorCheckingEnable
:1;
123 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
124 /// Note: Not all processor implements R/W.
126 UINT32 ResponseErrorCheckingEnable
:1;
128 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
129 /// all processor implements R/W.
131 UINT32 MCERR_DriveEnable
:1;
133 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
134 /// Not all processor implements R/W.
136 UINT32 AddressParityEnable
:1;
140 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
141 /// all processor implements R/W.
143 UINT32 BINIT_DriverEnable
:1;
145 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
147 UINT32 OutputTriStateEnable
:1;
149 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
151 UINT32 ExecuteBIST
:1;
153 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
155 UINT32 MCERR_ObservationEnabled
:1;
157 /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.
159 UINT32 IntelTXTCapableChipset
:1;
161 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
163 UINT32 BINIT_ObservationEnabled
:1;
166 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
168 UINT32 ResetVector
:1;
171 /// [Bits 17:16] APIC Cluster ID (R/O).
173 UINT32 APICClusterID
:2;
175 /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =
176 /// Non-integer ratio.
178 UINT32 NonIntegerBusRatio
:1;
181 /// [Bits 21:20] Symmetric Arbitration ID (R/O).
183 UINT32 SymmetricArbitrationID
:2;
185 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
187 UINT32 IntegerBusFrequencyRatio
:5;
192 /// All bit fields as a 32-bit value
196 /// All bit fields as a 64-bit value
199 } MSR_CORE2_EBL_CR_POWERON_REGISTER
;
203 Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.
205 @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)
206 @param EAX Lower 32-bits of MSR value.
207 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
208 @param EDX Upper 32-bits of MSR value.
209 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
213 MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;
215 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
216 AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
218 @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
220 #define MSR_CORE2_FEATURE_CONTROL 0x0000003A
223 MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL
227 /// Individual bit fields
232 /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock
233 /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read
234 /// visible and writeable while in SMM.
241 /// All bit fields as a 32-bit value
245 /// All bit fields as a 64-bit value
248 } MSR_CORE2_FEATURE_CONTROL_REGISTER
;
252 Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
253 record registers on the last branch record stack. The From_IP part of the
254 stack contains pointers to the source instruction. See also: - Last Branch
255 Record Stack TOS at 1C9H - Section 17.5.
257 @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP
258 @param EAX Lower 32-bits of MSR value.
259 @param EDX Upper 32-bits of MSR value.
265 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
266 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
268 @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
269 MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
270 MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
271 MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
274 #define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040
275 #define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041
276 #define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042
277 #define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043
282 Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
283 record registers on the last branch record stack. This To_IP part of the
284 stack contains pointers to the destination instruction.
286 @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP
287 @param EAX Lower 32-bits of MSR value.
288 @param EDX Upper 32-bits of MSR value.
294 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
295 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
297 @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
298 MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
299 MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
300 MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
303 #define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060
304 #define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061
305 #define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062
306 #define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063
311 Unique. System Management Mode Base Address register (WO in SMM)
312 Model-specific implementation of SMRR-like interface, read visible and write
315 @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)
316 @param EAX Lower 32-bits of MSR value.
317 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
318 @param EDX Upper 32-bits of MSR value.
319 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
323 MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;
326 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
328 @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
330 #define MSR_CORE2_SMRR_PHYSBASE 0x000000A0
333 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE
337 /// Individual bit fields
342 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
348 /// All bit fields as a 32-bit value
352 /// All bit fields as a 64-bit value
355 } MSR_CORE2_SMRR_PHYSBASE_REGISTER
;
359 Unique. System Management Mode Physical Address Mask register (WO in SMM)
360 Model-specific implementation of SMRR-like interface, read visible and write
363 @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)
364 @param EAX Lower 32-bits of MSR value.
365 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
366 @param EDX Upper 32-bits of MSR value.
367 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
371 MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;
374 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
376 @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
378 #define MSR_CORE2_SMRR_PHYSMASK 0x000000A1
381 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK
385 /// Individual bit fields
390 /// [Bit 11] Valid. Physical address base and range mask are valid.
394 /// [Bits 31:12] PhysMask. SMRR physical address range mask.
400 /// All bit fields as a 32-bit value
404 /// All bit fields as a 64-bit value
407 } MSR_CORE2_SMRR_PHYSMASK_REGISTER
;
411 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
412 bus clock speed for processors based on Intel Core microarchitecture:.
414 @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)
415 @param EAX Lower 32-bits of MSR value.
416 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
417 @param EDX Upper 32-bits of MSR value.
418 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
422 MSR_CORE2_FSB_FREQ_REGISTER Msr;
424 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
426 @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
428 #define MSR_CORE2_FSB_FREQ 0x000000CD
431 MSR information returned for MSR index #MSR_CORE2_FSB_FREQ
435 /// Individual bit fields
439 /// [Bits 2:0] - Scalable Bus Speed
440 /// 101B: 100 MHz (FSB 400)
441 /// 001B: 133 MHz (FSB 533)
442 /// 011B: 167 MHz (FSB 667)
443 /// 010B: 200 MHz (FSB 800)
444 /// 000B: 267 MHz (FSB 1067)
445 /// 100B: 333 MHz (FSB 1333)
447 /// 133.33 MHz should be utilized if performing calculation with System
448 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
449 /// performing calculation with System Bus Speed when encoding is 011B.
450 /// 266.67 MHz should be utilized if performing calculation with System
451 /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if
452 /// performing calculation with System Bus Speed when encoding is 100B.
454 UINT32 ScalableBusSpeed
:3;
459 /// All bit fields as a 32-bit value
463 /// All bit fields as a 64-bit value
466 } MSR_CORE2_FSB_FREQ_REGISTER
;
471 @param ECX MSR_CORE2_PERF_STATUS (0x00000198)
472 @param EAX Lower 32-bits of MSR value.
473 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
474 @param EDX Upper 32-bits of MSR value.
475 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
479 MSR_CORE2_PERF_STATUS_REGISTER Msr;
481 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
482 AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
484 @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
486 #define MSR_CORE2_PERF_STATUS 0x00000198
489 MSR information returned for MSR index #MSR_CORE2_PERF_STATUS
493 /// Individual bit fields
497 /// [Bits 15:0] Current Performance State Value.
499 UINT32 CurrentPerformanceStateValue
:16;
502 /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default
505 UINT32 XEOperation
:1;
508 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
509 /// configured for the processor.
511 UINT32 MaximumBusRatio
:5;
514 /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio
515 /// is enabled. Applies processors based on Enhanced Intel Core
516 /// microarchitecture.
518 UINT32 NonIntegerBusRatio
:1;
522 /// All bit fields as a 64-bit value
525 } MSR_CORE2_PERF_STATUS_REGISTER
;
531 @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)
532 @param EAX Lower 32-bits of MSR value.
533 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
534 @param EDX Upper 32-bits of MSR value.
535 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
539 MSR_CORE2_THERM2_CTL_REGISTER Msr;
541 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
542 AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
544 @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
546 #define MSR_CORE2_THERM2_CTL 0x0000019D
549 MSR information returned for MSR index #MSR_CORE2_THERM2_CTL
553 /// Individual bit fields
558 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
559 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
560 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
561 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
562 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
569 /// All bit fields as a 32-bit value
573 /// All bit fields as a 64-bit value
576 } MSR_CORE2_THERM2_CTL_REGISTER
;
580 Enable Misc. Processor Features (R/W) Allows a variety of processor
581 functions to be enabled and disabled.
583 @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
584 @param EAX Lower 32-bits of MSR value.
585 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
586 @param EDX Upper 32-bits of MSR value.
587 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
591 MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;
593 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
594 AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
596 @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
598 #define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0
601 MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE
605 /// Individual bit fields
609 /// [Bit 0] Fast-Strings Enable See Table 2-2.
611 UINT32 FastStrings
:1;
614 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
617 UINT32 AutomaticThermalControlCircuit
:1;
620 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
622 UINT32 PerformanceMonitoring
:1;
625 /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the
626 /// hardware prefetcher operation on streams of data. When clear
627 /// (default), enables the prefetch queue. Disabling of the hardware
628 /// prefetcher may impact processor performance.
630 UINT32 HardwarePrefetcherDisable
:1;
632 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
633 /// the processor to indicate a pending break event within the processor 0
634 /// = Indicates compatible FERR# signaling behavior This bit must be set
635 /// to 1 to support XAPIC interrupt model usage.
639 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
643 /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
648 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
649 /// thermal sensor indicates that the die temperature is at the
650 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
651 /// TM2 will reduce the bus to core ratio and voltage according to the
652 /// value last written to MSR_THERM2_CTL bits 15:0.
653 /// When this bit is clear (0, default), the processor does not change
654 /// the VID signals or the bus to core ratio when the processor enters a
655 /// thermally managed state. The BIOS must enable this feature if the
656 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
657 /// not set, this feature is not supported and BIOS must not alter the
658 /// contents of the TM2 bit location. The processor is operating out of
659 /// specification if both this bit and the TM1 bit are set to 0.
664 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
670 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
674 /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set
675 /// to 1, the processor fetches the cache line that contains data
676 /// currently required by the processor. When set to 0, the processor
677 /// fetches cache lines that comprise a cache line pair (128 bytes).
678 /// Single processor platforms should not set this bit. Server platforms
679 /// should set or clear this bit based on platform performance observed in
680 /// validation and testing. BIOS may contain a setup option that controls
681 /// the setting of this bit.
683 UINT32 AdjacentCacheLinePrefetchDisable
:1;
685 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
686 /// (R/WO) When set, this bit causes the following bits to become
687 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
688 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
689 /// be set before an Enhanced Intel SpeedStep Technology transition is
690 /// requested. This bit is cleared on reset.
695 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.
697 UINT32 LimitCpuidMaxval
:1;
699 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
701 UINT32 xTPR_Message_Disable
:1;
705 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
710 /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU
711 /// L1 data cache prefetcher is disabled. The default value after reset is
712 /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is
713 /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple
714 /// loads from the same line done within a time limit, the DCU prefetcher
715 /// assumes the next line will be required. The next line is prefetched in
716 /// to the L1 data cache from memory or L2.
718 UINT32 DCUPrefetcherDisable
:1;
720 /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that
721 /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled
722 /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
723 /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
724 /// reports the processor's support of IDA is enabled. Note: the power-on
725 /// default value is used by BIOS to detect hardware support of IDA. If
726 /// power-on default value is 1, IDA is available in the processor. If
727 /// power-on default value is 0, IDA is not available.
731 /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP
732 /// prefetcher is disabled. The default value after reset is 0. BIOS may
733 /// write '1' to disable this feature. The IP prefetcher is an L1 data
734 /// cache prefetcher. The IP prefetcher looks for sequential load history
735 /// to determine whether to prefetch the next expected data into the L1
736 /// cache from memory or L2.
738 UINT32 IPPrefetcherDisable
:1;
739 UINT32 Reserved10
:24;
742 /// All bit fields as a 64-bit value
745 } MSR_CORE2_IA32_MISC_ENABLE_REGISTER
;
749 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
750 that points to the MSR containing the most recent branch record. See
751 MSR_LASTBRANCH_0_FROM_IP (at 40H).
753 @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)
754 @param EAX Lower 32-bits of MSR value.
755 @param EDX Upper 32-bits of MSR value.
761 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
762 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
764 @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
766 #define MSR_CORE2_LASTBRANCH_TOS 0x000001C9
770 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
771 last branch instruction that the processor executed prior to the last
772 exception that was generated or the last interrupt that was handled.
774 @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)
775 @param EAX Lower 32-bits of MSR value.
776 @param EDX Upper 32-bits of MSR value.
782 Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
784 @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
786 #define MSR_CORE2_LER_FROM_LIP 0x000001DD
790 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
791 to the target of the last branch instruction that the processor executed
792 prior to the last exception that was generated or the last interrupt that
795 @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)
796 @param EAX Lower 32-bits of MSR value.
797 @param EDX Upper 32-bits of MSR value.
803 Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
805 @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
807 #define MSR_CORE2_LER_TO_LIP 0x000001DE
811 Unique. Fixed-Function Performance Counter Register n (R/W).
813 @param ECX MSR_CORE2_PERF_FIXED_CTRn
814 @param EAX Lower 32-bits of MSR value.
815 @param EDX Upper 32-bits of MSR value.
821 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
822 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
824 @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.
825 MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.
826 MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.
829 #define MSR_CORE2_PERF_FIXED_CTR0 0x00000309
830 #define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A
831 #define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B
836 Unique. RO. This applies to processors that do not support architectural
839 @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)
840 @param EAX Lower 32-bits of MSR value.
841 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
842 @param EDX Upper 32-bits of MSR value.
843 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
847 MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;
849 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
850 AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
852 @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.
854 #define MSR_CORE2_PERF_CAPABILITIES 0x00000345
857 MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES
861 /// Individual bit fields
865 /// [Bits 5:0] LBR Format. See Table 2-2.
869 /// [Bit 6] PEBS Record Format.
873 /// [Bit 7] PEBSSaveArchRegs. See Table 2-2.
875 UINT32 PEBS_ARCH_REG
:1;
880 /// All bit fields as a 32-bit value
884 /// All bit fields as a 64-bit value
887 } MSR_CORE2_PERF_CAPABILITIES_REGISTER
;
891 Unique. Fixed-Function-Counter Control Register (R/W).
893 @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
894 @param EAX Lower 32-bits of MSR value.
895 @param EDX Upper 32-bits of MSR value.
901 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
902 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
904 @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.
906 #define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D
910 Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
912 @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
913 @param EAX Lower 32-bits of MSR value.
914 @param EDX Upper 32-bits of MSR value.
920 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);
921 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);
923 @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
925 #define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E
929 Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
931 @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
932 @param EAX Lower 32-bits of MSR value.
933 @param EDX Upper 32-bits of MSR value.
939 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
940 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
942 @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.
944 #define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F
948 Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
950 @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
951 @param EAX Lower 32-bits of MSR value.
952 @param EDX Upper 32-bits of MSR value.
958 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
959 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
961 @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
963 #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390
967 Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
970 @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)
971 @param EAX Lower 32-bits of MSR value.
972 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
973 @param EDX Upper 32-bits of MSR value.
974 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
978 MSR_CORE2_PEBS_ENABLE_REGISTER Msr;
980 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
981 AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
983 @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
985 #define MSR_CORE2_PEBS_ENABLE 0x000003F1
988 MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE
992 /// Individual bit fields
996 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1000 UINT32 Reserved2
:32;
1003 /// All bit fields as a 32-bit value
1007 /// All bit fields as a 64-bit value
1010 } MSR_CORE2_PEBS_ENABLE_REGISTER
;
1014 Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
1015 processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1017 @param ECX MSR_CORE2_EMON_L3_CTR_CTLn
1018 @param EAX Lower 32-bits of MSR value.
1019 @param EDX Upper 32-bits of MSR value.
1021 <b>Example usage</b>
1025 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
1026 AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
1028 @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
1029 MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
1030 MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
1031 MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
1032 MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
1033 MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
1034 MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
1035 MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
1038 #define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC
1039 #define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD
1040 #define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE
1041 #define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF
1042 #define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0
1043 #define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1
1044 #define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2
1045 #define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3
1050 Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor
1051 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1053 @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
1054 @param EAX Lower 32-bits of MSR value.
1055 @param EDX Upper 32-bits of MSR value.
1057 <b>Example usage</b>
1061 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
1062 AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
1064 @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.
1066 #define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8