2 MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __HASWELL_E_MSR_H__
19 #define __HASWELL_E_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel processors based on the Haswell-E microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x3F \
40 Package. Configured State of Enabled Processor Core Count and Logical
41 Processor Count (RO) - After a Power-On RESET, enumerates factory
42 configuration of the number of processor cores and logical processors in the
43 physical package. - Following the sequence of (i) BIOS modified a
44 Configuration Mask which selects a subset of processor cores to be active
45 post RESET and (ii) a RESET event after the modification, enumerates the
46 current configuration of enabled processor core count and logical processor
47 count in the physical package.
49 @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
57 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;
59 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);
61 @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
63 #define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035
66 MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
70 /// Individual bit fields
74 /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are
75 /// currently enabled (by either factory configuration or BIOS
76 /// configuration) in the physical package.
78 UINT32 Core_Count
: 16;
80 /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
81 /// are currently enabled (by either factory configuration or BIOS
82 /// configuration) in the physical package.
84 UINT32 Thread_Count
: 16;
88 /// All bit fields as a 32-bit value
92 /// All bit fields as a 64-bit value
95 } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
;
98 Thread. A Hardware Assigned ID for the Logical Processor (RO).
100 @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
101 @param EAX Lower 32-bits of MSR value.
102 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
103 @param EDX Upper 32-bits of MSR value.
104 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
108 MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;
110 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);
112 @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
114 #define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053
117 MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
121 /// Individual bit fields
125 /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific
126 /// numerical. value physically assigned to each logical processor. This
127 /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
128 /// a physical package.
130 UINT32 Logical_Processor_ID
: 8;
131 UINT32 Reserved1
: 24;
132 UINT32 Reserved2
: 32;
135 /// All bit fields as a 32-bit value
139 /// All bit fields as a 64-bit value
142 } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
;
145 Core. C-State Configuration Control (R/W) Note: C-state values are processor
146 specific C-state code names, unrelated to MWAIT extension C-state parameters
147 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
149 @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
150 @param EAX Lower 32-bits of MSR value.
151 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
152 @param EDX Upper 32-bits of MSR value.
153 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
157 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
159 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
160 AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
162 @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
164 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2
167 MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
171 /// Individual bit fields
175 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
176 /// processor-specific C-state code name (consuming the least power) for
177 /// the package. The default is set as factory-configured package C-state
178 /// limit. The following C-state code name encodings are supported: 000b:
179 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
180 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
181 /// supported by the processor are available.
184 UINT32 Reserved1
: 7;
186 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
189 UINT32 Reserved2
: 4;
191 /// [Bit 15] CFG Lock (R/WO).
194 UINT32 Reserved3
: 9;
196 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
198 UINT32 C3AutoDemotion
: 1;
200 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
202 UINT32 C1AutoDemotion
: 1;
204 /// [Bit 27] Enable C3 Undemotion (R/W).
206 UINT32 C3Undemotion
: 1;
208 /// [Bit 28] Enable C1 Undemotion (R/W).
210 UINT32 C1Undemotion
: 1;
212 /// [Bit 29] Package C State Demotion Enable (R/W).
214 UINT32 CStateDemotion
: 1;
216 /// [Bit 30] Package C State UnDemotion Enable (R/W).
218 UINT32 CStateUndemotion
: 1;
219 UINT32 Reserved4
: 1;
220 UINT32 Reserved5
: 32;
223 /// All bit fields as a 32-bit value
227 /// All bit fields as a 64-bit value
230 } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
;
233 Thread. Global Machine Check Capability (R/O).
235 @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
236 @param EAX Lower 32-bits of MSR value.
237 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
238 @param EDX Upper 32-bits of MSR value.
239 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
243 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;
245 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
247 @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
249 #define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179
252 MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
256 /// Individual bit fields
260 /// [Bits 7:0] Count.
264 /// [Bit 8] MCG_CTL_P.
266 UINT32 MCG_CTL_P
: 1;
268 /// [Bit 9] MCG_EXT_P.
270 UINT32 MCG_EXT_P
: 1;
272 /// [Bit 10] MCP_CMCI_P.
274 UINT32 MCP_CMCI_P
: 1;
276 /// [Bit 11] MCG_TES_P.
278 UINT32 MCG_TES_P
: 1;
279 UINT32 Reserved1
: 4;
281 /// [Bits 23:16] MCG_EXT_CNT.
283 UINT32 MCG_EXT_CNT
: 8;
285 /// [Bit 24] MCG_SER_P.
287 UINT32 MCG_SER_P
: 1;
289 /// [Bit 25] MCG_EM_P.
293 /// [Bit 26] MCG_ELOG_P.
295 UINT32 MCG_ELOG_P
: 1;
296 UINT32 Reserved2
: 5;
297 UINT32 Reserved3
: 32;
300 /// All bit fields as a 32-bit value
304 /// All bit fields as a 64-bit value
307 } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
;
310 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
311 Enhancement. Accessible only while in SMM.
313 @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
314 @param EAX Lower 32-bits of MSR value.
315 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
316 @param EDX Upper 32-bits of MSR value.
317 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
321 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;
323 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
324 AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
326 @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
328 #define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D
331 MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
335 /// Individual bit fields
338 UINT32 Reserved1
: 32;
339 UINT32 Reserved2
: 26;
341 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
342 /// SMM code access restriction is supported and a host-space interface
343 /// available to SMM handler.
345 UINT32 SMM_Code_Access_Chk
: 1;
347 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
348 /// SMM long flow indicator is supported and a host-space interface
349 /// available to SMM handler.
351 UINT32 Long_Flow_Indication
: 1;
352 UINT32 Reserved3
: 4;
355 /// All bit fields as a 64-bit value
358 } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
;
361 Package. MC Bank Error Configuration (R/W).
363 @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
364 @param EAX Lower 32-bits of MSR value.
365 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
366 @param EDX Upper 32-bits of MSR value.
367 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
371 MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;
373 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
374 AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
376 @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
378 #define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F
381 MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
385 /// Individual bit fields
388 UINT32 Reserved1
: 1;
390 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
391 /// to log additional info in bits 36:32.
393 UINT32 MemErrorLogEnable
: 1;
394 UINT32 Reserved2
: 30;
395 UINT32 Reserved3
: 32;
398 /// All bit fields as a 32-bit value
402 /// All bit fields as a 64-bit value
405 } MSR_HASWELL_E_ERROR_CONTROL_REGISTER
;
408 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
409 RW if MSR_PLATFORM_INFO.[28] = 1.
411 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
412 @param EAX Lower 32-bits of MSR value.
413 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
414 @param EDX Upper 32-bits of MSR value.
415 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
419 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;
421 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
423 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
425 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD
428 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
432 /// Individual bit fields
436 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
437 /// limit of 1 core active.
439 UINT32 Maximum1C
: 8;
441 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
442 /// limit of 2 core active.
444 UINT32 Maximum2C
: 8;
446 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
447 /// limit of 3 core active.
449 UINT32 Maximum3C
: 8;
451 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
452 /// limit of 4 core active.
454 UINT32 Maximum4C
: 8;
456 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
457 /// limit of 5 core active.
459 UINT32 Maximum5C
: 8;
461 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
462 /// limit of 6 core active.
464 UINT32 Maximum6C
: 8;
466 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
467 /// limit of 7 core active.
469 UINT32 Maximum7C
: 8;
471 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
472 /// limit of 8 core active.
474 UINT32 Maximum8C
: 8;
477 /// All bit fields as a 64-bit value
480 } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
;
483 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
484 RW if MSR_PLATFORM_INFO.[28] = 1.
486 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
487 @param EAX Lower 32-bits of MSR value.
488 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
489 @param EDX Upper 32-bits of MSR value.
490 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
494 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;
496 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
498 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
500 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE
503 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
507 /// Individual bit fields
511 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
512 /// limit of 9 core active.
514 UINT32 Maximum9C
: 8;
516 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
517 /// limit of 10 core active.
519 UINT32 Maximum10C
: 8;
521 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
522 /// limit of 11 core active.
524 UINT32 Maximum11C
: 8;
526 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
527 /// limit of 12 core active.
529 UINT32 Maximum12C
: 8;
531 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
532 /// limit of 13 core active.
534 UINT32 Maximum13C
: 8;
536 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
537 /// limit of 14 core active.
539 UINT32 Maximum14C
: 8;
541 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
542 /// limit of 15 core active.
544 UINT32 Maximum15C
: 8;
546 /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
547 /// limit of 16 core active.
549 UINT32 Maximum16C
: 8;
552 /// All bit fields as a 64-bit value
555 } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
;
558 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
559 RW if MSR_PLATFORM_INFO.[28] = 1.
561 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
562 @param EAX Lower 32-bits of MSR value.
563 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
564 @param EDX Upper 32-bits of MSR value.
565 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
569 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;
571 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
573 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
575 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF
578 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
582 /// Individual bit fields
586 /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
587 /// limit of 17 core active.
589 UINT32 Maximum17C
: 8;
591 /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
592 /// limit of 18 core active.
594 UINT32 Maximum18C
: 8;
595 UINT32 Reserved1
: 16;
596 UINT32 Reserved2
: 31;
598 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
599 /// the processor uses override configuration specified in
600 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
601 /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
602 /// configuration (Default).
604 UINT32 TurboRatioLimitConfigurationSemaphore
: 1;
607 /// All bit fields as a 64-bit value
610 } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
;
613 Package. Unit Multipliers used in RAPL Interfaces (R/O).
615 @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
616 @param EAX Lower 32-bits of MSR value.
617 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
618 @param EDX Upper 32-bits of MSR value.
619 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
623 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;
625 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
627 @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
629 #define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606
632 MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
636 /// Individual bit fields
640 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
642 UINT32 PowerUnits
: 4;
643 UINT32 Reserved1
: 4;
645 /// [Bits 12:8] Package. Energy Status Units Energy related information
646 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
647 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
650 UINT32 EnergyStatusUnits
: 5;
651 UINT32 Reserved2
: 3;
653 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
656 UINT32 TimeUnits
: 4;
657 UINT32 Reserved3
: 12;
658 UINT32 Reserved4
: 32;
661 /// All bit fields as a 32-bit value
665 /// All bit fields as a 64-bit value
668 } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
;
671 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
674 @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
675 @param EAX Lower 32-bits of MSR value.
676 @param EDX Upper 32-bits of MSR value.
682 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
683 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
685 @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
687 #define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618
690 Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.
692 @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
693 @param EAX Lower 32-bits of MSR value.
694 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
695 @param EDX Upper 32-bits of MSR value.
696 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
700 MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;
702 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
704 @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
706 #define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
709 MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
713 /// Individual bit fields
717 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
718 /// to enable DRAM RAPL mode 0 (Direct VR).
721 UINT32 Reserved
: 32;
724 /// All bit fields as a 32-bit value
728 /// All bit fields as a 64-bit value
731 } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER
;
734 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
737 @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
738 @param EAX Lower 32-bits of MSR value.
739 @param EDX Upper 32-bits of MSR value.
745 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
747 @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
749 #define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B
752 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
754 @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
755 @param EAX Lower 32-bits of MSR value.
756 @param EDX Upper 32-bits of MSR value.
762 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
763 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
765 @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
767 #define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C
770 Package. Configuration of PCIE PLL Relative to BCLK(R/W).
772 @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
773 @param EAX Lower 32-bits of MSR value.
774 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
775 @param EDX Upper 32-bits of MSR value.
776 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
780 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;
782 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
783 AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);
785 @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
787 #define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E
790 MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
794 /// Individual bit fields
798 /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz
799 /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use
800 /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
803 UINT32 PCIERatio
: 2;
805 /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
808 UINT32 LPLLSelect
: 1;
810 /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
811 /// before re-locking Gen2/Gen3 PLLs.
813 UINT32 LONGRESET
: 1;
814 UINT32 Reserved1
: 28;
815 UINT32 Reserved2
: 32;
818 /// All bit fields as a 32-bit value
822 /// All bit fields as a 64-bit value
825 } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
;
828 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
829 fields represent the widest possible range of uncore frequencies. Writing to
830 these fields allows software to control the minimum and the maximum
831 frequency that hardware will select.
833 @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
834 @param EAX Lower 32-bits of MSR value.
835 Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
836 @param EDX Upper 32-bits of MSR value.
837 Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
841 MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
843 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
844 AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
847 #define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620
850 MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
854 /// Individual bit fields
858 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
861 UINT32 MAX_RATIO
: 7;
862 UINT32 Reserved1
: 1;
864 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
865 /// possible ratio of the LLC/Ring.
867 UINT32 MIN_RATIO
: 7;
868 UINT32 Reserved2
: 17;
869 UINT32 Reserved3
: 32;
872 /// All bit fields as a 32-bit value
876 /// All bit fields as a 64-bit value
879 } MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER
;
882 Package. Reserved (R/O) Reads return 0.
884 @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
885 @param EAX Lower 32-bits of MSR value.
886 @param EDX Upper 32-bits of MSR value.
892 Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);
894 @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
896 #define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639
899 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
900 refers to processor core frequency).
902 @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
903 @param EAX Lower 32-bits of MSR value.
904 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
905 @param EDX Upper 32-bits of MSR value.
906 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
910 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
912 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
913 AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
915 @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
917 #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690
920 MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
924 /// Individual bit fields
928 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
929 /// reduced below the operating system request due to assertion of
930 /// external PROCHOT.
932 UINT32 PROCHOT_Status
: 1;
934 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
935 /// operating system request due to a thermal event.
937 UINT32 ThermalStatus
: 1;
939 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
940 /// reduced below the operating system request due to PBM limit.
942 UINT32 PowerBudgetManagementStatus
: 1;
944 /// [Bit 3] Platform Configuration Services Status (R0) When set,
945 /// frequency is reduced below the operating system request due to PCS
948 UINT32 PlatformConfigurationServicesStatus
: 1;
949 UINT32 Reserved1
: 1;
951 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
952 /// When set, frequency is reduced below the operating system request
953 /// because the processor has detected that utilization is low.
955 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
: 1;
957 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
958 /// below the operating system request due to a thermal alert from the
959 /// Voltage Regulator.
961 UINT32 VRThermAlertStatus
: 1;
962 UINT32 Reserved2
: 1;
964 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
965 /// reduced below the operating system request due to electrical design
966 /// point constraints (e.g. maximum electrical current consumption).
968 UINT32 ElectricalDesignPointStatus
: 1;
969 UINT32 Reserved3
: 1;
971 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
972 /// below the operating system request due to Multi-Core Turbo limits.
974 UINT32 MultiCoreTurboStatus
: 1;
975 UINT32 Reserved4
: 2;
977 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
978 /// below max non-turbo P1.
980 UINT32 FrequencyP1Status
: 1;
982 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
983 /// set, frequency is reduced below max n-core turbo frequency.
985 UINT32 TurboFrequencyLimitingStatus
: 1;
987 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
988 /// reduced below the operating system request.
990 UINT32 FrequencyLimitingStatus
: 1;
992 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
993 /// has asserted since the log bit was last cleared. This log bit will
994 /// remain set until cleared by software writing 0.
996 UINT32 PROCHOT_Log
: 1;
998 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
999 /// has asserted since the log bit was last cleared. This log bit will
1000 /// remain set until cleared by software writing 0.
1002 UINT32 ThermalLog
: 1;
1004 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
1005 /// Status bit has asserted since the log bit was last cleared. This log
1006 /// bit will remain set until cleared by software writing 0.
1008 UINT32 PowerBudgetManagementLog
: 1;
1010 /// [Bit 19] Platform Configuration Services Log When set, indicates that
1011 /// the PCS Status bit has asserted since the log bit was last cleared.
1012 /// This log bit will remain set until cleared by software writing 0.
1014 UINT32 PlatformConfigurationServicesLog
: 1;
1015 UINT32 Reserved5
: 1;
1017 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1018 /// indicates that the AUBFC Status bit has asserted since the log bit was
1019 /// last cleared. This log bit will remain set until cleared by software
1022 UINT32 AutonomousUtilizationBasedFrequencyControlLog
: 1;
1024 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1025 /// Alert Status bit has asserted since the log bit was last cleared. This
1026 /// log bit will remain set until cleared by software writing 0.
1028 UINT32 VRThermAlertLog
: 1;
1029 UINT32 Reserved6
: 1;
1031 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1032 /// Status bit has asserted since the log bit was last cleared. This log
1033 /// bit will remain set until cleared by software writing 0.
1035 UINT32 ElectricalDesignPointLog
: 1;
1036 UINT32 Reserved7
: 1;
1038 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
1039 /// Turbo Status bit has asserted since the log bit was last cleared. This
1040 /// log bit will remain set until cleared by software writing 0.
1042 UINT32 MultiCoreTurboLog
: 1;
1043 UINT32 Reserved8
: 2;
1045 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
1046 /// Frequency P1 Status bit has asserted since the log bit was last
1047 /// cleared. This log bit will remain set until cleared by software
1050 UINT32 CoreFrequencyP1Log
: 1;
1052 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
1053 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
1054 /// has asserted since the log bit was last cleared. This log bit will
1055 /// remain set until cleared by software writing 0.
1057 UINT32 TurboFrequencyLimitingLog
: 1;
1059 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
1060 /// Frequency Limiting Status bit has asserted since the log bit was last
1061 /// cleared. This log bit will remain set until cleared by software
1064 UINT32 CoreFrequencyLimitingLog
: 1;
1065 UINT32 Reserved9
: 32;
1068 /// All bit fields as a 32-bit value
1072 /// All bit fields as a 64-bit value
1075 } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
;
1078 THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
1079 ECX=0):EBX.RDT-M[bit 12] = 1.
1081 @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
1082 @param EAX Lower 32-bits of MSR value.
1083 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1084 @param EDX Upper 32-bits of MSR value.
1085 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1087 <b>Example usage</b>
1089 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;
1091 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
1092 AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
1094 @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
1096 #define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D
1099 MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
1103 /// Individual bit fields
1107 /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
1108 /// occupancy monitoring all other encoding reserved..
1111 UINT32 Reserved1
: 24;
1113 /// [Bits 41:32] RMID (RW).
1116 UINT32 Reserved2
: 22;
1119 /// All bit fields as a 64-bit value
1122 } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
;
1125 THREAD. Resource Association Register (R/W)..
1127 @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
1128 @param EAX Lower 32-bits of MSR value.
1129 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1130 @param EDX Upper 32-bits of MSR value.
1131 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1133 <b>Example usage</b>
1135 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;
1137 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
1138 AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
1140 @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
1142 #define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F
1145 MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
1149 /// Individual bit fields
1153 /// [Bits 9:0] RMID.
1156 UINT32 Reserved1
: 22;
1157 UINT32 Reserved2
: 32;
1160 /// All bit fields as a 32-bit value
1164 /// All bit fields as a 64-bit value
1167 } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER
;
1170 Package. Uncore perfmon per-socket global control.
1172 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
1173 @param EAX Lower 32-bits of MSR value.
1174 @param EDX Upper 32-bits of MSR value.
1176 <b>Example usage</b>
1180 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
1181 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
1183 @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1185 #define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700
1188 Package. Uncore perfmon per-socket global status.
1190 @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
1191 @param EAX Lower 32-bits of MSR value.
1192 @param EDX Upper 32-bits of MSR value.
1194 <b>Example usage</b>
1198 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
1199 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
1201 @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1203 #define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701
1206 Package. Uncore perfmon per-socket global configuration.
1208 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
1209 @param EAX Lower 32-bits of MSR value.
1210 @param EDX Upper 32-bits of MSR value.
1212 <b>Example usage</b>
1216 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
1217 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
1219 @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1221 #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702
1224 Package. Uncore U-box UCLK fixed counter control.
1226 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
1227 @param EAX Lower 32-bits of MSR value.
1228 @param EDX Upper 32-bits of MSR value.
1230 <b>Example usage</b>
1234 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
1235 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
1237 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
1239 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703
1242 Package. Uncore U-box UCLK fixed counter.
1244 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
1245 @param EAX Lower 32-bits of MSR value.
1246 @param EDX Upper 32-bits of MSR value.
1248 <b>Example usage</b>
1252 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
1253 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
1255 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
1257 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704
1260 Package. Uncore U-box perfmon event select for U-box counter 0.
1262 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
1263 @param EAX Lower 32-bits of MSR value.
1264 @param EDX Upper 32-bits of MSR value.
1266 <b>Example usage</b>
1270 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
1271 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
1273 @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
1275 #define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705
1278 Package. Uncore U-box perfmon event select for U-box counter 1.
1280 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
1281 @param EAX Lower 32-bits of MSR value.
1282 @param EDX Upper 32-bits of MSR value.
1284 <b>Example usage</b>
1288 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
1289 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
1291 @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
1293 #define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706
1296 Package. Uncore U-box perfmon U-box wide status.
1298 @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
1299 @param EAX Lower 32-bits of MSR value.
1300 @param EDX Upper 32-bits of MSR value.
1302 <b>Example usage</b>
1306 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
1307 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
1309 @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1311 #define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708
1314 Package. Uncore U-box perfmon counter 0.
1316 @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
1317 @param EAX Lower 32-bits of MSR value.
1318 @param EDX Upper 32-bits of MSR value.
1320 <b>Example usage</b>
1324 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
1325 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
1327 @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
1329 #define MSR_HASWELL_E_U_PMON_CTR0 0x00000709
1332 Package. Uncore U-box perfmon counter 1.
1334 @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
1335 @param EAX Lower 32-bits of MSR value.
1336 @param EDX Upper 32-bits of MSR value.
1338 <b>Example usage</b>
1342 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
1343 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
1345 @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
1347 #define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A
1350 Package. Uncore PCU perfmon for PCU-box-wide control.
1352 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
1353 @param EAX Lower 32-bits of MSR value.
1354 @param EDX Upper 32-bits of MSR value.
1356 <b>Example usage</b>
1360 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
1361 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
1363 @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
1365 #define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710
1368 Package. Uncore PCU perfmon event select for PCU counter 0.
1370 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
1371 @param EAX Lower 32-bits of MSR value.
1372 @param EDX Upper 32-bits of MSR value.
1374 <b>Example usage</b>
1378 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
1379 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
1381 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
1383 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711
1386 Package. Uncore PCU perfmon event select for PCU counter 1.
1388 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
1389 @param EAX Lower 32-bits of MSR value.
1390 @param EDX Upper 32-bits of MSR value.
1392 <b>Example usage</b>
1396 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
1397 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
1399 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
1401 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712
1404 Package. Uncore PCU perfmon event select for PCU counter 2.
1406 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
1407 @param EAX Lower 32-bits of MSR value.
1408 @param EDX Upper 32-bits of MSR value.
1410 <b>Example usage</b>
1414 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
1415 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
1417 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
1419 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713
1422 Package. Uncore PCU perfmon event select for PCU counter 3.
1424 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
1425 @param EAX Lower 32-bits of MSR value.
1426 @param EDX Upper 32-bits of MSR value.
1428 <b>Example usage</b>
1432 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
1433 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
1435 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
1437 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714
1440 Package. Uncore PCU perfmon box-wide filter.
1442 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
1443 @param EAX Lower 32-bits of MSR value.
1444 @param EDX Upper 32-bits of MSR value.
1446 <b>Example usage</b>
1450 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
1451 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
1453 @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
1455 #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715
1458 Package. Uncore PCU perfmon box wide status.
1460 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
1461 @param EAX Lower 32-bits of MSR value.
1462 @param EDX Upper 32-bits of MSR value.
1464 <b>Example usage</b>
1468 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
1469 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
1471 @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1473 #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716
1476 Package. Uncore PCU perfmon counter 0.
1478 @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
1479 @param EAX Lower 32-bits of MSR value.
1480 @param EDX Upper 32-bits of MSR value.
1482 <b>Example usage</b>
1486 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
1487 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
1489 @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
1491 #define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717
1494 Package. Uncore PCU perfmon counter 1.
1496 @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
1497 @param EAX Lower 32-bits of MSR value.
1498 @param EDX Upper 32-bits of MSR value.
1500 <b>Example usage</b>
1504 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
1505 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
1507 @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
1509 #define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718
1512 Package. Uncore PCU perfmon counter 2.
1514 @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
1515 @param EAX Lower 32-bits of MSR value.
1516 @param EDX Upper 32-bits of MSR value.
1518 <b>Example usage</b>
1522 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
1523 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
1525 @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
1527 #define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719
1530 Package. Uncore PCU perfmon counter 3.
1532 @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
1533 @param EAX Lower 32-bits of MSR value.
1534 @param EDX Upper 32-bits of MSR value.
1536 <b>Example usage</b>
1540 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
1541 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
1543 @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
1545 #define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A
1548 Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
1550 @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
1551 @param EAX Lower 32-bits of MSR value.
1552 @param EDX Upper 32-bits of MSR value.
1554 <b>Example usage</b>
1558 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
1559 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
1561 @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
1563 #define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720
1566 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
1568 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
1569 @param EAX Lower 32-bits of MSR value.
1570 @param EDX Upper 32-bits of MSR value.
1572 <b>Example usage</b>
1576 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
1577 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
1579 @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
1581 #define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721
1584 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
1586 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
1587 @param EAX Lower 32-bits of MSR value.
1588 @param EDX Upper 32-bits of MSR value.
1590 <b>Example usage</b>
1594 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
1595 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
1597 @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
1599 #define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722
1602 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
1604 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
1605 @param EAX Lower 32-bits of MSR value.
1606 @param EDX Upper 32-bits of MSR value.
1608 <b>Example usage</b>
1612 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
1613 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
1615 @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
1617 #define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723
1620 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
1622 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
1623 @param EAX Lower 32-bits of MSR value.
1624 @param EDX Upper 32-bits of MSR value.
1626 <b>Example usage</b>
1630 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
1631 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
1633 @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
1635 #define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724
1638 Package. Uncore SBo 0 perfmon box-wide filter.
1640 @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
1641 @param EAX Lower 32-bits of MSR value.
1642 @param EDX Upper 32-bits of MSR value.
1644 <b>Example usage</b>
1648 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
1649 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
1651 @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
1653 #define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725
1656 Package. Uncore SBo 0 perfmon counter 0.
1658 @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
1659 @param EAX Lower 32-bits of MSR value.
1660 @param EDX Upper 32-bits of MSR value.
1662 <b>Example usage</b>
1666 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
1667 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
1669 @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
1671 #define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726
1674 Package. Uncore SBo 0 perfmon counter 1.
1676 @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
1677 @param EAX Lower 32-bits of MSR value.
1678 @param EDX Upper 32-bits of MSR value.
1680 <b>Example usage</b>
1684 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
1685 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
1687 @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
1689 #define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727
1692 Package. Uncore SBo 0 perfmon counter 2.
1694 @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
1695 @param EAX Lower 32-bits of MSR value.
1696 @param EDX Upper 32-bits of MSR value.
1698 <b>Example usage</b>
1702 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
1703 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
1705 @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
1707 #define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728
1710 Package. Uncore SBo 0 perfmon counter 3.
1712 @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
1713 @param EAX Lower 32-bits of MSR value.
1714 @param EDX Upper 32-bits of MSR value.
1716 <b>Example usage</b>
1720 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
1721 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
1723 @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
1725 #define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729
1728 Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
1730 @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
1731 @param EAX Lower 32-bits of MSR value.
1732 @param EDX Upper 32-bits of MSR value.
1734 <b>Example usage</b>
1738 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
1739 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
1741 @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
1743 #define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A
1746 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
1748 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
1749 @param EAX Lower 32-bits of MSR value.
1750 @param EDX Upper 32-bits of MSR value.
1752 <b>Example usage</b>
1756 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
1757 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
1759 @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
1761 #define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B
1764 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
1766 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
1767 @param EAX Lower 32-bits of MSR value.
1768 @param EDX Upper 32-bits of MSR value.
1770 <b>Example usage</b>
1774 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
1775 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
1777 @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
1779 #define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C
1782 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
1784 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
1785 @param EAX Lower 32-bits of MSR value.
1786 @param EDX Upper 32-bits of MSR value.
1788 <b>Example usage</b>
1792 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
1793 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
1795 @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
1797 #define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D
1800 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
1802 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
1803 @param EAX Lower 32-bits of MSR value.
1804 @param EDX Upper 32-bits of MSR value.
1806 <b>Example usage</b>
1810 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
1811 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
1813 @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
1815 #define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E
1818 Package. Uncore SBo 1 perfmon box-wide filter.
1820 @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
1821 @param EAX Lower 32-bits of MSR value.
1822 @param EDX Upper 32-bits of MSR value.
1824 <b>Example usage</b>
1828 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
1829 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
1831 @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
1833 #define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F
1836 Package. Uncore SBo 1 perfmon counter 0.
1838 @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
1839 @param EAX Lower 32-bits of MSR value.
1840 @param EDX Upper 32-bits of MSR value.
1842 <b>Example usage</b>
1846 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
1847 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
1849 @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
1851 #define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730
1854 Package. Uncore SBo 1 perfmon counter 1.
1856 @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
1857 @param EAX Lower 32-bits of MSR value.
1858 @param EDX Upper 32-bits of MSR value.
1860 <b>Example usage</b>
1864 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
1865 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
1867 @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
1869 #define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731
1872 Package. Uncore SBo 1 perfmon counter 2.
1874 @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
1875 @param EAX Lower 32-bits of MSR value.
1876 @param EDX Upper 32-bits of MSR value.
1878 <b>Example usage</b>
1882 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
1883 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
1885 @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
1887 #define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732
1890 Package. Uncore SBo 1 perfmon counter 3.
1892 @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
1893 @param EAX Lower 32-bits of MSR value.
1894 @param EDX Upper 32-bits of MSR value.
1896 <b>Example usage</b>
1900 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
1901 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
1903 @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
1905 #define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733
1908 Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
1910 @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
1911 @param EAX Lower 32-bits of MSR value.
1912 @param EDX Upper 32-bits of MSR value.
1914 <b>Example usage</b>
1918 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
1919 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
1921 @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
1923 #define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734
1926 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
1928 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
1929 @param EAX Lower 32-bits of MSR value.
1930 @param EDX Upper 32-bits of MSR value.
1932 <b>Example usage</b>
1936 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
1937 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
1939 @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
1941 #define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735
1944 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
1946 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
1947 @param EAX Lower 32-bits of MSR value.
1948 @param EDX Upper 32-bits of MSR value.
1950 <b>Example usage</b>
1954 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
1955 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
1957 @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
1959 #define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736
1962 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
1964 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
1965 @param EAX Lower 32-bits of MSR value.
1966 @param EDX Upper 32-bits of MSR value.
1968 <b>Example usage</b>
1972 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
1973 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
1975 @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
1977 #define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737
1980 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
1982 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
1983 @param EAX Lower 32-bits of MSR value.
1984 @param EDX Upper 32-bits of MSR value.
1986 <b>Example usage</b>
1990 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
1991 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
1993 @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
1995 #define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738
1998 Package. Uncore SBo 2 perfmon box-wide filter.
2000 @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
2001 @param EAX Lower 32-bits of MSR value.
2002 @param EDX Upper 32-bits of MSR value.
2004 <b>Example usage</b>
2008 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
2009 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
2011 @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
2013 #define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739
2016 Package. Uncore SBo 2 perfmon counter 0.
2018 @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
2019 @param EAX Lower 32-bits of MSR value.
2020 @param EDX Upper 32-bits of MSR value.
2022 <b>Example usage</b>
2026 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
2027 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
2029 @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
2031 #define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A
2034 Package. Uncore SBo 2 perfmon counter 1.
2036 @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
2037 @param EAX Lower 32-bits of MSR value.
2038 @param EDX Upper 32-bits of MSR value.
2040 <b>Example usage</b>
2044 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
2045 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
2047 @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
2049 #define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B
2052 Package. Uncore SBo 2 perfmon counter 2.
2054 @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
2055 @param EAX Lower 32-bits of MSR value.
2056 @param EDX Upper 32-bits of MSR value.
2058 <b>Example usage</b>
2062 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
2063 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
2065 @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
2067 #define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C
2070 Package. Uncore SBo 2 perfmon counter 3.
2072 @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
2073 @param EAX Lower 32-bits of MSR value.
2074 @param EDX Upper 32-bits of MSR value.
2076 <b>Example usage</b>
2080 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
2081 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
2083 @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
2085 #define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D
2088 Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
2090 @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
2091 @param EAX Lower 32-bits of MSR value.
2092 @param EDX Upper 32-bits of MSR value.
2094 <b>Example usage</b>
2098 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
2099 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
2101 @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
2103 #define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E
2106 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
2108 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
2109 @param EAX Lower 32-bits of MSR value.
2110 @param EDX Upper 32-bits of MSR value.
2112 <b>Example usage</b>
2116 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
2117 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
2119 @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
2121 #define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F
2124 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
2126 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
2127 @param EAX Lower 32-bits of MSR value.
2128 @param EDX Upper 32-bits of MSR value.
2130 <b>Example usage</b>
2134 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
2135 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
2137 @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
2139 #define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740
2142 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
2144 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
2145 @param EAX Lower 32-bits of MSR value.
2146 @param EDX Upper 32-bits of MSR value.
2148 <b>Example usage</b>
2152 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
2153 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
2155 @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
2157 #define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741
2160 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
2162 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
2163 @param EAX Lower 32-bits of MSR value.
2164 @param EDX Upper 32-bits of MSR value.
2166 <b>Example usage</b>
2170 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
2171 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
2173 @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
2175 #define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742
2178 Package. Uncore SBo 3 perfmon box-wide filter.
2180 @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
2181 @param EAX Lower 32-bits of MSR value.
2182 @param EDX Upper 32-bits of MSR value.
2184 <b>Example usage</b>
2188 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
2189 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
2191 @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
2193 #define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743
2196 Package. Uncore SBo 3 perfmon counter 0.
2198 @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
2199 @param EAX Lower 32-bits of MSR value.
2200 @param EDX Upper 32-bits of MSR value.
2202 <b>Example usage</b>
2206 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
2207 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
2209 @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
2211 #define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744
2214 Package. Uncore SBo 3 perfmon counter 1.
2216 @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
2217 @param EAX Lower 32-bits of MSR value.
2218 @param EDX Upper 32-bits of MSR value.
2220 <b>Example usage</b>
2224 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
2225 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
2227 @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
2229 #define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745
2232 Package. Uncore SBo 3 perfmon counter 2.
2234 @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
2235 @param EAX Lower 32-bits of MSR value.
2236 @param EDX Upper 32-bits of MSR value.
2238 <b>Example usage</b>
2242 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
2243 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
2245 @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
2247 #define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746
2250 Package. Uncore SBo 3 perfmon counter 3.
2252 @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
2253 @param EAX Lower 32-bits of MSR value.
2254 @param EDX Upper 32-bits of MSR value.
2256 <b>Example usage</b>
2260 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
2261 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
2263 @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
2265 #define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747
2268 Package. Uncore C-box 0 perfmon for box-wide control.
2270 @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
2271 @param EAX Lower 32-bits of MSR value.
2272 @param EDX Upper 32-bits of MSR value.
2274 <b>Example usage</b>
2278 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
2279 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
2281 @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
2283 #define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00
2286 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
2288 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
2289 @param EAX Lower 32-bits of MSR value.
2290 @param EDX Upper 32-bits of MSR value.
2292 <b>Example usage</b>
2296 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
2297 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
2299 @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
2301 #define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01
2304 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
2306 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
2307 @param EAX Lower 32-bits of MSR value.
2308 @param EDX Upper 32-bits of MSR value.
2310 <b>Example usage</b>
2314 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
2315 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
2317 @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
2319 #define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02
2322 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
2324 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
2325 @param EAX Lower 32-bits of MSR value.
2326 @param EDX Upper 32-bits of MSR value.
2328 <b>Example usage</b>
2332 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
2333 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
2335 @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
2337 #define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03
2340 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
2342 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
2343 @param EAX Lower 32-bits of MSR value.
2344 @param EDX Upper 32-bits of MSR value.
2346 <b>Example usage</b>
2350 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
2351 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
2353 @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
2355 #define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04
2358 Package. Uncore C-box 0 perfmon box wide filter 0.
2360 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
2361 @param EAX Lower 32-bits of MSR value.
2362 @param EDX Upper 32-bits of MSR value.
2364 <b>Example usage</b>
2368 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
2369 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
2371 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
2373 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05
2376 Package. Uncore C-box 0 perfmon box wide filter 1.
2378 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
2379 @param EAX Lower 32-bits of MSR value.
2380 @param EDX Upper 32-bits of MSR value.
2382 <b>Example usage</b>
2386 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
2387 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
2389 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
2391 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06
2394 Package. Uncore C-box 0 perfmon box wide status.
2396 @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
2397 @param EAX Lower 32-bits of MSR value.
2398 @param EDX Upper 32-bits of MSR value.
2400 <b>Example usage</b>
2404 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
2405 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
2407 @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
2409 #define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07
2412 Package. Uncore C-box 0 perfmon counter 0.
2414 @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
2415 @param EAX Lower 32-bits of MSR value.
2416 @param EDX Upper 32-bits of MSR value.
2418 <b>Example usage</b>
2422 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
2423 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
2425 @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
2427 #define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08
2430 Package. Uncore C-box 0 perfmon counter 1.
2432 @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
2433 @param EAX Lower 32-bits of MSR value.
2434 @param EDX Upper 32-bits of MSR value.
2436 <b>Example usage</b>
2440 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
2441 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
2443 @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
2445 #define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09
2448 Package. Uncore C-box 0 perfmon counter 2.
2450 @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
2451 @param EAX Lower 32-bits of MSR value.
2452 @param EDX Upper 32-bits of MSR value.
2454 <b>Example usage</b>
2458 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
2459 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
2461 @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
2463 #define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A
2466 Package. Uncore C-box 0 perfmon counter 3.
2468 @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
2469 @param EAX Lower 32-bits of MSR value.
2470 @param EDX Upper 32-bits of MSR value.
2472 <b>Example usage</b>
2476 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
2477 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
2479 @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
2481 #define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B
2484 Package. Uncore C-box 1 perfmon for box-wide control.
2486 @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
2487 @param EAX Lower 32-bits of MSR value.
2488 @param EDX Upper 32-bits of MSR value.
2490 <b>Example usage</b>
2494 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
2495 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
2497 @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
2499 #define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10
2502 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
2504 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
2505 @param EAX Lower 32-bits of MSR value.
2506 @param EDX Upper 32-bits of MSR value.
2508 <b>Example usage</b>
2512 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
2513 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
2515 @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
2517 #define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11
2520 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
2522 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
2523 @param EAX Lower 32-bits of MSR value.
2524 @param EDX Upper 32-bits of MSR value.
2526 <b>Example usage</b>
2530 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
2531 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
2533 @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
2535 #define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12
2538 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
2540 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
2541 @param EAX Lower 32-bits of MSR value.
2542 @param EDX Upper 32-bits of MSR value.
2544 <b>Example usage</b>
2548 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
2549 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
2551 @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
2553 #define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13
2556 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
2558 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
2559 @param EAX Lower 32-bits of MSR value.
2560 @param EDX Upper 32-bits of MSR value.
2562 <b>Example usage</b>
2566 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
2567 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
2569 @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
2571 #define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14
2574 Package. Uncore C-box 1 perfmon box wide filter 0.
2576 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
2577 @param EAX Lower 32-bits of MSR value.
2578 @param EDX Upper 32-bits of MSR value.
2580 <b>Example usage</b>
2584 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
2585 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
2587 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
2589 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15
2592 Package. Uncore C-box 1 perfmon box wide filter1.
2594 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
2595 @param EAX Lower 32-bits of MSR value.
2596 @param EDX Upper 32-bits of MSR value.
2598 <b>Example usage</b>
2602 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
2603 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
2605 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
2607 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16
2610 Package. Uncore C-box 1 perfmon box wide status.
2612 @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
2613 @param EAX Lower 32-bits of MSR value.
2614 @param EDX Upper 32-bits of MSR value.
2616 <b>Example usage</b>
2620 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
2621 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
2623 @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
2625 #define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17
2628 Package. Uncore C-box 1 perfmon counter 0.
2630 @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
2631 @param EAX Lower 32-bits of MSR value.
2632 @param EDX Upper 32-bits of MSR value.
2634 <b>Example usage</b>
2638 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
2639 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
2641 @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
2643 #define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18
2646 Package. Uncore C-box 1 perfmon counter 1.
2648 @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
2649 @param EAX Lower 32-bits of MSR value.
2650 @param EDX Upper 32-bits of MSR value.
2652 <b>Example usage</b>
2656 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
2657 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
2659 @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
2661 #define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19
2664 Package. Uncore C-box 1 perfmon counter 2.
2666 @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
2667 @param EAX Lower 32-bits of MSR value.
2668 @param EDX Upper 32-bits of MSR value.
2670 <b>Example usage</b>
2674 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
2675 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
2677 @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
2679 #define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A
2682 Package. Uncore C-box 1 perfmon counter 3.
2684 @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
2685 @param EAX Lower 32-bits of MSR value.
2686 @param EDX Upper 32-bits of MSR value.
2688 <b>Example usage</b>
2692 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
2693 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
2695 @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
2697 #define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B
2700 Package. Uncore C-box 2 perfmon for box-wide control.
2702 @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
2703 @param EAX Lower 32-bits of MSR value.
2704 @param EDX Upper 32-bits of MSR value.
2706 <b>Example usage</b>
2710 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
2711 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
2713 @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
2715 #define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20
2718 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
2720 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
2721 @param EAX Lower 32-bits of MSR value.
2722 @param EDX Upper 32-bits of MSR value.
2724 <b>Example usage</b>
2728 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
2729 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
2731 @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
2733 #define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21
2736 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
2738 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
2739 @param EAX Lower 32-bits of MSR value.
2740 @param EDX Upper 32-bits of MSR value.
2742 <b>Example usage</b>
2746 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
2747 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
2749 @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
2751 #define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22
2754 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
2756 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
2757 @param EAX Lower 32-bits of MSR value.
2758 @param EDX Upper 32-bits of MSR value.
2760 <b>Example usage</b>
2764 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
2765 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
2767 @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
2769 #define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23
2772 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
2774 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
2775 @param EAX Lower 32-bits of MSR value.
2776 @param EDX Upper 32-bits of MSR value.
2778 <b>Example usage</b>
2782 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
2783 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
2785 @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
2787 #define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24
2790 Package. Uncore C-box 2 perfmon box wide filter 0.
2792 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
2793 @param EAX Lower 32-bits of MSR value.
2794 @param EDX Upper 32-bits of MSR value.
2796 <b>Example usage</b>
2800 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
2801 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
2803 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
2805 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25
2808 Package. Uncore C-box 2 perfmon box wide filter1.
2810 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
2811 @param EAX Lower 32-bits of MSR value.
2812 @param EDX Upper 32-bits of MSR value.
2814 <b>Example usage</b>
2818 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
2819 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
2821 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
2823 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26
2826 Package. Uncore C-box 2 perfmon box wide status.
2828 @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
2829 @param EAX Lower 32-bits of MSR value.
2830 @param EDX Upper 32-bits of MSR value.
2832 <b>Example usage</b>
2836 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
2837 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
2839 @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
2841 #define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27
2844 Package. Uncore C-box 2 perfmon counter 0.
2846 @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
2847 @param EAX Lower 32-bits of MSR value.
2848 @param EDX Upper 32-bits of MSR value.
2850 <b>Example usage</b>
2854 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
2855 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
2857 @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
2859 #define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28
2862 Package. Uncore C-box 2 perfmon counter 1.
2864 @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
2865 @param EAX Lower 32-bits of MSR value.
2866 @param EDX Upper 32-bits of MSR value.
2868 <b>Example usage</b>
2872 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
2873 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
2875 @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
2877 #define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29
2880 Package. Uncore C-box 2 perfmon counter 2.
2882 @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
2883 @param EAX Lower 32-bits of MSR value.
2884 @param EDX Upper 32-bits of MSR value.
2886 <b>Example usage</b>
2890 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
2891 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
2893 @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
2895 #define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A
2898 Package. Uncore C-box 2 perfmon counter 3.
2900 @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
2901 @param EAX Lower 32-bits of MSR value.
2902 @param EDX Upper 32-bits of MSR value.
2904 <b>Example usage</b>
2908 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
2909 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
2911 @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
2913 #define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B
2916 Package. Uncore C-box 3 perfmon for box-wide control.
2918 @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
2919 @param EAX Lower 32-bits of MSR value.
2920 @param EDX Upper 32-bits of MSR value.
2922 <b>Example usage</b>
2926 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
2927 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
2929 @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
2931 #define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30
2934 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
2936 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
2937 @param EAX Lower 32-bits of MSR value.
2938 @param EDX Upper 32-bits of MSR value.
2940 <b>Example usage</b>
2944 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
2945 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
2947 @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
2949 #define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31
2952 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
2954 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
2955 @param EAX Lower 32-bits of MSR value.
2956 @param EDX Upper 32-bits of MSR value.
2958 <b>Example usage</b>
2962 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
2963 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
2965 @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
2967 #define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32
2970 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
2972 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
2973 @param EAX Lower 32-bits of MSR value.
2974 @param EDX Upper 32-bits of MSR value.
2976 <b>Example usage</b>
2980 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
2981 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
2983 @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
2985 #define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33
2988 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
2990 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
2991 @param EAX Lower 32-bits of MSR value.
2992 @param EDX Upper 32-bits of MSR value.
2994 <b>Example usage</b>
2998 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
2999 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
3001 @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3003 #define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34
3006 Package. Uncore C-box 3 perfmon box wide filter 0.
3008 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
3009 @param EAX Lower 32-bits of MSR value.
3010 @param EDX Upper 32-bits of MSR value.
3012 <b>Example usage</b>
3016 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
3017 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
3019 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
3021 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35
3024 Package. Uncore C-box 3 perfmon box wide filter1.
3026 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
3027 @param EAX Lower 32-bits of MSR value.
3028 @param EDX Upper 32-bits of MSR value.
3030 <b>Example usage</b>
3034 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
3035 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
3037 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
3039 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36
3042 Package. Uncore C-box 3 perfmon box wide status.
3044 @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
3045 @param EAX Lower 32-bits of MSR value.
3046 @param EDX Upper 32-bits of MSR value.
3048 <b>Example usage</b>
3052 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
3053 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
3055 @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
3057 #define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37
3060 Package. Uncore C-box 3 perfmon counter 0.
3062 @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
3063 @param EAX Lower 32-bits of MSR value.
3064 @param EDX Upper 32-bits of MSR value.
3066 <b>Example usage</b>
3070 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
3071 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
3073 @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3075 #define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38
3078 Package. Uncore C-box 3 perfmon counter 1.
3080 @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
3081 @param EAX Lower 32-bits of MSR value.
3082 @param EDX Upper 32-bits of MSR value.
3084 <b>Example usage</b>
3088 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
3089 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
3091 @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3093 #define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39
3096 Package. Uncore C-box 3 perfmon counter 2.
3098 @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
3099 @param EAX Lower 32-bits of MSR value.
3100 @param EDX Upper 32-bits of MSR value.
3102 <b>Example usage</b>
3106 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
3107 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
3109 @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
3111 #define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A
3114 Package. Uncore C-box 3 perfmon counter 3.
3116 @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
3117 @param EAX Lower 32-bits of MSR value.
3118 @param EDX Upper 32-bits of MSR value.
3120 <b>Example usage</b>
3124 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
3125 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
3127 @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
3129 #define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B
3132 Package. Uncore C-box 4 perfmon for box-wide control.
3134 @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
3135 @param EAX Lower 32-bits of MSR value.
3136 @param EDX Upper 32-bits of MSR value.
3138 <b>Example usage</b>
3142 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
3143 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
3145 @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
3147 #define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40
3150 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
3152 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
3153 @param EAX Lower 32-bits of MSR value.
3154 @param EDX Upper 32-bits of MSR value.
3156 <b>Example usage</b>
3160 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
3161 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
3163 @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
3165 #define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41
3168 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
3170 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
3171 @param EAX Lower 32-bits of MSR value.
3172 @param EDX Upper 32-bits of MSR value.
3174 <b>Example usage</b>
3178 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
3179 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
3181 @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
3183 #define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42
3186 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
3188 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
3189 @param EAX Lower 32-bits of MSR value.
3190 @param EDX Upper 32-bits of MSR value.
3192 <b>Example usage</b>
3196 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
3197 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
3199 @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
3201 #define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43
3204 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
3206 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
3207 @param EAX Lower 32-bits of MSR value.
3208 @param EDX Upper 32-bits of MSR value.
3210 <b>Example usage</b>
3214 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
3215 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
3217 @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
3219 #define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44
3222 Package. Uncore C-box 4 perfmon box wide filter 0.
3224 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
3225 @param EAX Lower 32-bits of MSR value.
3226 @param EDX Upper 32-bits of MSR value.
3228 <b>Example usage</b>
3232 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
3233 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
3235 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
3237 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45
3240 Package. Uncore C-box 4 perfmon box wide filter1.
3242 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
3243 @param EAX Lower 32-bits of MSR value.
3244 @param EDX Upper 32-bits of MSR value.
3246 <b>Example usage</b>
3250 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
3251 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
3253 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
3255 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46
3258 Package. Uncore C-box 4 perfmon box wide status.
3260 @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
3261 @param EAX Lower 32-bits of MSR value.
3262 @param EDX Upper 32-bits of MSR value.
3264 <b>Example usage</b>
3268 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
3269 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
3271 @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
3273 #define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47
3276 Package. Uncore C-box 4 perfmon counter 0.
3278 @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
3279 @param EAX Lower 32-bits of MSR value.
3280 @param EDX Upper 32-bits of MSR value.
3282 <b>Example usage</b>
3286 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
3287 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
3289 @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
3291 #define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48
3294 Package. Uncore C-box 4 perfmon counter 1.
3296 @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
3297 @param EAX Lower 32-bits of MSR value.
3298 @param EDX Upper 32-bits of MSR value.
3300 <b>Example usage</b>
3304 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
3305 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
3307 @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
3309 #define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49
3312 Package. Uncore C-box 4 perfmon counter 2.
3314 @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
3315 @param EAX Lower 32-bits of MSR value.
3316 @param EDX Upper 32-bits of MSR value.
3318 <b>Example usage</b>
3322 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
3323 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
3325 @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
3327 #define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A
3330 Package. Uncore C-box 4 perfmon counter 3.
3332 @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
3333 @param EAX Lower 32-bits of MSR value.
3334 @param EDX Upper 32-bits of MSR value.
3336 <b>Example usage</b>
3340 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
3341 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
3343 @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
3345 #define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B
3348 Package. Uncore C-box 5 perfmon for box-wide control.
3350 @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
3351 @param EAX Lower 32-bits of MSR value.
3352 @param EDX Upper 32-bits of MSR value.
3354 <b>Example usage</b>
3358 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
3359 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
3361 @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
3363 #define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50
3366 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
3368 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
3369 @param EAX Lower 32-bits of MSR value.
3370 @param EDX Upper 32-bits of MSR value.
3372 <b>Example usage</b>
3376 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
3377 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
3379 @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
3381 #define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51
3384 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
3386 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
3387 @param EAX Lower 32-bits of MSR value.
3388 @param EDX Upper 32-bits of MSR value.
3390 <b>Example usage</b>
3394 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
3395 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
3397 @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
3399 #define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52
3402 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
3404 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
3405 @param EAX Lower 32-bits of MSR value.
3406 @param EDX Upper 32-bits of MSR value.
3408 <b>Example usage</b>
3412 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
3413 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
3415 @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
3417 #define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53
3420 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
3422 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
3423 @param EAX Lower 32-bits of MSR value.
3424 @param EDX Upper 32-bits of MSR value.
3426 <b>Example usage</b>
3430 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
3431 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
3433 @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
3435 #define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54
3438 Package. Uncore C-box 5 perfmon box wide filter 0.
3440 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
3441 @param EAX Lower 32-bits of MSR value.
3442 @param EDX Upper 32-bits of MSR value.
3444 <b>Example usage</b>
3448 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
3449 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
3451 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
3453 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55
3456 Package. Uncore C-box 5 perfmon box wide filter1.
3458 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
3459 @param EAX Lower 32-bits of MSR value.
3460 @param EDX Upper 32-bits of MSR value.
3462 <b>Example usage</b>
3466 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
3467 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
3469 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
3471 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56
3474 Package. Uncore C-box 5 perfmon box wide status.
3476 @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
3477 @param EAX Lower 32-bits of MSR value.
3478 @param EDX Upper 32-bits of MSR value.
3480 <b>Example usage</b>
3484 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
3485 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
3487 @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
3489 #define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57
3492 Package. Uncore C-box 5 perfmon counter 0.
3494 @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
3495 @param EAX Lower 32-bits of MSR value.
3496 @param EDX Upper 32-bits of MSR value.
3498 <b>Example usage</b>
3502 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
3503 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
3505 @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
3507 #define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58
3510 Package. Uncore C-box 5 perfmon counter 1.
3512 @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
3513 @param EAX Lower 32-bits of MSR value.
3514 @param EDX Upper 32-bits of MSR value.
3516 <b>Example usage</b>
3520 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
3521 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
3523 @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
3525 #define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59
3528 Package. Uncore C-box 5 perfmon counter 2.
3530 @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
3531 @param EAX Lower 32-bits of MSR value.
3532 @param EDX Upper 32-bits of MSR value.
3534 <b>Example usage</b>
3538 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
3539 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
3541 @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
3543 #define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A
3546 Package. Uncore C-box 5 perfmon counter 3.
3548 @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
3549 @param EAX Lower 32-bits of MSR value.
3550 @param EDX Upper 32-bits of MSR value.
3552 <b>Example usage</b>
3556 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
3557 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
3559 @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
3561 #define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B
3564 Package. Uncore C-box 6 perfmon for box-wide control.
3566 @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
3567 @param EAX Lower 32-bits of MSR value.
3568 @param EDX Upper 32-bits of MSR value.
3570 <b>Example usage</b>
3574 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
3575 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
3577 @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
3579 #define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60
3582 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
3584 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
3585 @param EAX Lower 32-bits of MSR value.
3586 @param EDX Upper 32-bits of MSR value.
3588 <b>Example usage</b>
3592 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
3593 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
3595 @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
3597 #define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61
3600 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
3602 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
3603 @param EAX Lower 32-bits of MSR value.
3604 @param EDX Upper 32-bits of MSR value.
3606 <b>Example usage</b>
3610 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
3611 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
3613 @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
3615 #define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62
3618 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
3620 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
3621 @param EAX Lower 32-bits of MSR value.
3622 @param EDX Upper 32-bits of MSR value.
3624 <b>Example usage</b>
3628 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
3629 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
3631 @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
3633 #define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63
3636 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
3638 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
3639 @param EAX Lower 32-bits of MSR value.
3640 @param EDX Upper 32-bits of MSR value.
3642 <b>Example usage</b>
3646 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
3647 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
3649 @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
3651 #define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64
3654 Package. Uncore C-box 6 perfmon box wide filter 0.
3656 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
3657 @param EAX Lower 32-bits of MSR value.
3658 @param EDX Upper 32-bits of MSR value.
3660 <b>Example usage</b>
3664 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
3665 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
3667 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
3669 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65
3672 Package. Uncore C-box 6 perfmon box wide filter1.
3674 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
3675 @param EAX Lower 32-bits of MSR value.
3676 @param EDX Upper 32-bits of MSR value.
3678 <b>Example usage</b>
3682 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
3683 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
3685 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
3687 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66
3690 Package. Uncore C-box 6 perfmon box wide status.
3692 @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
3693 @param EAX Lower 32-bits of MSR value.
3694 @param EDX Upper 32-bits of MSR value.
3696 <b>Example usage</b>
3700 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
3701 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
3703 @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
3705 #define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67
3708 Package. Uncore C-box 6 perfmon counter 0.
3710 @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
3711 @param EAX Lower 32-bits of MSR value.
3712 @param EDX Upper 32-bits of MSR value.
3714 <b>Example usage</b>
3718 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
3719 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
3721 @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
3723 #define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68
3726 Package. Uncore C-box 6 perfmon counter 1.
3728 @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
3729 @param EAX Lower 32-bits of MSR value.
3730 @param EDX Upper 32-bits of MSR value.
3732 <b>Example usage</b>
3736 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
3737 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
3739 @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
3741 #define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69
3744 Package. Uncore C-box 6 perfmon counter 2.
3746 @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
3747 @param EAX Lower 32-bits of MSR value.
3748 @param EDX Upper 32-bits of MSR value.
3750 <b>Example usage</b>
3754 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
3755 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
3757 @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
3759 #define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A
3762 Package. Uncore C-box 6 perfmon counter 3.
3764 @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
3765 @param EAX Lower 32-bits of MSR value.
3766 @param EDX Upper 32-bits of MSR value.
3768 <b>Example usage</b>
3772 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
3773 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
3775 @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
3777 #define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B
3780 Package. Uncore C-box 7 perfmon for box-wide control.
3782 @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
3783 @param EAX Lower 32-bits of MSR value.
3784 @param EDX Upper 32-bits of MSR value.
3786 <b>Example usage</b>
3790 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
3791 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
3793 @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
3795 #define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70
3798 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
3800 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
3801 @param EAX Lower 32-bits of MSR value.
3802 @param EDX Upper 32-bits of MSR value.
3804 <b>Example usage</b>
3808 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
3809 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
3811 @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
3813 #define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71
3816 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
3818 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
3819 @param EAX Lower 32-bits of MSR value.
3820 @param EDX Upper 32-bits of MSR value.
3822 <b>Example usage</b>
3826 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
3827 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
3829 @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
3831 #define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72
3834 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
3836 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
3837 @param EAX Lower 32-bits of MSR value.
3838 @param EDX Upper 32-bits of MSR value.
3840 <b>Example usage</b>
3844 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
3845 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
3847 @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
3849 #define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73
3852 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
3854 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
3855 @param EAX Lower 32-bits of MSR value.
3856 @param EDX Upper 32-bits of MSR value.
3858 <b>Example usage</b>
3862 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
3863 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
3865 @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
3867 #define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74
3870 Package. Uncore C-box 7 perfmon box wide filter 0.
3872 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
3873 @param EAX Lower 32-bits of MSR value.
3874 @param EDX Upper 32-bits of MSR value.
3876 <b>Example usage</b>
3880 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
3881 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
3883 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
3885 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75
3888 Package. Uncore C-box 7 perfmon box wide filter1.
3890 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
3891 @param EAX Lower 32-bits of MSR value.
3892 @param EDX Upper 32-bits of MSR value.
3894 <b>Example usage</b>
3898 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
3899 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
3901 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
3903 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76
3906 Package. Uncore C-box 7 perfmon box wide status.
3908 @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
3909 @param EAX Lower 32-bits of MSR value.
3910 @param EDX Upper 32-bits of MSR value.
3912 <b>Example usage</b>
3916 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
3917 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
3919 @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
3921 #define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77
3924 Package. Uncore C-box 7 perfmon counter 0.
3926 @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
3927 @param EAX Lower 32-bits of MSR value.
3928 @param EDX Upper 32-bits of MSR value.
3930 <b>Example usage</b>
3934 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
3935 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
3937 @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
3939 #define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78
3942 Package. Uncore C-box 7 perfmon counter 1.
3944 @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
3945 @param EAX Lower 32-bits of MSR value.
3946 @param EDX Upper 32-bits of MSR value.
3948 <b>Example usage</b>
3952 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
3953 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
3955 @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
3957 #define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79
3960 Package. Uncore C-box 7 perfmon counter 2.
3962 @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
3963 @param EAX Lower 32-bits of MSR value.
3964 @param EDX Upper 32-bits of MSR value.
3966 <b>Example usage</b>
3970 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
3971 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
3973 @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
3975 #define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A
3978 Package. Uncore C-box 7 perfmon counter 3.
3980 @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
3981 @param EAX Lower 32-bits of MSR value.
3982 @param EDX Upper 32-bits of MSR value.
3984 <b>Example usage</b>
3988 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
3989 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
3991 @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
3993 #define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B
3996 Package. Uncore C-box 8 perfmon local box wide control.
3998 @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
3999 @param EAX Lower 32-bits of MSR value.
4000 @param EDX Upper 32-bits of MSR value.
4002 <b>Example usage</b>
4006 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
4007 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
4009 @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
4011 #define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80
4014 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
4016 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
4017 @param EAX Lower 32-bits of MSR value.
4018 @param EDX Upper 32-bits of MSR value.
4020 <b>Example usage</b>
4024 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
4025 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
4027 @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
4029 #define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81
4032 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
4034 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
4035 @param EAX Lower 32-bits of MSR value.
4036 @param EDX Upper 32-bits of MSR value.
4038 <b>Example usage</b>
4042 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
4043 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
4045 @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
4047 #define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82
4050 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
4052 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
4053 @param EAX Lower 32-bits of MSR value.
4054 @param EDX Upper 32-bits of MSR value.
4056 <b>Example usage</b>
4060 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
4061 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
4063 @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
4065 #define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83
4068 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
4070 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
4071 @param EAX Lower 32-bits of MSR value.
4072 @param EDX Upper 32-bits of MSR value.
4074 <b>Example usage</b>
4078 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
4079 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
4081 @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
4083 #define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84
4086 Package. Uncore C-box 8 perfmon box wide filter0.
4088 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
4089 @param EAX Lower 32-bits of MSR value.
4090 @param EDX Upper 32-bits of MSR value.
4092 <b>Example usage</b>
4096 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
4097 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
4099 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
4101 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85
4104 Package. Uncore C-box 8 perfmon box wide filter1.
4106 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
4107 @param EAX Lower 32-bits of MSR value.
4108 @param EDX Upper 32-bits of MSR value.
4110 <b>Example usage</b>
4114 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
4115 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
4117 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
4119 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86
4122 Package. Uncore C-box 8 perfmon box wide status.
4124 @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
4125 @param EAX Lower 32-bits of MSR value.
4126 @param EDX Upper 32-bits of MSR value.
4128 <b>Example usage</b>
4132 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
4133 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
4135 @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
4137 #define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87
4140 Package. Uncore C-box 8 perfmon counter 0.
4142 @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
4143 @param EAX Lower 32-bits of MSR value.
4144 @param EDX Upper 32-bits of MSR value.
4146 <b>Example usage</b>
4150 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
4151 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
4153 @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
4155 #define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88
4158 Package. Uncore C-box 8 perfmon counter 1.
4160 @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
4161 @param EAX Lower 32-bits of MSR value.
4162 @param EDX Upper 32-bits of MSR value.
4164 <b>Example usage</b>
4168 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
4169 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
4171 @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
4173 #define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89
4176 Package. Uncore C-box 8 perfmon counter 2.
4178 @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
4179 @param EAX Lower 32-bits of MSR value.
4180 @param EDX Upper 32-bits of MSR value.
4182 <b>Example usage</b>
4186 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
4187 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
4189 @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
4191 #define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A
4194 Package. Uncore C-box 8 perfmon counter 3.
4196 @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
4197 @param EAX Lower 32-bits of MSR value.
4198 @param EDX Upper 32-bits of MSR value.
4200 <b>Example usage</b>
4204 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
4205 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
4207 @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
4209 #define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B
4212 Package. Uncore C-box 9 perfmon local box wide control.
4214 @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
4215 @param EAX Lower 32-bits of MSR value.
4216 @param EDX Upper 32-bits of MSR value.
4218 <b>Example usage</b>
4222 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
4223 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
4225 @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
4227 #define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90
4230 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
4232 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
4233 @param EAX Lower 32-bits of MSR value.
4234 @param EDX Upper 32-bits of MSR value.
4236 <b>Example usage</b>
4240 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
4241 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
4243 @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
4245 #define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91
4248 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
4250 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
4251 @param EAX Lower 32-bits of MSR value.
4252 @param EDX Upper 32-bits of MSR value.
4254 <b>Example usage</b>
4258 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
4259 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
4261 @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
4263 #define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92
4266 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
4268 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
4269 @param EAX Lower 32-bits of MSR value.
4270 @param EDX Upper 32-bits of MSR value.
4272 <b>Example usage</b>
4276 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
4277 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
4279 @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
4281 #define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93
4284 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
4286 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
4287 @param EAX Lower 32-bits of MSR value.
4288 @param EDX Upper 32-bits of MSR value.
4290 <b>Example usage</b>
4294 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
4295 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
4297 @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
4299 #define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94
4302 Package. Uncore C-box 9 perfmon box wide filter0.
4304 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
4305 @param EAX Lower 32-bits of MSR value.
4306 @param EDX Upper 32-bits of MSR value.
4308 <b>Example usage</b>
4312 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
4313 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
4315 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
4317 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95
4320 Package. Uncore C-box 9 perfmon box wide filter1.
4322 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
4323 @param EAX Lower 32-bits of MSR value.
4324 @param EDX Upper 32-bits of MSR value.
4326 <b>Example usage</b>
4330 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
4331 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
4333 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
4335 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96
4338 Package. Uncore C-box 9 perfmon box wide status.
4340 @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
4341 @param EAX Lower 32-bits of MSR value.
4342 @param EDX Upper 32-bits of MSR value.
4344 <b>Example usage</b>
4348 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
4349 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
4351 @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
4353 #define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97
4356 Package. Uncore C-box 9 perfmon counter 0.
4358 @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
4359 @param EAX Lower 32-bits of MSR value.
4360 @param EDX Upper 32-bits of MSR value.
4362 <b>Example usage</b>
4366 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
4367 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
4369 @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
4371 #define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98
4374 Package. Uncore C-box 9 perfmon counter 1.
4376 @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
4377 @param EAX Lower 32-bits of MSR value.
4378 @param EDX Upper 32-bits of MSR value.
4380 <b>Example usage</b>
4384 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
4385 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
4387 @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
4389 #define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99
4392 Package. Uncore C-box 9 perfmon counter 2.
4394 @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
4395 @param EAX Lower 32-bits of MSR value.
4396 @param EDX Upper 32-bits of MSR value.
4398 <b>Example usage</b>
4402 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
4403 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
4405 @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
4407 #define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A
4410 Package. Uncore C-box 9 perfmon counter 3.
4412 @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
4413 @param EAX Lower 32-bits of MSR value.
4414 @param EDX Upper 32-bits of MSR value.
4416 <b>Example usage</b>
4420 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
4421 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
4423 @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
4425 #define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B
4428 Package. Uncore C-box 10 perfmon local box wide control.
4430 @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
4431 @param EAX Lower 32-bits of MSR value.
4432 @param EDX Upper 32-bits of MSR value.
4434 <b>Example usage</b>
4438 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
4439 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
4441 @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
4443 #define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0
4446 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
4448 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
4449 @param EAX Lower 32-bits of MSR value.
4450 @param EDX Upper 32-bits of MSR value.
4452 <b>Example usage</b>
4456 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
4457 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
4459 @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
4461 #define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1
4464 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
4466 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
4467 @param EAX Lower 32-bits of MSR value.
4468 @param EDX Upper 32-bits of MSR value.
4470 <b>Example usage</b>
4474 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
4475 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
4477 @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
4479 #define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2
4482 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
4484 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
4485 @param EAX Lower 32-bits of MSR value.
4486 @param EDX Upper 32-bits of MSR value.
4488 <b>Example usage</b>
4492 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
4493 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
4495 @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
4497 #define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3
4500 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
4502 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
4503 @param EAX Lower 32-bits of MSR value.
4504 @param EDX Upper 32-bits of MSR value.
4506 <b>Example usage</b>
4510 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
4511 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
4513 @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
4515 #define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4
4518 Package. Uncore C-box 10 perfmon box wide filter0.
4520 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
4521 @param EAX Lower 32-bits of MSR value.
4522 @param EDX Upper 32-bits of MSR value.
4524 <b>Example usage</b>
4528 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
4529 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
4531 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
4533 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5
4536 Package. Uncore C-box 10 perfmon box wide filter1.
4538 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
4539 @param EAX Lower 32-bits of MSR value.
4540 @param EDX Upper 32-bits of MSR value.
4542 <b>Example usage</b>
4546 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
4547 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
4549 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
4551 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6
4554 Package. Uncore C-box 10 perfmon box wide status.
4556 @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
4557 @param EAX Lower 32-bits of MSR value.
4558 @param EDX Upper 32-bits of MSR value.
4560 <b>Example usage</b>
4564 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
4565 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
4567 @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
4569 #define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7
4572 Package. Uncore C-box 10 perfmon counter 0.
4574 @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
4575 @param EAX Lower 32-bits of MSR value.
4576 @param EDX Upper 32-bits of MSR value.
4578 <b>Example usage</b>
4582 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
4583 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
4585 @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
4587 #define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8
4590 Package. Uncore C-box 10 perfmon counter 1.
4592 @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
4593 @param EAX Lower 32-bits of MSR value.
4594 @param EDX Upper 32-bits of MSR value.
4596 <b>Example usage</b>
4600 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
4601 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
4603 @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
4605 #define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9
4608 Package. Uncore C-box 10 perfmon counter 2.
4610 @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
4611 @param EAX Lower 32-bits of MSR value.
4612 @param EDX Upper 32-bits of MSR value.
4614 <b>Example usage</b>
4618 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
4619 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
4621 @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
4623 #define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA
4626 Package. Uncore C-box 10 perfmon counter 3.
4628 @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
4629 @param EAX Lower 32-bits of MSR value.
4630 @param EDX Upper 32-bits of MSR value.
4632 <b>Example usage</b>
4636 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
4637 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
4639 @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
4641 #define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB
4644 Package. Uncore C-box 11 perfmon local box wide control.
4646 @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
4647 @param EAX Lower 32-bits of MSR value.
4648 @param EDX Upper 32-bits of MSR value.
4650 <b>Example usage</b>
4654 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
4655 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
4657 @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
4659 #define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0
4662 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
4664 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
4665 @param EAX Lower 32-bits of MSR value.
4666 @param EDX Upper 32-bits of MSR value.
4668 <b>Example usage</b>
4672 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
4673 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
4675 @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
4677 #define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1
4680 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
4682 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
4683 @param EAX Lower 32-bits of MSR value.
4684 @param EDX Upper 32-bits of MSR value.
4686 <b>Example usage</b>
4690 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
4691 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
4693 @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
4695 #define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2
4698 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
4700 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
4701 @param EAX Lower 32-bits of MSR value.
4702 @param EDX Upper 32-bits of MSR value.
4704 <b>Example usage</b>
4708 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
4709 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
4711 @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
4713 #define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3
4716 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
4718 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
4719 @param EAX Lower 32-bits of MSR value.
4720 @param EDX Upper 32-bits of MSR value.
4722 <b>Example usage</b>
4726 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
4727 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
4729 @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
4731 #define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4
4734 Package. Uncore C-box 11 perfmon box wide filter0.
4736 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
4737 @param EAX Lower 32-bits of MSR value.
4738 @param EDX Upper 32-bits of MSR value.
4740 <b>Example usage</b>
4744 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
4745 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
4747 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
4749 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5
4752 Package. Uncore C-box 11 perfmon box wide filter1.
4754 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
4755 @param EAX Lower 32-bits of MSR value.
4756 @param EDX Upper 32-bits of MSR value.
4758 <b>Example usage</b>
4762 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
4763 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
4765 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
4767 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6
4770 Package. Uncore C-box 11 perfmon box wide status.
4772 @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
4773 @param EAX Lower 32-bits of MSR value.
4774 @param EDX Upper 32-bits of MSR value.
4776 <b>Example usage</b>
4780 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
4781 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
4783 @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
4785 #define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7
4788 Package. Uncore C-box 11 perfmon counter 0.
4790 @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
4791 @param EAX Lower 32-bits of MSR value.
4792 @param EDX Upper 32-bits of MSR value.
4794 <b>Example usage</b>
4798 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
4799 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
4801 @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
4803 #define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8
4806 Package. Uncore C-box 11 perfmon counter 1.
4808 @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
4809 @param EAX Lower 32-bits of MSR value.
4810 @param EDX Upper 32-bits of MSR value.
4812 <b>Example usage</b>
4816 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
4817 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
4819 @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
4821 #define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9
4824 Package. Uncore C-box 11 perfmon counter 2.
4826 @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
4827 @param EAX Lower 32-bits of MSR value.
4828 @param EDX Upper 32-bits of MSR value.
4830 <b>Example usage</b>
4834 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
4835 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
4837 @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
4839 #define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA
4842 Package. Uncore C-box 11 perfmon counter 3.
4844 @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
4845 @param EAX Lower 32-bits of MSR value.
4846 @param EDX Upper 32-bits of MSR value.
4848 <b>Example usage</b>
4852 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
4853 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
4855 @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
4857 #define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB
4860 Package. Uncore C-box 12 perfmon local box wide control.
4862 @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
4863 @param EAX Lower 32-bits of MSR value.
4864 @param EDX Upper 32-bits of MSR value.
4866 <b>Example usage</b>
4870 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
4871 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
4873 @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
4875 #define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0
4878 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
4880 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
4881 @param EAX Lower 32-bits of MSR value.
4882 @param EDX Upper 32-bits of MSR value.
4884 <b>Example usage</b>
4888 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
4889 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
4891 @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
4893 #define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1
4896 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
4898 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
4899 @param EAX Lower 32-bits of MSR value.
4900 @param EDX Upper 32-bits of MSR value.
4902 <b>Example usage</b>
4906 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
4907 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
4909 @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
4911 #define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2
4914 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
4916 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
4917 @param EAX Lower 32-bits of MSR value.
4918 @param EDX Upper 32-bits of MSR value.
4920 <b>Example usage</b>
4924 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
4925 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
4927 @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
4929 #define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3
4932 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
4934 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
4935 @param EAX Lower 32-bits of MSR value.
4936 @param EDX Upper 32-bits of MSR value.
4938 <b>Example usage</b>
4942 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
4943 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
4945 @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
4947 #define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4
4950 Package. Uncore C-box 12 perfmon box wide filter0.
4952 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
4953 @param EAX Lower 32-bits of MSR value.
4954 @param EDX Upper 32-bits of MSR value.
4956 <b>Example usage</b>
4960 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
4961 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
4963 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
4965 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5
4968 Package. Uncore C-box 12 perfmon box wide filter1.
4970 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
4971 @param EAX Lower 32-bits of MSR value.
4972 @param EDX Upper 32-bits of MSR value.
4974 <b>Example usage</b>
4978 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
4979 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
4981 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
4983 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6
4986 Package. Uncore C-box 12 perfmon box wide status.
4988 @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
4989 @param EAX Lower 32-bits of MSR value.
4990 @param EDX Upper 32-bits of MSR value.
4992 <b>Example usage</b>
4996 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
4997 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
4999 @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
5001 #define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7
5004 Package. Uncore C-box 12 perfmon counter 0.
5006 @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
5007 @param EAX Lower 32-bits of MSR value.
5008 @param EDX Upper 32-bits of MSR value.
5010 <b>Example usage</b>
5014 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
5015 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
5017 @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
5019 #define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8
5022 Package. Uncore C-box 12 perfmon counter 1.
5024 @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
5025 @param EAX Lower 32-bits of MSR value.
5026 @param EDX Upper 32-bits of MSR value.
5028 <b>Example usage</b>
5032 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
5033 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
5035 @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
5037 #define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9
5040 Package. Uncore C-box 12 perfmon counter 2.
5042 @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
5043 @param EAX Lower 32-bits of MSR value.
5044 @param EDX Upper 32-bits of MSR value.
5046 <b>Example usage</b>
5050 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
5051 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
5053 @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
5055 #define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA
5058 Package. Uncore C-box 12 perfmon counter 3.
5060 @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
5061 @param EAX Lower 32-bits of MSR value.
5062 @param EDX Upper 32-bits of MSR value.
5064 <b>Example usage</b>
5068 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
5069 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
5071 @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
5073 #define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB
5076 Package. Uncore C-box 13 perfmon local box wide control.
5078 @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
5079 @param EAX Lower 32-bits of MSR value.
5080 @param EDX Upper 32-bits of MSR value.
5082 <b>Example usage</b>
5086 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
5087 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
5089 @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
5091 #define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0
5094 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
5096 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
5097 @param EAX Lower 32-bits of MSR value.
5098 @param EDX Upper 32-bits of MSR value.
5100 <b>Example usage</b>
5104 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
5105 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
5107 @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
5109 #define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1
5112 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
5114 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
5115 @param EAX Lower 32-bits of MSR value.
5116 @param EDX Upper 32-bits of MSR value.
5118 <b>Example usage</b>
5122 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
5123 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
5125 @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
5127 #define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2
5130 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
5132 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
5133 @param EAX Lower 32-bits of MSR value.
5134 @param EDX Upper 32-bits of MSR value.
5136 <b>Example usage</b>
5140 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
5141 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
5143 @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
5145 #define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3
5148 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
5150 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
5151 @param EAX Lower 32-bits of MSR value.
5152 @param EDX Upper 32-bits of MSR value.
5154 <b>Example usage</b>
5158 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
5159 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
5161 @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
5163 #define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4
5166 Package. Uncore C-box 13 perfmon box wide filter0.
5168 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
5169 @param EAX Lower 32-bits of MSR value.
5170 @param EDX Upper 32-bits of MSR value.
5172 <b>Example usage</b>
5176 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
5177 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
5179 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
5181 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5
5184 Package. Uncore C-box 13 perfmon box wide filter1.
5186 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
5187 @param EAX Lower 32-bits of MSR value.
5188 @param EDX Upper 32-bits of MSR value.
5190 <b>Example usage</b>
5194 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
5195 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
5197 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
5199 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6
5202 Package. Uncore C-box 13 perfmon box wide status.
5204 @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
5205 @param EAX Lower 32-bits of MSR value.
5206 @param EDX Upper 32-bits of MSR value.
5208 <b>Example usage</b>
5212 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
5213 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
5215 @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
5217 #define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7
5220 Package. Uncore C-box 13 perfmon counter 0.
5222 @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
5223 @param EAX Lower 32-bits of MSR value.
5224 @param EDX Upper 32-bits of MSR value.
5226 <b>Example usage</b>
5230 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
5231 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
5233 @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
5235 #define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8
5238 Package. Uncore C-box 13 perfmon counter 1.
5240 @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
5241 @param EAX Lower 32-bits of MSR value.
5242 @param EDX Upper 32-bits of MSR value.
5244 <b>Example usage</b>
5248 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
5249 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
5251 @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
5253 #define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9
5256 Package. Uncore C-box 13 perfmon counter 2.
5258 @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
5259 @param EAX Lower 32-bits of MSR value.
5260 @param EDX Upper 32-bits of MSR value.
5262 <b>Example usage</b>
5266 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
5267 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
5269 @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
5271 #define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA
5274 Package. Uncore C-box 13 perfmon counter 3.
5276 @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
5277 @param EAX Lower 32-bits of MSR value.
5278 @param EDX Upper 32-bits of MSR value.
5280 <b>Example usage</b>
5284 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
5285 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
5287 @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
5289 #define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB
5292 Package. Uncore C-box 14 perfmon local box wide control.
5294 @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
5295 @param EAX Lower 32-bits of MSR value.
5296 @param EDX Upper 32-bits of MSR value.
5298 <b>Example usage</b>
5302 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
5303 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
5305 @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
5307 #define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0
5310 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
5312 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
5313 @param EAX Lower 32-bits of MSR value.
5314 @param EDX Upper 32-bits of MSR value.
5316 <b>Example usage</b>
5320 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
5321 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
5323 @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
5325 #define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1
5328 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
5330 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
5331 @param EAX Lower 32-bits of MSR value.
5332 @param EDX Upper 32-bits of MSR value.
5334 <b>Example usage</b>
5338 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
5339 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
5341 @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
5343 #define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2
5346 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
5348 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
5349 @param EAX Lower 32-bits of MSR value.
5350 @param EDX Upper 32-bits of MSR value.
5352 <b>Example usage</b>
5356 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
5357 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
5359 @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
5361 #define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3
5364 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
5366 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
5367 @param EAX Lower 32-bits of MSR value.
5368 @param EDX Upper 32-bits of MSR value.
5370 <b>Example usage</b>
5374 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
5375 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
5377 @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
5379 #define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4
5382 Package. Uncore C-box 14 perfmon box wide filter0.
5384 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
5385 @param EAX Lower 32-bits of MSR value.
5386 @param EDX Upper 32-bits of MSR value.
5388 <b>Example usage</b>
5392 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
5393 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
5395 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
5397 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5
5400 Package. Uncore C-box 14 perfmon box wide filter1.
5402 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
5403 @param EAX Lower 32-bits of MSR value.
5404 @param EDX Upper 32-bits of MSR value.
5406 <b>Example usage</b>
5410 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
5411 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
5413 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
5415 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6
5418 Package. Uncore C-box 14 perfmon box wide status.
5420 @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
5421 @param EAX Lower 32-bits of MSR value.
5422 @param EDX Upper 32-bits of MSR value.
5424 <b>Example usage</b>
5428 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
5429 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
5431 @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
5433 #define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7
5436 Package. Uncore C-box 14 perfmon counter 0.
5438 @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
5439 @param EAX Lower 32-bits of MSR value.
5440 @param EDX Upper 32-bits of MSR value.
5442 <b>Example usage</b>
5446 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
5447 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
5449 @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
5451 #define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8
5454 Package. Uncore C-box 14 perfmon counter 1.
5456 @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
5457 @param EAX Lower 32-bits of MSR value.
5458 @param EDX Upper 32-bits of MSR value.
5460 <b>Example usage</b>
5464 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
5465 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
5467 @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
5469 #define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9
5472 Package. Uncore C-box 14 perfmon counter 2.
5474 @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
5475 @param EAX Lower 32-bits of MSR value.
5476 @param EDX Upper 32-bits of MSR value.
5478 <b>Example usage</b>
5482 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
5483 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
5485 @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
5487 #define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA
5490 Package. Uncore C-box 14 perfmon counter 3.
5492 @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
5493 @param EAX Lower 32-bits of MSR value.
5494 @param EDX Upper 32-bits of MSR value.
5496 <b>Example usage</b>
5500 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
5501 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
5503 @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
5505 #define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB
5508 Package. Uncore C-box 15 perfmon local box wide control.
5510 @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
5511 @param EAX Lower 32-bits of MSR value.
5512 @param EDX Upper 32-bits of MSR value.
5514 <b>Example usage</b>
5518 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
5519 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
5521 @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
5523 #define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0
5526 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
5528 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
5529 @param EAX Lower 32-bits of MSR value.
5530 @param EDX Upper 32-bits of MSR value.
5532 <b>Example usage</b>
5536 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
5537 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
5539 @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
5541 #define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1
5544 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
5546 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
5547 @param EAX Lower 32-bits of MSR value.
5548 @param EDX Upper 32-bits of MSR value.
5550 <b>Example usage</b>
5554 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
5555 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
5557 @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
5559 #define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2
5562 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
5564 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
5565 @param EAX Lower 32-bits of MSR value.
5566 @param EDX Upper 32-bits of MSR value.
5568 <b>Example usage</b>
5572 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
5573 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
5575 @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
5577 #define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3
5580 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
5582 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
5583 @param EAX Lower 32-bits of MSR value.
5584 @param EDX Upper 32-bits of MSR value.
5586 <b>Example usage</b>
5590 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
5591 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
5593 @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
5595 #define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4
5598 Package. Uncore C-box 15 perfmon box wide filter0.
5600 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
5601 @param EAX Lower 32-bits of MSR value.
5602 @param EDX Upper 32-bits of MSR value.
5604 <b>Example usage</b>
5608 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
5609 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
5611 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
5613 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5
5616 Package. Uncore C-box 15 perfmon box wide filter1.
5618 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
5619 @param EAX Lower 32-bits of MSR value.
5620 @param EDX Upper 32-bits of MSR value.
5622 <b>Example usage</b>
5626 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
5627 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
5629 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
5631 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6
5634 Package. Uncore C-box 15 perfmon box wide status.
5636 @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
5637 @param EAX Lower 32-bits of MSR value.
5638 @param EDX Upper 32-bits of MSR value.
5640 <b>Example usage</b>
5644 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
5645 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
5647 @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
5649 #define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7
5652 Package. Uncore C-box 15 perfmon counter 0.
5654 @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
5655 @param EAX Lower 32-bits of MSR value.
5656 @param EDX Upper 32-bits of MSR value.
5658 <b>Example usage</b>
5662 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
5663 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
5665 @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
5667 #define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8
5670 Package. Uncore C-box 15 perfmon counter 1.
5672 @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
5673 @param EAX Lower 32-bits of MSR value.
5674 @param EDX Upper 32-bits of MSR value.
5676 <b>Example usage</b>
5680 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
5681 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
5683 @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
5685 #define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9
5688 Package. Uncore C-box 15 perfmon counter 2.
5690 @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
5691 @param EAX Lower 32-bits of MSR value.
5692 @param EDX Upper 32-bits of MSR value.
5694 <b>Example usage</b>
5698 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
5699 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
5701 @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
5703 #define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA
5706 Package. Uncore C-box 15 perfmon counter 3.
5708 @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
5709 @param EAX Lower 32-bits of MSR value.
5710 @param EDX Upper 32-bits of MSR value.
5712 <b>Example usage</b>
5716 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
5717 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
5719 @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
5721 #define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB
5724 Package. Uncore C-box 16 perfmon for box-wide control.
5726 @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
5727 @param EAX Lower 32-bits of MSR value.
5728 @param EDX Upper 32-bits of MSR value.
5730 <b>Example usage</b>
5734 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
5735 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
5737 @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
5739 #define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00
5742 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
5744 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
5745 @param EAX Lower 32-bits of MSR value.
5746 @param EDX Upper 32-bits of MSR value.
5748 <b>Example usage</b>
5752 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
5753 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
5755 @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
5757 #define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01
5760 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
5762 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
5763 @param EAX Lower 32-bits of MSR value.
5764 @param EDX Upper 32-bits of MSR value.
5766 <b>Example usage</b>
5770 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
5771 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
5773 @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
5775 #define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02
5778 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
5780 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
5781 @param EAX Lower 32-bits of MSR value.
5782 @param EDX Upper 32-bits of MSR value.
5784 <b>Example usage</b>
5788 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
5789 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
5791 @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
5793 #define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03
5796 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
5798 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
5799 @param EAX Lower 32-bits of MSR value.
5800 @param EDX Upper 32-bits of MSR value.
5802 <b>Example usage</b>
5806 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
5807 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
5809 @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
5811 #define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04
5814 Package. Uncore C-box 16 perfmon box wide filter 0.
5816 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
5817 @param EAX Lower 32-bits of MSR value.
5818 @param EDX Upper 32-bits of MSR value.
5820 <b>Example usage</b>
5824 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
5825 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
5827 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
5829 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05
5832 Package. Uncore C-box 16 perfmon box wide filter 1.
5834 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
5835 @param EAX Lower 32-bits of MSR value.
5836 @param EDX Upper 32-bits of MSR value.
5838 <b>Example usage</b>
5842 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
5843 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
5845 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
5847 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06
5850 Package. Uncore C-box 16 perfmon box wide status.
5852 @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
5853 @param EAX Lower 32-bits of MSR value.
5854 @param EDX Upper 32-bits of MSR value.
5856 <b>Example usage</b>
5860 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
5861 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
5863 @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
5865 #define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07
5868 Package. Uncore C-box 16 perfmon counter 0.
5870 @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
5871 @param EAX Lower 32-bits of MSR value.
5872 @param EDX Upper 32-bits of MSR value.
5874 <b>Example usage</b>
5878 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
5879 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
5881 @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
5883 #define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08
5886 Package. Uncore C-box 16 perfmon counter 1.
5888 @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
5889 @param EAX Lower 32-bits of MSR value.
5890 @param EDX Upper 32-bits of MSR value.
5892 <b>Example usage</b>
5896 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
5897 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
5899 @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
5901 #define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09
5904 Package. Uncore C-box 16 perfmon counter 2.
5906 @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
5907 @param EAX Lower 32-bits of MSR value.
5908 @param EDX Upper 32-bits of MSR value.
5910 <b>Example usage</b>
5914 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
5915 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
5917 @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
5919 #define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A
5922 Package. Uncore C-box 16 perfmon counter 3.
5924 @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
5925 @param EAX Lower 32-bits of MSR value.
5926 @param EDX Upper 32-bits of MSR value.
5928 <b>Example usage</b>
5932 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
5933 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
5935 @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
5937 #define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B
5940 Package. Uncore C-box 17 perfmon for box-wide control.
5942 @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
5943 @param EAX Lower 32-bits of MSR value.
5944 @param EDX Upper 32-bits of MSR value.
5946 <b>Example usage</b>
5950 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
5951 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
5953 @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
5955 #define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10
5958 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
5960 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
5961 @param EAX Lower 32-bits of MSR value.
5962 @param EDX Upper 32-bits of MSR value.
5964 <b>Example usage</b>
5968 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
5969 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
5971 @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
5973 #define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11
5976 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
5978 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
5979 @param EAX Lower 32-bits of MSR value.
5980 @param EDX Upper 32-bits of MSR value.
5982 <b>Example usage</b>
5986 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
5987 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
5989 @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
5991 #define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12
5994 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
5996 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
5997 @param EAX Lower 32-bits of MSR value.
5998 @param EDX Upper 32-bits of MSR value.
6000 <b>Example usage</b>
6004 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
6005 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
6007 @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
6009 #define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13
6012 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
6014 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
6015 @param EAX Lower 32-bits of MSR value.
6016 @param EDX Upper 32-bits of MSR value.
6018 <b>Example usage</b>
6022 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
6023 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
6025 @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
6027 #define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14
6030 Package. Uncore C-box 17 perfmon box wide filter 0.
6032 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
6033 @param EAX Lower 32-bits of MSR value.
6034 @param EDX Upper 32-bits of MSR value.
6036 <b>Example usage</b>
6040 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
6041 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
6043 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
6045 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15
6048 Package. Uncore C-box 17 perfmon box wide filter1.
6050 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
6051 @param EAX Lower 32-bits of MSR value.
6052 @param EDX Upper 32-bits of MSR value.
6054 <b>Example usage</b>
6058 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
6059 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
6061 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
6063 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16
6066 Package. Uncore C-box 17 perfmon box wide status.
6068 @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
6069 @param EAX Lower 32-bits of MSR value.
6070 @param EDX Upper 32-bits of MSR value.
6072 <b>Example usage</b>
6076 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
6077 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
6079 @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
6081 #define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17
6084 Package. Uncore C-box 17 perfmon counter n.
6086 @param ECX MSR_HASWELL_E_C17_PMON_CTRn
6087 @param EAX Lower 32-bits of MSR value.
6088 @param EDX Upper 32-bits of MSR value.
6090 <b>Example usage</b>
6094 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
6095 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
6097 @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
6098 MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
6099 MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
6100 MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
6103 #define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18
6104 #define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19
6105 #define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A
6106 #define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B