2 MSR Definitions for Intel processors based on the Nehalem microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __NEHALEM_MSR_H__
19 #define __NEHALEM_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel processors based on the Nehalem microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x1A || \
36 DisplayModel == 0x1E || \
37 DisplayModel == 0x1F || \
38 DisplayModel == 0x2E \
43 Package. Model Specific Platform ID (R).
45 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)
46 @param EAX Lower 32-bits of MSR value.
47 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
48 @param EDX Upper 32-bits of MSR value.
49 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
53 MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;
55 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
57 @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
59 #define MSR_NEHALEM_PLATFORM_ID 0x00000017
62 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID
66 /// Individual bit fields
69 UINT32 Reserved1
: 32;
70 UINT32 Reserved2
: 18;
72 /// [Bits 52:50] See Table 2-2.
74 UINT32 PlatformId
: 3;
75 UINT32 Reserved3
: 11;
78 /// All bit fields as a 64-bit value
81 } MSR_NEHALEM_PLATFORM_ID_REGISTER
;
84 Thread. SMI Counter (R/O).
86 @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)
87 @param EAX Lower 32-bits of MSR value.
88 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
89 @param EDX Upper 32-bits of MSR value.
90 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
94 MSR_NEHALEM_SMI_COUNT_REGISTER Msr;
96 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
98 @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
100 #define MSR_NEHALEM_SMI_COUNT 0x00000034
103 MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT
107 /// Individual bit fields
111 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
114 UINT32 SMICount
: 32;
115 UINT32 Reserved
: 32;
118 /// All bit fields as a 32-bit value
122 /// All bit fields as a 64-bit value
125 } MSR_NEHALEM_SMI_COUNT_REGISTER
;
128 Package. see http://biosbits.org.
130 @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
131 @param EAX Lower 32-bits of MSR value.
132 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
133 @param EDX Upper 32-bits of MSR value.
134 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
138 MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;
140 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
141 AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
143 @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
145 #define MSR_NEHALEM_PLATFORM_INFO 0x000000CE
148 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO
152 /// Individual bit fields
155 UINT32 Reserved1
: 8;
157 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
158 /// of the frequency that invariant TSC runs at. The invariant TSC
159 /// frequency can be computed by multiplying this ratio by 133.33 MHz.
161 UINT32 MaximumNonTurboRatio
: 8;
162 UINT32 Reserved2
: 12;
164 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
165 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
166 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
167 /// Turbo mode is disabled.
169 UINT32 RatioLimit
: 1;
171 /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)
172 /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are
173 /// programmable, and when set to 0, indicates TDC and TDP Limits for
174 /// Turbo mode are not programmable.
176 UINT32 TDC_TDPLimit
: 1;
177 UINT32 Reserved3
: 2;
178 UINT32 Reserved4
: 8;
180 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
181 /// minimum ratio (maximum efficiency) that the processor can operates, in
182 /// units of 133.33MHz.
184 UINT32 MaximumEfficiencyRatio
: 8;
185 UINT32 Reserved5
: 16;
188 /// All bit fields as a 64-bit value
191 } MSR_NEHALEM_PLATFORM_INFO_REGISTER
;
194 Core. C-State Configuration Control (R/W) Note: C-state values are
195 processor specific C-state code names, unrelated to MWAIT extension C-state
196 parameters or ACPI CStates. See http://biosbits.org.
198 @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
199 @param EAX Lower 32-bits of MSR value.
200 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
201 @param EDX Upper 32-bits of MSR value.
202 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
206 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
208 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
209 AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
211 @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
213 #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2
216 MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL
220 /// Individual bit fields
224 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
225 /// processor-specific C-state code name (consuming the least power). for
226 /// the package. The default is set as factory-configured package C-state
227 /// limit. The following C-state code name encodings are supported: 000b:
228 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
229 /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package
230 /// C-state limit. Note: This field cannot be used to limit package
234 UINT32 Reserved1
: 7;
236 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
237 /// IO_read instructions sent to IO register specified by
238 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
241 UINT32 Reserved2
: 4;
243 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
244 /// until next reset.
247 UINT32 Reserved3
: 8;
249 /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores
250 /// in a deep C-State will wake only when the event message is destined
251 /// for that core. When 0, all processor cores in a deep C-State will wake
252 /// for an event message.
254 UINT32 InterruptFiltering
: 1;
256 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
257 /// will conditionally demote C6/C7 requests to C3 based on uncore
258 /// auto-demote information.
260 UINT32 C3AutoDemotion
: 1;
262 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
263 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
264 /// auto-demote information.
266 UINT32 C1AutoDemotion
: 1;
268 /// [Bit 27] Enable C3 Undemotion (R/W).
270 UINT32 C3Undemotion
: 1;
272 /// [Bit 28] Enable C1 Undemotion (R/W).
274 UINT32 C1Undemotion
: 1;
276 /// [Bit 29] Package C State Demotion Enable (R/W).
278 UINT32 CStateDemotion
: 1;
280 /// [Bit 30] Package C State UnDemotion Enable (R/W).
282 UINT32 CStateUndemotion
: 1;
283 UINT32 Reserved4
: 1;
284 UINT32 Reserved5
: 32;
287 /// All bit fields as a 32-bit value
291 /// All bit fields as a 64-bit value
294 } MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
;
297 Core. Power Management IO Redirection in C-state (R/W) See
300 @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
301 @param EAX Lower 32-bits of MSR value.
302 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
303 @param EDX Upper 32-bits of MSR value.
304 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
308 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;
310 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
311 AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
313 @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
315 #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4
318 MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE
322 /// Individual bit fields
326 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
327 /// visible to software for IO redirection. If IO MWAIT Redirection is
328 /// enabled, reads to this address will be consumed by the power
329 /// management logic and decoded to MWAIT instructions. When IO port
330 /// address redirection is enabled, this is the IO port address reported
331 /// to the OS/software.
333 UINT32 Lvl2Base
: 16;
335 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
336 /// maximum C-State code name to be included when IO read to MWAIT
337 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
338 /// is the max C-State to include 001b - C6 is the max C-State to include
339 /// 010b - C7 is the max C-State to include.
341 UINT32 CStateRange
: 3;
342 UINT32 Reserved1
: 13;
343 UINT32 Reserved2
: 32;
346 /// All bit fields as a 32-bit value
350 /// All bit fields as a 64-bit value
353 } MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER
;
356 Enable Misc. Processor Features (R/W) Allows a variety of processor
357 functions to be enabled and disabled.
359 @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
360 @param EAX Lower 32-bits of MSR value.
361 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
362 @param EDX Upper 32-bits of MSR value.
363 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
367 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;
369 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
370 AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
372 @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
374 #define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0
377 MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE
381 /// Individual bit fields
385 /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
387 UINT32 FastStrings
: 1;
388 UINT32 Reserved1
: 2;
390 /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
391 /// Table 2-2. Default value is 1.
393 UINT32 AutomaticThermalControlCircuit
: 1;
394 UINT32 Reserved2
: 3;
396 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
398 UINT32 PerformanceMonitoring
: 1;
399 UINT32 Reserved3
: 3;
401 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
405 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
409 UINT32 Reserved4
: 3;
411 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
415 UINT32 Reserved5
: 1;
417 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.
420 UINT32 Reserved6
: 3;
422 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
424 UINT32 LimitCpuidMaxval
: 1;
426 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
428 UINT32 xTPR_Message_Disable
: 1;
429 UINT32 Reserved7
: 8;
430 UINT32 Reserved8
: 2;
432 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
435 UINT32 Reserved9
: 3;
437 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
438 /// that support Intel Turbo Boost Technology, the turbo mode feature is
439 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
440 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
441 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
442 /// the power-on default value is used by BIOS to detect hardware support
443 /// of turbo mode. If power-on default value is 1, turbo mode is available
444 /// in the processor. If power-on default value is 0, turbo mode is not
447 UINT32 TurboModeDisable
: 1;
448 UINT32 Reserved10
: 25;
451 /// All bit fields as a 64-bit value
454 } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER
;
459 @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
460 @param EAX Lower 32-bits of MSR value.
461 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
462 @param EDX Upper 32-bits of MSR value.
463 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
467 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;
469 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
470 AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
472 @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
474 #define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2
477 MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET
481 /// Individual bit fields
484 UINT32 Reserved1
: 16;
486 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
487 /// PROCHOT# will be asserted. The value is degree C.
489 UINT32 TemperatureTarget
: 8;
490 UINT32 Reserved2
: 8;
491 UINT32 Reserved3
: 32;
494 /// All bit fields as a 32-bit value
498 /// All bit fields as a 64-bit value
501 } MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER
;
504 Miscellaneous Feature Control (R/W).
506 @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
507 @param EAX Lower 32-bits of MSR value.
508 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
509 @param EDX Upper 32-bits of MSR value.
510 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
514 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;
516 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
517 AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
519 @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
521 #define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4
524 MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL
528 /// Individual bit fields
532 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
533 /// L2 hardware prefetcher, which fetches additional lines of code or data
534 /// into the L2 cache.
536 UINT32 L2HardwarePrefetcherDisable
: 1;
538 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
539 /// disables the adjacent cache line prefetcher, which fetches the cache
540 /// line that comprises a cache line pair (128 bytes).
542 UINT32 L2AdjacentCacheLinePrefetcherDisable
: 1;
544 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
545 /// the L1 data cache prefetcher, which fetches the next cache line into
548 UINT32 DCUHardwarePrefetcherDisable
: 1;
550 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
551 /// data cache IP prefetcher, which uses sequential load history (based on
552 /// instruction Pointer of previous loads) to determine whether to
553 /// prefetch additional lines.
555 UINT32 DCUIPPrefetcherDisable
: 1;
556 UINT32 Reserved1
: 28;
557 UINT32 Reserved2
: 32;
560 /// All bit fields as a 32-bit value
564 /// All bit fields as a 64-bit value
567 } MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER
;
570 Thread. Offcore Response Event Select Register (R/W).
572 @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
573 @param EAX Lower 32-bits of MSR value.
574 @param EDX Upper 32-bits of MSR value.
580 Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
581 AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
583 @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
585 #define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6
588 See http://biosbits.org.
590 @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
591 @param EAX Lower 32-bits of MSR value.
592 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
593 @param EDX Upper 32-bits of MSR value.
594 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
598 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;
600 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
601 AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
603 @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
605 #define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA
608 MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT
612 /// Individual bit fields
616 /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,
617 /// enables hardware coordination of Enhanced Intel Speedstep Technology
618 /// request from processor cores; When 1, disables hardware coordination
619 /// of Enhanced Intel Speedstep Technology requests.
621 UINT32 EISTHardwareCoordinationDisable
: 1;
623 /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes
624 /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with
625 /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by
626 /// CPUID.(EAX=06h):ECX[3].
628 UINT32 EnergyPerformanceBiasEnable
: 1;
629 UINT32 Reserved1
: 30;
630 UINT32 Reserved2
: 32;
633 /// All bit fields as a 32-bit value
637 /// All bit fields as a 64-bit value
640 } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
;
643 See http://biosbits.org.
645 @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
646 @param EAX Lower 32-bits of MSR value.
647 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
648 @param EDX Upper 32-bits of MSR value.
649 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
653 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;
655 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
656 AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
658 @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.
660 #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC
663 MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT
667 /// Individual bit fields
671 /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt
674 UINT32 TDPLimit
: 15;
676 /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0
677 /// indicates override is not active, and a value = 1 indicates active.
679 UINT32 TDPLimitOverrideEnable
: 1;
681 /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp
684 UINT32 TDCLimit
: 15;
686 /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0
687 /// indicates override is not active, and a value = 1 indicates active.
689 UINT32 TDCLimitOverrideEnable
: 1;
690 UINT32 Reserved
: 32;
693 /// All bit fields as a 32-bit value
697 /// All bit fields as a 64-bit value
700 } MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
;
703 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
704 RW if MSR_PLATFORM_INFO.[28] = 1.
706 @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
707 @param EAX Lower 32-bits of MSR value.
708 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
709 @param EDX Upper 32-bits of MSR value.
710 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
714 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;
716 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
718 @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
720 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD
723 MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT
727 /// Individual bit fields
731 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
732 /// limit of 1 core active.
734 UINT32 Maximum1C
: 8;
736 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
737 /// limit of 2 core active.
739 UINT32 Maximum2C
: 8;
741 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
742 /// limit of 3 core active.
744 UINT32 Maximum3C
: 8;
746 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
747 /// limit of 4 core active.
749 UINT32 Maximum4C
: 8;
750 UINT32 Reserved
: 32;
753 /// All bit fields as a 32-bit value
757 /// All bit fields as a 64-bit value
760 } MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER
;
763 Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
764 "Filtering of Last Branch Records.".
766 @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
767 @param EAX Lower 32-bits of MSR value.
768 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
769 @param EDX Upper 32-bits of MSR value.
770 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
774 MSR_NEHALEM_LBR_SELECT_REGISTER Msr;
776 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
777 AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
779 @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
781 #define MSR_NEHALEM_LBR_SELECT 0x000001C8
784 MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT
788 /// Individual bit fields
792 /// [Bit 0] CPL_EQ_0.
796 /// [Bit 1] CPL_NEQ_0.
798 UINT32 CPL_NEQ_0
: 1;
804 /// [Bit 3] NEAR_REL_CALL.
806 UINT32 NEAR_REL_CALL
: 1;
808 /// [Bit 4] NEAR_IND_CALL.
810 UINT32 NEAR_IND_CALL
: 1;
812 /// [Bit 5] NEAR_RET.
816 /// [Bit 6] NEAR_IND_JMP.
818 UINT32 NEAR_IND_JMP
: 1;
820 /// [Bit 7] NEAR_REL_JMP.
822 UINT32 NEAR_REL_JMP
: 1;
824 /// [Bit 8] FAR_BRANCH.
826 UINT32 FAR_BRANCH
: 1;
827 UINT32 Reserved1
: 23;
828 UINT32 Reserved2
: 32;
831 /// All bit fields as a 32-bit value
835 /// All bit fields as a 64-bit value
838 } MSR_NEHALEM_LBR_SELECT_REGISTER
;
841 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
842 that points to the MSR containing the most recent branch record. See
843 MSR_LASTBRANCH_0_FROM_IP (at 680H).
845 @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
846 @param EAX Lower 32-bits of MSR value.
847 @param EDX Upper 32-bits of MSR value.
853 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
854 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
856 @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
858 #define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9
861 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
862 last branch instruction that the processor executed prior to the last
863 exception that was generated or the last interrupt that was handled.
865 @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
866 @param EAX Lower 32-bits of MSR value.
867 @param EDX Upper 32-bits of MSR value.
873 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
875 @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
877 #define MSR_NEHALEM_LER_FROM_LIP 0x000001DD
880 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
881 to the target of the last branch instruction that the processor executed
882 prior to the last exception that was generated or the last interrupt that
885 @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)
886 @param EAX Lower 32-bits of MSR value.
887 @param EDX Upper 32-bits of MSR value.
893 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
895 @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
897 #define MSR_NEHALEM_LER_TO_LIP 0x000001DE
900 Core. Power Control Register. See http://biosbits.org.
902 @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)
903 @param EAX Lower 32-bits of MSR value.
904 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
905 @param EDX Upper 32-bits of MSR value.
906 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
910 MSR_NEHALEM_POWER_CTL_REGISTER Msr;
912 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
913 AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
915 @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.
917 #define MSR_NEHALEM_POWER_CTL 0x000001FC
920 MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL
924 /// Individual bit fields
927 UINT32 Reserved1
: 1;
929 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the
930 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
931 /// operating point when all execution cores enter MWAIT (C1).
933 UINT32 C1EEnable
: 1;
934 UINT32 Reserved2
: 30;
935 UINT32 Reserved3
: 32;
938 /// All bit fields as a 32-bit value
942 /// All bit fields as a 64-bit value
945 } MSR_NEHALEM_POWER_CTL_REGISTER
;
950 @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)
951 @param EAX Lower 32-bits of MSR value.
952 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
953 @param EDX Upper 32-bits of MSR value.
954 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
958 MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;
960 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);
962 @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
964 #define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E
967 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS
971 /// Individual bit fields
974 UINT32 Reserved1
: 32;
975 UINT32 Reserved2
: 29;
977 /// [Bit 61] UNC_Ovf Uncore overflowed if 1.
979 UINT32 Ovf_Uncore
: 1;
980 UINT32 Reserved3
: 2;
983 /// All bit fields as a 64-bit value
986 } MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER
;
991 @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
992 @param EAX Lower 32-bits of MSR value.
993 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
994 @param EDX Upper 32-bits of MSR value.
995 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
999 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1001 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
1002 AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1004 @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
1006 #define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390
1009 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL
1013 /// Individual bit fields
1016 UINT32 Reserved1
: 32;
1017 UINT32 Reserved2
: 29;
1019 /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.
1021 UINT32 Ovf_Uncore
: 1;
1022 UINT32 Reserved3
: 2;
1025 /// All bit fields as a 64-bit value
1028 } MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1031 Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
1033 @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
1034 @param EAX Lower 32-bits of MSR value.
1035 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1036 @param EDX Upper 32-bits of MSR value.
1037 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1039 <b>Example usage</b>
1041 MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;
1043 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
1044 AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
1046 @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1048 #define MSR_NEHALEM_PEBS_ENABLE 0x000003F1
1051 MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE
1055 /// Individual bit fields
1059 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1061 UINT32 PEBS_EN_PMC0
: 1;
1063 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1065 UINT32 PEBS_EN_PMC1
: 1;
1067 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1069 UINT32 PEBS_EN_PMC2
: 1;
1071 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1073 UINT32 PEBS_EN_PMC3
: 1;
1074 UINT32 Reserved1
: 28;
1076 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1078 UINT32 LL_EN_PMC0
: 1;
1080 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1082 UINT32 LL_EN_PMC1
: 1;
1084 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1086 UINT32 LL_EN_PMC2
: 1;
1088 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1090 UINT32 LL_EN_PMC3
: 1;
1091 UINT32 Reserved2
: 28;
1094 /// All bit fields as a 64-bit value
1097 } MSR_NEHALEM_PEBS_ENABLE_REGISTER
;
1100 Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
1103 @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
1104 @param EAX Lower 32-bits of MSR value.
1105 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1106 @param EDX Upper 32-bits of MSR value.
1107 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1109 <b>Example usage</b>
1111 MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;
1113 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
1114 AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
1116 @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1118 #define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6
1121 MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT
1125 /// Individual bit fields
1129 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1130 /// that will be counted. (R/W).
1132 UINT32 MinimumThreshold
: 16;
1133 UINT32 Reserved1
: 16;
1134 UINT32 Reserved2
: 32;
1137 /// All bit fields as a 32-bit value
1141 /// All bit fields as a 64-bit value
1144 } MSR_NEHALEM_PEBS_LD_LAT_REGISTER
;
1147 Package. Note: C-state values are processor specific C-state code names,
1148 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1149 Residency Counter. (R/O) Value since last reset that this package is in
1150 processor-specific C3 states. Count at the same frequency as the TSC.
1152 @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)
1153 @param EAX Lower 32-bits of MSR value.
1154 @param EDX Upper 32-bits of MSR value.
1156 <b>Example usage</b>
1160 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
1161 AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);
1163 @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1165 #define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8
1168 Package. Note: C-state values are processor specific C-state code names,
1169 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1170 Residency Counter. (R/O) Value since last reset that this package is in
1171 processor-specific C6 states. Count at the same frequency as the TSC.
1173 @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)
1174 @param EAX Lower 32-bits of MSR value.
1175 @param EDX Upper 32-bits of MSR value.
1177 <b>Example usage</b>
1181 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
1182 AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);
1184 @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1186 #define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9
1189 Package. Note: C-state values are processor specific C-state code names,
1190 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1191 Residency Counter. (R/O) Value since last reset that this package is in
1192 processor-specific C7 states. Count at the same frequency as the TSC.
1194 @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)
1195 @param EAX Lower 32-bits of MSR value.
1196 @param EDX Upper 32-bits of MSR value.
1198 <b>Example usage</b>
1202 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
1203 AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);
1205 @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1207 #define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA
1210 Core. Note: C-state values are processor specific C-state code names,
1211 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1212 Residency Counter. (R/O) Value since last reset that this core is in
1213 processor-specific C3 states. Count at the same frequency as the TSC.
1215 @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)
1216 @param EAX Lower 32-bits of MSR value.
1217 @param EDX Upper 32-bits of MSR value.
1219 <b>Example usage</b>
1223 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
1224 AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);
1226 @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1228 #define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC
1231 Core. Note: C-state values are processor specific C-state code names,
1232 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1233 Residency Counter. (R/O) Value since last reset that this core is in
1234 processor-specific C6 states. Count at the same frequency as the TSC.
1236 @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)
1237 @param EAX Lower 32-bits of MSR value.
1238 @param EDX Upper 32-bits of MSR value.
1240 <b>Example usage</b>
1244 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
1245 AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);
1247 @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1249 #define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD
1252 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1253 branch record registers on the last branch record stack. The From_IP part of
1254 the stack contains pointers to the source instruction. See also: - Last
1255 Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in
1258 @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP
1259 @param EAX Lower 32-bits of MSR value.
1260 @param EDX Upper 32-bits of MSR value.
1262 <b>Example usage</b>
1266 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
1267 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);
1269 @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1270 MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1271 MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1272 MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1273 MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1274 MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1275 MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1276 MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1277 MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1278 MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1279 MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1280 MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1281 MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1282 MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1283 MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1284 MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1287 #define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680
1288 #define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681
1289 #define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682
1290 #define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683
1291 #define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684
1292 #define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685
1293 #define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686
1294 #define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687
1295 #define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688
1296 #define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689
1297 #define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A
1298 #define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B
1299 #define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C
1300 #define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D
1301 #define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E
1302 #define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F
1306 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1307 record registers on the last branch record stack. This part of the stack
1308 contains pointers to the destination instruction.
1310 @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP
1311 @param EAX Lower 32-bits of MSR value.
1312 @param EDX Upper 32-bits of MSR value.
1314 <b>Example usage</b>
1318 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
1319 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);
1321 @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1322 MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1323 MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1324 MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1325 MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1326 MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1327 MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1328 MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1329 MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1330 MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1331 MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1332 MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1333 MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1334 MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1335 MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1336 MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1339 #define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0
1340 #define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1
1341 #define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2
1342 #define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3
1343 #define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4
1344 #define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5
1345 #define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6
1346 #define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7
1347 #define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8
1348 #define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9
1349 #define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA
1350 #define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB
1351 #define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC
1352 #define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD
1353 #define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE
1354 #define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF
1360 @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)
1361 @param EAX Lower 32-bits of MSR value.
1362 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1363 @param EDX Upper 32-bits of MSR value.
1364 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1366 <b>Example usage</b>
1368 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;
1370 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
1371 AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);
1373 @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.
1375 #define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301
1378 MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF
1382 /// Individual bit fields
1386 /// [Bit 0] From M to S (R/W).
1388 UINT32 FromMtoS
: 1;
1390 /// [Bit 1] From E to S (R/W).
1392 UINT32 FromEtoS
: 1;
1394 /// [Bit 2] From S to S (R/W).
1396 UINT32 FromStoS
: 1;
1398 /// [Bit 3] From F to S (R/W).
1400 UINT32 FromFtoS
: 1;
1402 /// [Bit 4] From M to I (R/W).
1404 UINT32 FromMtoI
: 1;
1406 /// [Bit 5] From E to I (R/W).
1408 UINT32 FromEtoI
: 1;
1410 /// [Bit 6] From S to I (R/W).
1412 UINT32 FromStoI
: 1;
1414 /// [Bit 7] From F to I (R/W).
1416 UINT32 FromFtoI
: 1;
1417 UINT32 Reserved1
: 24;
1418 UINT32 Reserved2
: 32;
1421 /// All bit fields as a 32-bit value
1425 /// All bit fields as a 64-bit value
1428 } MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
;
1431 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1434 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
1435 @param EAX Lower 32-bits of MSR value.
1436 @param EDX Upper 32-bits of MSR value.
1438 <b>Example usage</b>
1442 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
1443 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);
1445 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.
1447 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391
1450 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1453 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
1454 @param EAX Lower 32-bits of MSR value.
1455 @param EDX Upper 32-bits of MSR value.
1457 <b>Example usage</b>
1461 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
1462 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);
1464 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.
1466 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392
1469 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1472 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
1473 @param EAX Lower 32-bits of MSR value.
1474 @param EDX Upper 32-bits of MSR value.
1476 <b>Example usage</b>
1480 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
1481 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);
1483 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.
1485 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393
1488 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1491 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
1492 @param EAX Lower 32-bits of MSR value.
1493 @param EDX Upper 32-bits of MSR value.
1495 <b>Example usage</b>
1499 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
1500 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);
1502 @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.
1504 #define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394
1507 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1510 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
1511 @param EAX Lower 32-bits of MSR value.
1512 @param EDX Upper 32-bits of MSR value.
1514 <b>Example usage</b>
1518 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
1519 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);
1521 @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.
1523 #define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395
1526 Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".
1528 @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
1529 @param EAX Lower 32-bits of MSR value.
1530 @param EDX Upper 32-bits of MSR value.
1532 <b>Example usage</b>
1536 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
1537 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);
1539 @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.
1541 #define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396
1544 Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
1547 @param ECX MSR_NEHALEM_UNCORE_PMCi
1548 @param EAX Lower 32-bits of MSR value.
1549 @param EDX Upper 32-bits of MSR value.
1551 <b>Example usage</b>
1555 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
1556 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);
1558 @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.
1559 MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.
1560 MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.
1561 MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.
1562 MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.
1563 MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.
1564 MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.
1565 MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.
1568 #define MSR_NEHALEM_UNCORE_PMC0 0x000003B0
1569 #define MSR_NEHALEM_UNCORE_PMC1 0x000003B1
1570 #define MSR_NEHALEM_UNCORE_PMC2 0x000003B2
1571 #define MSR_NEHALEM_UNCORE_PMC3 0x000003B3
1572 #define MSR_NEHALEM_UNCORE_PMC4 0x000003B4
1573 #define MSR_NEHALEM_UNCORE_PMC5 0x000003B5
1574 #define MSR_NEHALEM_UNCORE_PMC6 0x000003B6
1575 #define MSR_NEHALEM_UNCORE_PMC7 0x000003B7
1579 Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
1582 @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi
1583 @param EAX Lower 32-bits of MSR value.
1584 @param EDX Upper 32-bits of MSR value.
1586 <b>Example usage</b>
1590 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
1591 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);
1593 @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.
1594 MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.
1595 MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.
1596 MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.
1597 MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.
1598 MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.
1599 MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.
1600 MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.
1603 #define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0
1604 #define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1
1605 #define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2
1606 #define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3
1607 #define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4
1608 #define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5
1609 #define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6
1610 #define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7
1614 Package. Uncore W-box perfmon fixed counter.
1616 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)
1617 @param EAX Lower 32-bits of MSR value.
1618 @param EDX Upper 32-bits of MSR value.
1620 <b>Example usage</b>
1624 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
1625 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);
1627 @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.
1629 #define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394
1632 Package. Uncore U-box perfmon fixed counter control MSR.
1634 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)
1635 @param EAX Lower 32-bits of MSR value.
1636 @param EDX Upper 32-bits of MSR value.
1638 <b>Example usage</b>
1642 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
1643 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);
1645 @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.
1647 #define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395
1650 Package. Uncore U-box perfmon global control MSR.
1652 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)
1653 @param EAX Lower 32-bits of MSR value.
1654 @param EDX Upper 32-bits of MSR value.
1656 <b>Example usage</b>
1660 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
1661 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);
1663 @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.
1665 #define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00
1668 Package. Uncore U-box perfmon global status MSR.
1670 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)
1671 @param EAX Lower 32-bits of MSR value.
1672 @param EDX Upper 32-bits of MSR value.
1674 <b>Example usage</b>
1678 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
1679 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);
1681 @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.
1683 #define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01
1686 Package. Uncore U-box perfmon global overflow control MSR.
1688 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)
1689 @param EAX Lower 32-bits of MSR value.
1690 @param EDX Upper 32-bits of MSR value.
1692 <b>Example usage</b>
1696 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
1697 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);
1699 @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.
1701 #define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02
1704 Package. Uncore U-box perfmon event select MSR.
1706 @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)
1707 @param EAX Lower 32-bits of MSR value.
1708 @param EDX Upper 32-bits of MSR value.
1710 <b>Example usage</b>
1714 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
1715 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);
1717 @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.
1719 #define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10
1722 Package. Uncore U-box perfmon counter MSR.
1724 @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)
1725 @param EAX Lower 32-bits of MSR value.
1726 @param EDX Upper 32-bits of MSR value.
1728 <b>Example usage</b>
1732 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
1733 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);
1735 @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.
1737 #define MSR_NEHALEM_U_PMON_CTR 0x00000C11
1740 Package. Uncore B-box 0 perfmon local box control MSR.
1742 @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)
1743 @param EAX Lower 32-bits of MSR value.
1744 @param EDX Upper 32-bits of MSR value.
1746 <b>Example usage</b>
1750 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
1751 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);
1753 @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.
1755 #define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20
1758 Package. Uncore B-box 0 perfmon local box status MSR.
1760 @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)
1761 @param EAX Lower 32-bits of MSR value.
1762 @param EDX Upper 32-bits of MSR value.
1764 <b>Example usage</b>
1768 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
1769 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);
1771 @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.
1773 #define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21
1776 Package. Uncore B-box 0 perfmon local box overflow control MSR.
1778 @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)
1779 @param EAX Lower 32-bits of MSR value.
1780 @param EDX Upper 32-bits of MSR value.
1782 <b>Example usage</b>
1786 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
1787 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);
1789 @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.
1791 #define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22
1794 Package. Uncore B-box 0 perfmon event select MSR.
1796 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)
1797 @param EAX Lower 32-bits of MSR value.
1798 @param EDX Upper 32-bits of MSR value.
1800 <b>Example usage</b>
1804 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
1805 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);
1807 @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.
1809 #define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30
1812 Package. Uncore B-box 0 perfmon counter MSR.
1814 @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)
1815 @param EAX Lower 32-bits of MSR value.
1816 @param EDX Upper 32-bits of MSR value.
1818 <b>Example usage</b>
1822 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
1823 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);
1825 @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.
1827 #define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31
1830 Package. Uncore B-box 0 perfmon event select MSR.
1832 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)
1833 @param EAX Lower 32-bits of MSR value.
1834 @param EDX Upper 32-bits of MSR value.
1836 <b>Example usage</b>
1840 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
1841 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);
1843 @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.
1845 #define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32
1848 Package. Uncore B-box 0 perfmon counter MSR.
1850 @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)
1851 @param EAX Lower 32-bits of MSR value.
1852 @param EDX Upper 32-bits of MSR value.
1854 <b>Example usage</b>
1858 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
1859 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);
1861 @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.
1863 #define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33
1866 Package. Uncore B-box 0 perfmon event select MSR.
1868 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)
1869 @param EAX Lower 32-bits of MSR value.
1870 @param EDX Upper 32-bits of MSR value.
1872 <b>Example usage</b>
1876 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
1877 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);
1879 @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.
1881 #define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34
1884 Package. Uncore B-box 0 perfmon counter MSR.
1886 @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)
1887 @param EAX Lower 32-bits of MSR value.
1888 @param EDX Upper 32-bits of MSR value.
1890 <b>Example usage</b>
1894 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
1895 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);
1897 @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.
1899 #define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35
1902 Package. Uncore B-box 0 perfmon event select MSR.
1904 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)
1905 @param EAX Lower 32-bits of MSR value.
1906 @param EDX Upper 32-bits of MSR value.
1908 <b>Example usage</b>
1912 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
1913 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);
1915 @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.
1917 #define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36
1920 Package. Uncore B-box 0 perfmon counter MSR.
1922 @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)
1923 @param EAX Lower 32-bits of MSR value.
1924 @param EDX Upper 32-bits of MSR value.
1926 <b>Example usage</b>
1930 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
1931 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);
1933 @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.
1935 #define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37
1938 Package. Uncore S-box 0 perfmon local box control MSR.
1940 @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)
1941 @param EAX Lower 32-bits of MSR value.
1942 @param EDX Upper 32-bits of MSR value.
1944 <b>Example usage</b>
1948 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
1949 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);
1951 @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.
1953 #define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40
1956 Package. Uncore S-box 0 perfmon local box status MSR.
1958 @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)
1959 @param EAX Lower 32-bits of MSR value.
1960 @param EDX Upper 32-bits of MSR value.
1962 <b>Example usage</b>
1966 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
1967 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);
1969 @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.
1971 #define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41
1974 Package. Uncore S-box 0 perfmon local box overflow control MSR.
1976 @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)
1977 @param EAX Lower 32-bits of MSR value.
1978 @param EDX Upper 32-bits of MSR value.
1980 <b>Example usage</b>
1984 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
1985 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);
1987 @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.
1989 #define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42
1992 Package. Uncore S-box 0 perfmon event select MSR.
1994 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)
1995 @param EAX Lower 32-bits of MSR value.
1996 @param EDX Upper 32-bits of MSR value.
1998 <b>Example usage</b>
2002 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
2003 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);
2005 @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.
2007 #define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50
2010 Package. Uncore S-box 0 perfmon counter MSR.
2012 @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)
2013 @param EAX Lower 32-bits of MSR value.
2014 @param EDX Upper 32-bits of MSR value.
2016 <b>Example usage</b>
2020 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
2021 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);
2023 @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
2025 #define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51
2028 Package. Uncore S-box 0 perfmon event select MSR.
2030 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)
2031 @param EAX Lower 32-bits of MSR value.
2032 @param EDX Upper 32-bits of MSR value.
2034 <b>Example usage</b>
2038 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
2039 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);
2041 @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.
2043 #define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52
2046 Package. Uncore S-box 0 perfmon counter MSR.
2048 @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)
2049 @param EAX Lower 32-bits of MSR value.
2050 @param EDX Upper 32-bits of MSR value.
2052 <b>Example usage</b>
2056 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
2057 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);
2059 @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
2061 #define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53
2064 Package. Uncore S-box 0 perfmon event select MSR.
2066 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)
2067 @param EAX Lower 32-bits of MSR value.
2068 @param EDX Upper 32-bits of MSR value.
2070 <b>Example usage</b>
2074 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
2075 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);
2077 @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.
2079 #define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54
2082 Package. Uncore S-box 0 perfmon counter MSR.
2084 @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)
2085 @param EAX Lower 32-bits of MSR value.
2086 @param EDX Upper 32-bits of MSR value.
2088 <b>Example usage</b>
2092 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
2093 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);
2095 @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
2097 #define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55
2100 Package. Uncore S-box 0 perfmon event select MSR.
2102 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)
2103 @param EAX Lower 32-bits of MSR value.
2104 @param EDX Upper 32-bits of MSR value.
2106 <b>Example usage</b>
2110 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
2111 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);
2113 @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.
2115 #define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56
2118 Package. Uncore S-box 0 perfmon counter MSR.
2120 @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)
2121 @param EAX Lower 32-bits of MSR value.
2122 @param EDX Upper 32-bits of MSR value.
2124 <b>Example usage</b>
2128 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
2129 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);
2131 @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
2133 #define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57
2136 Package. Uncore B-box 1 perfmon local box control MSR.
2138 @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)
2139 @param EAX Lower 32-bits of MSR value.
2140 @param EDX Upper 32-bits of MSR value.
2142 <b>Example usage</b>
2146 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
2147 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);
2149 @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.
2151 #define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60
2154 Package. Uncore B-box 1 perfmon local box status MSR.
2156 @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)
2157 @param EAX Lower 32-bits of MSR value.
2158 @param EDX Upper 32-bits of MSR value.
2160 <b>Example usage</b>
2164 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
2165 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);
2167 @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.
2169 #define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61
2172 Package. Uncore B-box 1 perfmon local box overflow control MSR.
2174 @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)
2175 @param EAX Lower 32-bits of MSR value.
2176 @param EDX Upper 32-bits of MSR value.
2178 <b>Example usage</b>
2182 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
2183 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);
2185 @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.
2187 #define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62
2190 Package. Uncore B-box 1 perfmon event select MSR.
2192 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)
2193 @param EAX Lower 32-bits of MSR value.
2194 @param EDX Upper 32-bits of MSR value.
2196 <b>Example usage</b>
2200 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
2201 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);
2203 @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.
2205 #define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70
2208 Package. Uncore B-box 1 perfmon counter MSR.
2210 @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)
2211 @param EAX Lower 32-bits of MSR value.
2212 @param EDX Upper 32-bits of MSR value.
2214 <b>Example usage</b>
2218 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
2219 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);
2221 @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.
2223 #define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71
2226 Package. Uncore B-box 1 perfmon event select MSR.
2228 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)
2229 @param EAX Lower 32-bits of MSR value.
2230 @param EDX Upper 32-bits of MSR value.
2232 <b>Example usage</b>
2236 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
2237 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);
2239 @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.
2241 #define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72
2244 Package. Uncore B-box 1 perfmon counter MSR.
2246 @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)
2247 @param EAX Lower 32-bits of MSR value.
2248 @param EDX Upper 32-bits of MSR value.
2250 <b>Example usage</b>
2254 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
2255 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);
2257 @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.
2259 #define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73
2262 Package. Uncore B-box 1 perfmon event select MSR.
2264 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)
2265 @param EAX Lower 32-bits of MSR value.
2266 @param EDX Upper 32-bits of MSR value.
2268 <b>Example usage</b>
2272 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
2273 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);
2275 @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.
2277 #define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74
2280 Package. Uncore B-box 1 perfmon counter MSR.
2282 @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)
2283 @param EAX Lower 32-bits of MSR value.
2284 @param EDX Upper 32-bits of MSR value.
2286 <b>Example usage</b>
2290 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
2291 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);
2293 @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.
2295 #define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75
2298 Package. Uncore B-box 1vperfmon event select MSR.
2300 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)
2301 @param EAX Lower 32-bits of MSR value.
2302 @param EDX Upper 32-bits of MSR value.
2304 <b>Example usage</b>
2308 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
2309 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);
2311 @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.
2313 #define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76
2316 Package. Uncore B-box 1 perfmon counter MSR.
2318 @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)
2319 @param EAX Lower 32-bits of MSR value.
2320 @param EDX Upper 32-bits of MSR value.
2322 <b>Example usage</b>
2326 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
2327 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);
2329 @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.
2331 #define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77
2334 Package. Uncore W-box perfmon local box control MSR.
2336 @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)
2337 @param EAX Lower 32-bits of MSR value.
2338 @param EDX Upper 32-bits of MSR value.
2340 <b>Example usage</b>
2344 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
2345 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);
2347 @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.
2349 #define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80
2352 Package. Uncore W-box perfmon local box status MSR.
2354 @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)
2355 @param EAX Lower 32-bits of MSR value.
2356 @param EDX Upper 32-bits of MSR value.
2358 <b>Example usage</b>
2362 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
2363 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);
2365 @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.
2367 #define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81
2370 Package. Uncore W-box perfmon local box overflow control MSR.
2372 @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)
2373 @param EAX Lower 32-bits of MSR value.
2374 @param EDX Upper 32-bits of MSR value.
2376 <b>Example usage</b>
2380 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
2381 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);
2383 @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.
2385 #define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82
2388 Package. Uncore W-box perfmon event select MSR.
2390 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)
2391 @param EAX Lower 32-bits of MSR value.
2392 @param EDX Upper 32-bits of MSR value.
2394 <b>Example usage</b>
2398 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
2399 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);
2401 @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.
2403 #define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90
2406 Package. Uncore W-box perfmon counter MSR.
2408 @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)
2409 @param EAX Lower 32-bits of MSR value.
2410 @param EDX Upper 32-bits of MSR value.
2412 <b>Example usage</b>
2416 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
2417 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);
2419 @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.
2421 #define MSR_NEHALEM_W_PMON_CTR0 0x00000C91
2424 Package. Uncore W-box perfmon event select MSR.
2426 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)
2427 @param EAX Lower 32-bits of MSR value.
2428 @param EDX Upper 32-bits of MSR value.
2430 <b>Example usage</b>
2434 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
2435 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);
2437 @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.
2439 #define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92
2442 Package. Uncore W-box perfmon counter MSR.
2444 @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)
2445 @param EAX Lower 32-bits of MSR value.
2446 @param EDX Upper 32-bits of MSR value.
2448 <b>Example usage</b>
2452 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
2453 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);
2455 @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.
2457 #define MSR_NEHALEM_W_PMON_CTR1 0x00000C93
2460 Package. Uncore W-box perfmon event select MSR.
2462 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)
2463 @param EAX Lower 32-bits of MSR value.
2464 @param EDX Upper 32-bits of MSR value.
2466 <b>Example usage</b>
2470 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
2471 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);
2473 @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.
2475 #define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94
2478 Package. Uncore W-box perfmon counter MSR.
2480 @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)
2481 @param EAX Lower 32-bits of MSR value.
2482 @param EDX Upper 32-bits of MSR value.
2484 <b>Example usage</b>
2488 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
2489 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);
2491 @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.
2493 #define MSR_NEHALEM_W_PMON_CTR2 0x00000C95
2496 Package. Uncore W-box perfmon event select MSR.
2498 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)
2499 @param EAX Lower 32-bits of MSR value.
2500 @param EDX Upper 32-bits of MSR value.
2502 <b>Example usage</b>
2506 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
2507 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);
2509 @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.
2511 #define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96
2514 Package. Uncore W-box perfmon counter MSR.
2516 @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)
2517 @param EAX Lower 32-bits of MSR value.
2518 @param EDX Upper 32-bits of MSR value.
2520 <b>Example usage</b>
2524 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
2525 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);
2527 @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.
2529 #define MSR_NEHALEM_W_PMON_CTR3 0x00000C97
2532 Package. Uncore M-box 0 perfmon local box control MSR.
2534 @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)
2535 @param EAX Lower 32-bits of MSR value.
2536 @param EDX Upper 32-bits of MSR value.
2538 <b>Example usage</b>
2542 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
2543 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);
2545 @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.
2547 #define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0
2550 Package. Uncore M-box 0 perfmon local box status MSR.
2552 @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)
2553 @param EAX Lower 32-bits of MSR value.
2554 @param EDX Upper 32-bits of MSR value.
2556 <b>Example usage</b>
2560 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
2561 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);
2563 @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.
2565 #define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1
2568 Package. Uncore M-box 0 perfmon local box overflow control MSR.
2570 @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)
2571 @param EAX Lower 32-bits of MSR value.
2572 @param EDX Upper 32-bits of MSR value.
2574 <b>Example usage</b>
2578 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
2579 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);
2581 @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.
2583 #define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2
2586 Package. Uncore M-box 0 perfmon time stamp unit select MSR.
2588 @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)
2589 @param EAX Lower 32-bits of MSR value.
2590 @param EDX Upper 32-bits of MSR value.
2592 <b>Example usage</b>
2596 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
2597 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);
2599 @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.
2601 #define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4
2604 Package. Uncore M-box 0 perfmon DSP unit select MSR.
2606 @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)
2607 @param EAX Lower 32-bits of MSR value.
2608 @param EDX Upper 32-bits of MSR value.
2610 <b>Example usage</b>
2614 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
2615 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);
2617 @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.
2619 #define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5
2622 Package. Uncore M-box 0 perfmon ISS unit select MSR.
2624 @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)
2625 @param EAX Lower 32-bits of MSR value.
2626 @param EDX Upper 32-bits of MSR value.
2628 <b>Example usage</b>
2632 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
2633 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);
2635 @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.
2637 #define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6
2640 Package. Uncore M-box 0 perfmon MAP unit select MSR.
2642 @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)
2643 @param EAX Lower 32-bits of MSR value.
2644 @param EDX Upper 32-bits of MSR value.
2646 <b>Example usage</b>
2650 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
2651 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);
2653 @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.
2655 #define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7
2658 Package. Uncore M-box 0 perfmon MIC THR select MSR.
2660 @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)
2661 @param EAX Lower 32-bits of MSR value.
2662 @param EDX Upper 32-bits of MSR value.
2664 <b>Example usage</b>
2668 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
2669 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);
2671 @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.
2673 #define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8
2676 Package. Uncore M-box 0 perfmon PGT unit select MSR.
2678 @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)
2679 @param EAX Lower 32-bits of MSR value.
2680 @param EDX Upper 32-bits of MSR value.
2682 <b>Example usage</b>
2686 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
2687 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);
2689 @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.
2691 #define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9
2694 Package. Uncore M-box 0 perfmon PLD unit select MSR.
2696 @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)
2697 @param EAX Lower 32-bits of MSR value.
2698 @param EDX Upper 32-bits of MSR value.
2700 <b>Example usage</b>
2704 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
2705 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);
2707 @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.
2709 #define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA
2712 Package. Uncore M-box 0 perfmon ZDP unit select MSR.
2714 @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)
2715 @param EAX Lower 32-bits of MSR value.
2716 @param EDX Upper 32-bits of MSR value.
2718 <b>Example usage</b>
2722 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
2723 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);
2725 @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.
2727 #define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB
2730 Package. Uncore M-box 0 perfmon event select MSR.
2732 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)
2733 @param EAX Lower 32-bits of MSR value.
2734 @param EDX Upper 32-bits of MSR value.
2736 <b>Example usage</b>
2740 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
2741 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);
2743 @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.
2745 #define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0
2748 Package. Uncore M-box 0 perfmon counter MSR.
2750 @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)
2751 @param EAX Lower 32-bits of MSR value.
2752 @param EDX Upper 32-bits of MSR value.
2754 <b>Example usage</b>
2758 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
2759 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);
2761 @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.
2763 #define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1
2766 Package. Uncore M-box 0 perfmon event select MSR.
2768 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)
2769 @param EAX Lower 32-bits of MSR value.
2770 @param EDX Upper 32-bits of MSR value.
2772 <b>Example usage</b>
2776 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
2777 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);
2779 @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.
2781 #define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2
2784 Package. Uncore M-box 0 perfmon counter MSR.
2786 @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)
2787 @param EAX Lower 32-bits of MSR value.
2788 @param EDX Upper 32-bits of MSR value.
2790 <b>Example usage</b>
2794 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
2795 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);
2797 @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.
2799 #define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3
2802 Package. Uncore M-box 0 perfmon event select MSR.
2804 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)
2805 @param EAX Lower 32-bits of MSR value.
2806 @param EDX Upper 32-bits of MSR value.
2808 <b>Example usage</b>
2812 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
2813 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);
2815 @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.
2817 #define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4
2820 Package. Uncore M-box 0 perfmon counter MSR.
2822 @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)
2823 @param EAX Lower 32-bits of MSR value.
2824 @param EDX Upper 32-bits of MSR value.
2826 <b>Example usage</b>
2830 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
2831 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);
2833 @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.
2835 #define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5
2838 Package. Uncore M-box 0 perfmon event select MSR.
2840 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)
2841 @param EAX Lower 32-bits of MSR value.
2842 @param EDX Upper 32-bits of MSR value.
2844 <b>Example usage</b>
2848 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
2849 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);
2851 @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.
2853 #define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6
2856 Package. Uncore M-box 0 perfmon counter MSR.
2858 @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)
2859 @param EAX Lower 32-bits of MSR value.
2860 @param EDX Upper 32-bits of MSR value.
2862 <b>Example usage</b>
2866 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
2867 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);
2869 @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.
2871 #define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7
2874 Package. Uncore M-box 0 perfmon event select MSR.
2876 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)
2877 @param EAX Lower 32-bits of MSR value.
2878 @param EDX Upper 32-bits of MSR value.
2880 <b>Example usage</b>
2884 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
2885 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);
2887 @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.
2889 #define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8
2892 Package. Uncore M-box 0 perfmon counter MSR.
2894 @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)
2895 @param EAX Lower 32-bits of MSR value.
2896 @param EDX Upper 32-bits of MSR value.
2898 <b>Example usage</b>
2902 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
2903 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);
2905 @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.
2907 #define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9
2910 Package. Uncore M-box 0 perfmon event select MSR.
2912 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)
2913 @param EAX Lower 32-bits of MSR value.
2914 @param EDX Upper 32-bits of MSR value.
2916 <b>Example usage</b>
2920 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
2921 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);
2923 @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.
2925 #define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA
2928 Package. Uncore M-box 0 perfmon counter MSR.
2930 @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)
2931 @param EAX Lower 32-bits of MSR value.
2932 @param EDX Upper 32-bits of MSR value.
2934 <b>Example usage</b>
2938 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
2939 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);
2941 @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.
2943 #define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB
2946 Package. Uncore S-box 1 perfmon local box control MSR.
2948 @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)
2949 @param EAX Lower 32-bits of MSR value.
2950 @param EDX Upper 32-bits of MSR value.
2952 <b>Example usage</b>
2956 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
2957 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);
2959 @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.
2961 #define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0
2964 Package. Uncore S-box 1 perfmon local box status MSR.
2966 @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)
2967 @param EAX Lower 32-bits of MSR value.
2968 @param EDX Upper 32-bits of MSR value.
2970 <b>Example usage</b>
2974 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
2975 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);
2977 @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.
2979 #define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1
2982 Package. Uncore S-box 1 perfmon local box overflow control MSR.
2984 @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)
2985 @param EAX Lower 32-bits of MSR value.
2986 @param EDX Upper 32-bits of MSR value.
2988 <b>Example usage</b>
2992 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
2993 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);
2995 @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.
2997 #define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2
3000 Package. Uncore S-box 1 perfmon event select MSR.
3002 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)
3003 @param EAX Lower 32-bits of MSR value.
3004 @param EDX Upper 32-bits of MSR value.
3006 <b>Example usage</b>
3010 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
3011 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);
3013 @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.
3015 #define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0
3018 Package. Uncore S-box 1 perfmon counter MSR.
3020 @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)
3021 @param EAX Lower 32-bits of MSR value.
3022 @param EDX Upper 32-bits of MSR value.
3024 <b>Example usage</b>
3028 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
3029 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);
3031 @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
3033 #define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1
3036 Package. Uncore S-box 1 perfmon event select MSR.
3038 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)
3039 @param EAX Lower 32-bits of MSR value.
3040 @param EDX Upper 32-bits of MSR value.
3042 <b>Example usage</b>
3046 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
3047 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);
3049 @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.
3051 #define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2
3054 Package. Uncore S-box 1 perfmon counter MSR.
3056 @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)
3057 @param EAX Lower 32-bits of MSR value.
3058 @param EDX Upper 32-bits of MSR value.
3060 <b>Example usage</b>
3064 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
3065 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);
3067 @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
3069 #define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3
3072 Package. Uncore S-box 1 perfmon event select MSR.
3074 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)
3075 @param EAX Lower 32-bits of MSR value.
3076 @param EDX Upper 32-bits of MSR value.
3078 <b>Example usage</b>
3082 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
3083 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);
3085 @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.
3087 #define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4
3090 Package. Uncore S-box 1 perfmon counter MSR.
3092 @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)
3093 @param EAX Lower 32-bits of MSR value.
3094 @param EDX Upper 32-bits of MSR value.
3096 <b>Example usage</b>
3100 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
3101 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);
3103 @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
3105 #define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5
3108 Package. Uncore S-box 1 perfmon event select MSR.
3110 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)
3111 @param EAX Lower 32-bits of MSR value.
3112 @param EDX Upper 32-bits of MSR value.
3114 <b>Example usage</b>
3118 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
3119 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);
3121 @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.
3123 #define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6
3126 Package. Uncore S-box 1 perfmon counter MSR.
3128 @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)
3129 @param EAX Lower 32-bits of MSR value.
3130 @param EDX Upper 32-bits of MSR value.
3132 <b>Example usage</b>
3136 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
3137 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);
3139 @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
3141 #define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7
3144 Package. Uncore M-box 1 perfmon local box control MSR.
3146 @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)
3147 @param EAX Lower 32-bits of MSR value.
3148 @param EDX Upper 32-bits of MSR value.
3150 <b>Example usage</b>
3154 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
3155 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);
3157 @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.
3159 #define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0
3162 Package. Uncore M-box 1 perfmon local box status MSR.
3164 @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)
3165 @param EAX Lower 32-bits of MSR value.
3166 @param EDX Upper 32-bits of MSR value.
3168 <b>Example usage</b>
3172 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
3173 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);
3175 @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.
3177 #define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1
3180 Package. Uncore M-box 1 perfmon local box overflow control MSR.
3182 @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)
3183 @param EAX Lower 32-bits of MSR value.
3184 @param EDX Upper 32-bits of MSR value.
3186 <b>Example usage</b>
3190 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
3191 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);
3193 @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.
3195 #define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2
3198 Package. Uncore M-box 1 perfmon time stamp unit select MSR.
3200 @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)
3201 @param EAX Lower 32-bits of MSR value.
3202 @param EDX Upper 32-bits of MSR value.
3204 <b>Example usage</b>
3208 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
3209 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);
3211 @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.
3213 #define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4
3216 Package. Uncore M-box 1 perfmon DSP unit select MSR.
3218 @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)
3219 @param EAX Lower 32-bits of MSR value.
3220 @param EDX Upper 32-bits of MSR value.
3222 <b>Example usage</b>
3226 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
3227 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);
3229 @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.
3231 #define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5
3234 Package. Uncore M-box 1 perfmon ISS unit select MSR.
3236 @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)
3237 @param EAX Lower 32-bits of MSR value.
3238 @param EDX Upper 32-bits of MSR value.
3240 <b>Example usage</b>
3244 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
3245 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);
3247 @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.
3249 #define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6
3252 Package. Uncore M-box 1 perfmon MAP unit select MSR.
3254 @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)
3255 @param EAX Lower 32-bits of MSR value.
3256 @param EDX Upper 32-bits of MSR value.
3258 <b>Example usage</b>
3262 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
3263 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);
3265 @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.
3267 #define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7
3270 Package. Uncore M-box 1 perfmon MIC THR select MSR.
3272 @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)
3273 @param EAX Lower 32-bits of MSR value.
3274 @param EDX Upper 32-bits of MSR value.
3276 <b>Example usage</b>
3280 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
3281 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);
3283 @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.
3285 #define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8
3288 Package. Uncore M-box 1 perfmon PGT unit select MSR.
3290 @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)
3291 @param EAX Lower 32-bits of MSR value.
3292 @param EDX Upper 32-bits of MSR value.
3294 <b>Example usage</b>
3298 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
3299 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);
3301 @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.
3303 #define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9
3306 Package. Uncore M-box 1 perfmon PLD unit select MSR.
3308 @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)
3309 @param EAX Lower 32-bits of MSR value.
3310 @param EDX Upper 32-bits of MSR value.
3312 <b>Example usage</b>
3316 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
3317 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);
3319 @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.
3321 #define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA
3324 Package. Uncore M-box 1 perfmon ZDP unit select MSR.
3326 @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)
3327 @param EAX Lower 32-bits of MSR value.
3328 @param EDX Upper 32-bits of MSR value.
3330 <b>Example usage</b>
3334 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
3335 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);
3337 @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.
3339 #define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB
3342 Package. Uncore M-box 1 perfmon event select MSR.
3344 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)
3345 @param EAX Lower 32-bits of MSR value.
3346 @param EDX Upper 32-bits of MSR value.
3348 <b>Example usage</b>
3352 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
3353 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);
3355 @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.
3357 #define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0
3360 Package. Uncore M-box 1 perfmon counter MSR.
3362 @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)
3363 @param EAX Lower 32-bits of MSR value.
3364 @param EDX Upper 32-bits of MSR value.
3366 <b>Example usage</b>
3370 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
3371 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);
3373 @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.
3375 #define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1
3378 Package. Uncore M-box 1 perfmon event select MSR.
3380 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)
3381 @param EAX Lower 32-bits of MSR value.
3382 @param EDX Upper 32-bits of MSR value.
3384 <b>Example usage</b>
3388 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
3389 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);
3391 @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.
3393 #define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2
3396 Package. Uncore M-box 1 perfmon counter MSR.
3398 @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)
3399 @param EAX Lower 32-bits of MSR value.
3400 @param EDX Upper 32-bits of MSR value.
3402 <b>Example usage</b>
3406 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
3407 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);
3409 @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.
3411 #define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3
3414 Package. Uncore M-box 1 perfmon event select MSR.
3416 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)
3417 @param EAX Lower 32-bits of MSR value.
3418 @param EDX Upper 32-bits of MSR value.
3420 <b>Example usage</b>
3424 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
3425 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);
3427 @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.
3429 #define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4
3432 Package. Uncore M-box 1 perfmon counter MSR.
3434 @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)
3435 @param EAX Lower 32-bits of MSR value.
3436 @param EDX Upper 32-bits of MSR value.
3438 <b>Example usage</b>
3442 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
3443 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);
3445 @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.
3447 #define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5
3450 Package. Uncore M-box 1 perfmon event select MSR.
3452 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)
3453 @param EAX Lower 32-bits of MSR value.
3454 @param EDX Upper 32-bits of MSR value.
3456 <b>Example usage</b>
3460 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
3461 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);
3463 @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.
3465 #define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6
3468 Package. Uncore M-box 1 perfmon counter MSR.
3470 @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)
3471 @param EAX Lower 32-bits of MSR value.
3472 @param EDX Upper 32-bits of MSR value.
3474 <b>Example usage</b>
3478 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
3479 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);
3481 @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.
3483 #define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7
3486 Package. Uncore M-box 1 perfmon event select MSR.
3488 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)
3489 @param EAX Lower 32-bits of MSR value.
3490 @param EDX Upper 32-bits of MSR value.
3492 <b>Example usage</b>
3496 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
3497 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);
3499 @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.
3501 #define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8
3504 Package. Uncore M-box 1 perfmon counter MSR.
3506 @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)
3507 @param EAX Lower 32-bits of MSR value.
3508 @param EDX Upper 32-bits of MSR value.
3510 <b>Example usage</b>
3514 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
3515 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);
3517 @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.
3519 #define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9
3522 Package. Uncore M-box 1 perfmon event select MSR.
3524 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)
3525 @param EAX Lower 32-bits of MSR value.
3526 @param EDX Upper 32-bits of MSR value.
3528 <b>Example usage</b>
3532 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
3533 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);
3535 @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.
3537 #define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA
3540 Package. Uncore M-box 1 perfmon counter MSR.
3542 @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)
3543 @param EAX Lower 32-bits of MSR value.
3544 @param EDX Upper 32-bits of MSR value.
3546 <b>Example usage</b>
3550 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
3551 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);
3553 @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.
3555 #define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB
3558 Package. Uncore C-box 0 perfmon local box control MSR.
3560 @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)
3561 @param EAX Lower 32-bits of MSR value.
3562 @param EDX Upper 32-bits of MSR value.
3564 <b>Example usage</b>
3568 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
3569 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);
3571 @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.
3573 #define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00
3576 Package. Uncore C-box 0 perfmon local box status MSR.
3578 @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)
3579 @param EAX Lower 32-bits of MSR value.
3580 @param EDX Upper 32-bits of MSR value.
3582 <b>Example usage</b>
3586 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
3587 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);
3589 @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
3591 #define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01
3594 Package. Uncore C-box 0 perfmon local box overflow control MSR.
3596 @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)
3597 @param EAX Lower 32-bits of MSR value.
3598 @param EDX Upper 32-bits of MSR value.
3600 <b>Example usage</b>
3604 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
3605 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);
3607 @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.
3609 #define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02
3612 Package. Uncore C-box 0 perfmon event select MSR.
3614 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)
3615 @param EAX Lower 32-bits of MSR value.
3616 @param EDX Upper 32-bits of MSR value.
3618 <b>Example usage</b>
3622 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
3623 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);
3625 @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.
3627 #define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10
3630 Package. Uncore C-box 0 perfmon counter MSR.
3632 @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)
3633 @param EAX Lower 32-bits of MSR value.
3634 @param EDX Upper 32-bits of MSR value.
3636 <b>Example usage</b>
3640 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
3641 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);
3643 @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
3645 #define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11
3648 Package. Uncore C-box 0 perfmon event select MSR.
3650 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)
3651 @param EAX Lower 32-bits of MSR value.
3652 @param EDX Upper 32-bits of MSR value.
3654 <b>Example usage</b>
3658 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
3659 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);
3661 @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.
3663 #define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12
3666 Package. Uncore C-box 0 perfmon counter MSR.
3668 @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)
3669 @param EAX Lower 32-bits of MSR value.
3670 @param EDX Upper 32-bits of MSR value.
3672 <b>Example usage</b>
3676 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
3677 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);
3679 @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
3681 #define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13
3684 Package. Uncore C-box 0 perfmon event select MSR.
3686 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)
3687 @param EAX Lower 32-bits of MSR value.
3688 @param EDX Upper 32-bits of MSR value.
3690 <b>Example usage</b>
3694 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
3695 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);
3697 @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.
3699 #define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14
3702 Package. Uncore C-box 0 perfmon counter MSR.
3704 @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)
3705 @param EAX Lower 32-bits of MSR value.
3706 @param EDX Upper 32-bits of MSR value.
3708 <b>Example usage</b>
3712 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
3713 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);
3715 @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
3717 #define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15
3720 Package. Uncore C-box 0 perfmon event select MSR.
3722 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)
3723 @param EAX Lower 32-bits of MSR value.
3724 @param EDX Upper 32-bits of MSR value.
3726 <b>Example usage</b>
3730 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
3731 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);
3733 @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.
3735 #define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16
3738 Package. Uncore C-box 0 perfmon counter MSR.
3740 @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)
3741 @param EAX Lower 32-bits of MSR value.
3742 @param EDX Upper 32-bits of MSR value.
3744 <b>Example usage</b>
3748 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
3749 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);
3751 @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
3753 #define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17
3756 Package. Uncore C-box 0 perfmon event select MSR.
3758 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)
3759 @param EAX Lower 32-bits of MSR value.
3760 @param EDX Upper 32-bits of MSR value.
3762 <b>Example usage</b>
3766 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
3767 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);
3769 @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.
3771 #define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18
3774 Package. Uncore C-box 0 perfmon counter MSR.
3776 @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)
3777 @param EAX Lower 32-bits of MSR value.
3778 @param EDX Upper 32-bits of MSR value.
3780 <b>Example usage</b>
3784 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
3785 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);
3787 @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.
3789 #define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19
3792 Package. Uncore C-box 0 perfmon event select MSR.
3794 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)
3795 @param EAX Lower 32-bits of MSR value.
3796 @param EDX Upper 32-bits of MSR value.
3798 <b>Example usage</b>
3802 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
3803 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);
3805 @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.
3807 #define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A
3810 Package. Uncore C-box 0 perfmon counter MSR.
3812 @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)
3813 @param EAX Lower 32-bits of MSR value.
3814 @param EDX Upper 32-bits of MSR value.
3816 <b>Example usage</b>
3820 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
3821 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);
3823 @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.
3825 #define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B
3828 Package. Uncore C-box 4 perfmon local box control MSR.
3830 @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)
3831 @param EAX Lower 32-bits of MSR value.
3832 @param EDX Upper 32-bits of MSR value.
3834 <b>Example usage</b>
3838 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
3839 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);
3841 @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.
3843 #define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20
3846 Package. Uncore C-box 4 perfmon local box status MSR.
3848 @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)
3849 @param EAX Lower 32-bits of MSR value.
3850 @param EDX Upper 32-bits of MSR value.
3852 <b>Example usage</b>
3856 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
3857 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);
3859 @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
3861 #define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21
3864 Package. Uncore C-box 4 perfmon local box overflow control MSR.
3866 @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)
3867 @param EAX Lower 32-bits of MSR value.
3868 @param EDX Upper 32-bits of MSR value.
3870 <b>Example usage</b>
3874 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
3875 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);
3877 @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.
3879 #define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22
3882 Package. Uncore C-box 4 perfmon event select MSR.
3884 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)
3885 @param EAX Lower 32-bits of MSR value.
3886 @param EDX Upper 32-bits of MSR value.
3888 <b>Example usage</b>
3892 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
3893 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);
3895 @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.
3897 #define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30
3900 Package. Uncore C-box 4 perfmon counter MSR.
3902 @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)
3903 @param EAX Lower 32-bits of MSR value.
3904 @param EDX Upper 32-bits of MSR value.
3906 <b>Example usage</b>
3910 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
3911 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);
3913 @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
3915 #define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31
3918 Package. Uncore C-box 4 perfmon event select MSR.
3920 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)
3921 @param EAX Lower 32-bits of MSR value.
3922 @param EDX Upper 32-bits of MSR value.
3924 <b>Example usage</b>
3928 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
3929 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);
3931 @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.
3933 #define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32
3936 Package. Uncore C-box 4 perfmon counter MSR.
3938 @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)
3939 @param EAX Lower 32-bits of MSR value.
3940 @param EDX Upper 32-bits of MSR value.
3942 <b>Example usage</b>
3946 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
3947 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);
3949 @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
3951 #define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33
3954 Package. Uncore C-box 4 perfmon event select MSR.
3956 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)
3957 @param EAX Lower 32-bits of MSR value.
3958 @param EDX Upper 32-bits of MSR value.
3960 <b>Example usage</b>
3964 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
3965 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);
3967 @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.
3969 #define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34
3972 Package. Uncore C-box 4 perfmon counter MSR.
3974 @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)
3975 @param EAX Lower 32-bits of MSR value.
3976 @param EDX Upper 32-bits of MSR value.
3978 <b>Example usage</b>
3982 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
3983 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);
3985 @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
3987 #define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35
3990 Package. Uncore C-box 4 perfmon event select MSR.
3992 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)
3993 @param EAX Lower 32-bits of MSR value.
3994 @param EDX Upper 32-bits of MSR value.
3996 <b>Example usage</b>
4000 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
4001 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);
4003 @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.
4005 #define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36
4008 Package. Uncore C-box 4 perfmon counter MSR.
4010 @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)
4011 @param EAX Lower 32-bits of MSR value.
4012 @param EDX Upper 32-bits of MSR value.
4014 <b>Example usage</b>
4018 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
4019 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);
4021 @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4023 #define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37
4026 Package. Uncore C-box 4 perfmon event select MSR.
4028 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)
4029 @param EAX Lower 32-bits of MSR value.
4030 @param EDX Upper 32-bits of MSR value.
4032 <b>Example usage</b>
4036 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
4037 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);
4039 @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.
4041 #define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38
4044 Package. Uncore C-box 4 perfmon counter MSR.
4046 @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)
4047 @param EAX Lower 32-bits of MSR value.
4048 @param EDX Upper 32-bits of MSR value.
4050 <b>Example usage</b>
4054 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
4055 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);
4057 @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.
4059 #define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39
4062 Package. Uncore C-box 4 perfmon event select MSR.
4064 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)
4065 @param EAX Lower 32-bits of MSR value.
4066 @param EDX Upper 32-bits of MSR value.
4068 <b>Example usage</b>
4072 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
4073 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);
4075 @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.
4077 #define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A
4080 Package. Uncore C-box 4 perfmon counter MSR.
4082 @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)
4083 @param EAX Lower 32-bits of MSR value.
4084 @param EDX Upper 32-bits of MSR value.
4086 <b>Example usage</b>
4090 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
4091 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);
4093 @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.
4095 #define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B
4098 Package. Uncore C-box 2 perfmon local box control MSR.
4100 @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)
4101 @param EAX Lower 32-bits of MSR value.
4102 @param EDX Upper 32-bits of MSR value.
4104 <b>Example usage</b>
4108 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
4109 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);
4111 @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.
4113 #define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40
4116 Package. Uncore C-box 2 perfmon local box status MSR.
4118 @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)
4119 @param EAX Lower 32-bits of MSR value.
4120 @param EDX Upper 32-bits of MSR value.
4122 <b>Example usage</b>
4126 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
4127 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);
4129 @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
4131 #define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41
4134 Package. Uncore C-box 2 perfmon local box overflow control MSR.
4136 @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)
4137 @param EAX Lower 32-bits of MSR value.
4138 @param EDX Upper 32-bits of MSR value.
4140 <b>Example usage</b>
4144 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
4145 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);
4147 @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.
4149 #define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42
4152 Package. Uncore C-box 2 perfmon event select MSR.
4154 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)
4155 @param EAX Lower 32-bits of MSR value.
4156 @param EDX Upper 32-bits of MSR value.
4158 <b>Example usage</b>
4162 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
4163 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);
4165 @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.
4167 #define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50
4170 Package. Uncore C-box 2 perfmon counter MSR.
4172 @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)
4173 @param EAX Lower 32-bits of MSR value.
4174 @param EDX Upper 32-bits of MSR value.
4176 <b>Example usage</b>
4180 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
4181 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);
4183 @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
4185 #define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51
4188 Package. Uncore C-box 2 perfmon event select MSR.
4190 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)
4191 @param EAX Lower 32-bits of MSR value.
4192 @param EDX Upper 32-bits of MSR value.
4194 <b>Example usage</b>
4198 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
4199 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);
4201 @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.
4203 #define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52
4206 Package. Uncore C-box 2 perfmon counter MSR.
4208 @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)
4209 @param EAX Lower 32-bits of MSR value.
4210 @param EDX Upper 32-bits of MSR value.
4212 <b>Example usage</b>
4216 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
4217 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);
4219 @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
4221 #define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53
4224 Package. Uncore C-box 2 perfmon event select MSR.
4226 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)
4227 @param EAX Lower 32-bits of MSR value.
4228 @param EDX Upper 32-bits of MSR value.
4230 <b>Example usage</b>
4234 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
4235 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);
4237 @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.
4239 #define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54
4242 Package. Uncore C-box 2 perfmon counter MSR.
4244 @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)
4245 @param EAX Lower 32-bits of MSR value.
4246 @param EDX Upper 32-bits of MSR value.
4248 <b>Example usage</b>
4252 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
4253 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);
4255 @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
4257 #define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55
4260 Package. Uncore C-box 2 perfmon event select MSR.
4262 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)
4263 @param EAX Lower 32-bits of MSR value.
4264 @param EDX Upper 32-bits of MSR value.
4266 <b>Example usage</b>
4270 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
4271 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);
4273 @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.
4275 #define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56
4278 Package. Uncore C-box 2 perfmon counter MSR.
4280 @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)
4281 @param EAX Lower 32-bits of MSR value.
4282 @param EDX Upper 32-bits of MSR value.
4284 <b>Example usage</b>
4288 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
4289 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);
4291 @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
4293 #define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57
4296 Package. Uncore C-box 2 perfmon event select MSR.
4298 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)
4299 @param EAX Lower 32-bits of MSR value.
4300 @param EDX Upper 32-bits of MSR value.
4302 <b>Example usage</b>
4306 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
4307 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);
4309 @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.
4311 #define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58
4314 Package. Uncore C-box 2 perfmon counter MSR.
4316 @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)
4317 @param EAX Lower 32-bits of MSR value.
4318 @param EDX Upper 32-bits of MSR value.
4320 <b>Example usage</b>
4324 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
4325 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);
4327 @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.
4329 #define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59
4332 Package. Uncore C-box 2 perfmon event select MSR.
4334 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)
4335 @param EAX Lower 32-bits of MSR value.
4336 @param EDX Upper 32-bits of MSR value.
4338 <b>Example usage</b>
4342 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
4343 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);
4345 @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.
4347 #define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A
4350 Package. Uncore C-box 2 perfmon counter MSR.
4352 @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)
4353 @param EAX Lower 32-bits of MSR value.
4354 @param EDX Upper 32-bits of MSR value.
4356 <b>Example usage</b>
4360 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
4361 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);
4363 @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.
4365 #define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B
4368 Package. Uncore C-box 6 perfmon local box control MSR.
4370 @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)
4371 @param EAX Lower 32-bits of MSR value.
4372 @param EDX Upper 32-bits of MSR value.
4374 <b>Example usage</b>
4378 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
4379 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);
4381 @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.
4383 #define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60
4386 Package. Uncore C-box 6 perfmon local box status MSR.
4388 @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)
4389 @param EAX Lower 32-bits of MSR value.
4390 @param EDX Upper 32-bits of MSR value.
4392 <b>Example usage</b>
4396 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
4397 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);
4399 @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
4401 #define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61
4404 Package. Uncore C-box 6 perfmon local box overflow control MSR.
4406 @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)
4407 @param EAX Lower 32-bits of MSR value.
4408 @param EDX Upper 32-bits of MSR value.
4410 <b>Example usage</b>
4414 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
4415 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);
4417 @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.
4419 #define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62
4422 Package. Uncore C-box 6 perfmon event select MSR.
4424 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)
4425 @param EAX Lower 32-bits of MSR value.
4426 @param EDX Upper 32-bits of MSR value.
4428 <b>Example usage</b>
4432 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
4433 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);
4435 @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.
4437 #define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70
4440 Package. Uncore C-box 6 perfmon counter MSR.
4442 @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)
4443 @param EAX Lower 32-bits of MSR value.
4444 @param EDX Upper 32-bits of MSR value.
4446 <b>Example usage</b>
4450 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
4451 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);
4453 @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4455 #define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71
4458 Package. Uncore C-box 6 perfmon event select MSR.
4460 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)
4461 @param EAX Lower 32-bits of MSR value.
4462 @param EDX Upper 32-bits of MSR value.
4464 <b>Example usage</b>
4468 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
4469 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);
4471 @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.
4473 #define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72
4476 Package. Uncore C-box 6 perfmon counter MSR.
4478 @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)
4479 @param EAX Lower 32-bits of MSR value.
4480 @param EDX Upper 32-bits of MSR value.
4482 <b>Example usage</b>
4486 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
4487 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);
4489 @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4491 #define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73
4494 Package. Uncore C-box 6 perfmon event select MSR.
4496 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)
4497 @param EAX Lower 32-bits of MSR value.
4498 @param EDX Upper 32-bits of MSR value.
4500 <b>Example usage</b>
4504 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
4505 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);
4507 @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.
4509 #define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74
4512 Package. Uncore C-box 6 perfmon counter MSR.
4514 @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)
4515 @param EAX Lower 32-bits of MSR value.
4516 @param EDX Upper 32-bits of MSR value.
4518 <b>Example usage</b>
4522 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
4523 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);
4525 @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4527 #define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75
4530 Package. Uncore C-box 6 perfmon event select MSR.
4532 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)
4533 @param EAX Lower 32-bits of MSR value.
4534 @param EDX Upper 32-bits of MSR value.
4536 <b>Example usage</b>
4540 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
4541 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);
4543 @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.
4545 #define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76
4548 Package. Uncore C-box 6 perfmon counter MSR.
4550 @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)
4551 @param EAX Lower 32-bits of MSR value.
4552 @param EDX Upper 32-bits of MSR value.
4554 <b>Example usage</b>
4558 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
4559 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);
4561 @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4563 #define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77
4566 Package. Uncore C-box 6 perfmon event select MSR.
4568 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)
4569 @param EAX Lower 32-bits of MSR value.
4570 @param EDX Upper 32-bits of MSR value.
4572 <b>Example usage</b>
4576 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
4577 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);
4579 @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.
4581 #define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78
4584 Package. Uncore C-box 6 perfmon counter MSR.
4586 @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)
4587 @param EAX Lower 32-bits of MSR value.
4588 @param EDX Upper 32-bits of MSR value.
4590 <b>Example usage</b>
4594 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
4595 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);
4597 @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.
4599 #define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79
4602 Package. Uncore C-box 6 perfmon event select MSR.
4604 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)
4605 @param EAX Lower 32-bits of MSR value.
4606 @param EDX Upper 32-bits of MSR value.
4608 <b>Example usage</b>
4612 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
4613 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);
4615 @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.
4617 #define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A
4620 Package. Uncore C-box 6 perfmon counter MSR.
4622 @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)
4623 @param EAX Lower 32-bits of MSR value.
4624 @param EDX Upper 32-bits of MSR value.
4626 <b>Example usage</b>
4630 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
4631 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);
4633 @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.
4635 #define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B
4638 Package. Uncore C-box 1 perfmon local box control MSR.
4640 @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)
4641 @param EAX Lower 32-bits of MSR value.
4642 @param EDX Upper 32-bits of MSR value.
4644 <b>Example usage</b>
4648 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
4649 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);
4651 @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.
4653 #define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80
4656 Package. Uncore C-box 1 perfmon local box status MSR.
4658 @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)
4659 @param EAX Lower 32-bits of MSR value.
4660 @param EDX Upper 32-bits of MSR value.
4662 <b>Example usage</b>
4666 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
4667 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);
4669 @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
4671 #define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81
4674 Package. Uncore C-box 1 perfmon local box overflow control MSR.
4676 @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)
4677 @param EAX Lower 32-bits of MSR value.
4678 @param EDX Upper 32-bits of MSR value.
4680 <b>Example usage</b>
4684 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
4685 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);
4687 @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.
4689 #define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82
4692 Package. Uncore C-box 1 perfmon event select MSR.
4694 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)
4695 @param EAX Lower 32-bits of MSR value.
4696 @param EDX Upper 32-bits of MSR value.
4698 <b>Example usage</b>
4702 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
4703 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);
4705 @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.
4707 #define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90
4710 Package. Uncore C-box 1 perfmon counter MSR.
4712 @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)
4713 @param EAX Lower 32-bits of MSR value.
4714 @param EDX Upper 32-bits of MSR value.
4716 <b>Example usage</b>
4720 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
4721 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);
4723 @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
4725 #define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91
4728 Package. Uncore C-box 1 perfmon event select MSR.
4730 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)
4731 @param EAX Lower 32-bits of MSR value.
4732 @param EDX Upper 32-bits of MSR value.
4734 <b>Example usage</b>
4738 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
4739 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);
4741 @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.
4743 #define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92
4746 Package. Uncore C-box 1 perfmon counter MSR.
4748 @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)
4749 @param EAX Lower 32-bits of MSR value.
4750 @param EDX Upper 32-bits of MSR value.
4752 <b>Example usage</b>
4756 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
4757 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);
4759 @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
4761 #define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93
4764 Package. Uncore C-box 1 perfmon event select MSR.
4766 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)
4767 @param EAX Lower 32-bits of MSR value.
4768 @param EDX Upper 32-bits of MSR value.
4770 <b>Example usage</b>
4774 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
4775 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);
4777 @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.
4779 #define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94
4782 Package. Uncore C-box 1 perfmon counter MSR.
4784 @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)
4785 @param EAX Lower 32-bits of MSR value.
4786 @param EDX Upper 32-bits of MSR value.
4788 <b>Example usage</b>
4792 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
4793 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);
4795 @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
4797 #define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95
4800 Package. Uncore C-box 1 perfmon event select MSR.
4802 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)
4803 @param EAX Lower 32-bits of MSR value.
4804 @param EDX Upper 32-bits of MSR value.
4806 <b>Example usage</b>
4810 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
4811 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);
4813 @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.
4815 #define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96
4818 Package. Uncore C-box 1 perfmon counter MSR.
4820 @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)
4821 @param EAX Lower 32-bits of MSR value.
4822 @param EDX Upper 32-bits of MSR value.
4824 <b>Example usage</b>
4828 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
4829 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);
4831 @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
4833 #define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97
4836 Package. Uncore C-box 1 perfmon event select MSR.
4838 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)
4839 @param EAX Lower 32-bits of MSR value.
4840 @param EDX Upper 32-bits of MSR value.
4842 <b>Example usage</b>
4846 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
4847 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);
4849 @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.
4851 #define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98
4854 Package. Uncore C-box 1 perfmon counter MSR.
4856 @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)
4857 @param EAX Lower 32-bits of MSR value.
4858 @param EDX Upper 32-bits of MSR value.
4860 <b>Example usage</b>
4864 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
4865 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);
4867 @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.
4869 #define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99
4872 Package. Uncore C-box 1 perfmon event select MSR.
4874 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)
4875 @param EAX Lower 32-bits of MSR value.
4876 @param EDX Upper 32-bits of MSR value.
4878 <b>Example usage</b>
4882 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
4883 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);
4885 @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.
4887 #define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A
4890 Package. Uncore C-box 1 perfmon counter MSR.
4892 @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)
4893 @param EAX Lower 32-bits of MSR value.
4894 @param EDX Upper 32-bits of MSR value.
4896 <b>Example usage</b>
4900 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
4901 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);
4903 @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.
4905 #define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B
4908 Package. Uncore C-box 5 perfmon local box control MSR.
4910 @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)
4911 @param EAX Lower 32-bits of MSR value.
4912 @param EDX Upper 32-bits of MSR value.
4914 <b>Example usage</b>
4918 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
4919 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);
4921 @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.
4923 #define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0
4926 Package. Uncore C-box 5 perfmon local box status MSR.
4928 @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)
4929 @param EAX Lower 32-bits of MSR value.
4930 @param EDX Upper 32-bits of MSR value.
4932 <b>Example usage</b>
4936 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
4937 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);
4939 @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
4941 #define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1
4944 Package. Uncore C-box 5 perfmon local box overflow control MSR.
4946 @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)
4947 @param EAX Lower 32-bits of MSR value.
4948 @param EDX Upper 32-bits of MSR value.
4950 <b>Example usage</b>
4954 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
4955 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);
4957 @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.
4959 #define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2
4962 Package. Uncore C-box 5 perfmon event select MSR.
4964 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)
4965 @param EAX Lower 32-bits of MSR value.
4966 @param EDX Upper 32-bits of MSR value.
4968 <b>Example usage</b>
4972 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
4973 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);
4975 @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.
4977 #define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0
4980 Package. Uncore C-box 5 perfmon counter MSR.
4982 @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)
4983 @param EAX Lower 32-bits of MSR value.
4984 @param EDX Upper 32-bits of MSR value.
4986 <b>Example usage</b>
4990 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
4991 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);
4993 @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
4995 #define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1
4998 Package. Uncore C-box 5 perfmon event select MSR.
5000 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)
5001 @param EAX Lower 32-bits of MSR value.
5002 @param EDX Upper 32-bits of MSR value.
5004 <b>Example usage</b>
5008 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
5009 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);
5011 @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.
5013 #define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2
5016 Package. Uncore C-box 5 perfmon counter MSR.
5018 @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)
5019 @param EAX Lower 32-bits of MSR value.
5020 @param EDX Upper 32-bits of MSR value.
5022 <b>Example usage</b>
5026 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
5027 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);
5029 @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
5031 #define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3
5034 Package. Uncore C-box 5 perfmon event select MSR.
5036 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)
5037 @param EAX Lower 32-bits of MSR value.
5038 @param EDX Upper 32-bits of MSR value.
5040 <b>Example usage</b>
5044 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
5045 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);
5047 @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.
5049 #define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4
5052 Package. Uncore C-box 5 perfmon counter MSR.
5054 @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)
5055 @param EAX Lower 32-bits of MSR value.
5056 @param EDX Upper 32-bits of MSR value.
5058 <b>Example usage</b>
5062 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
5063 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);
5065 @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
5067 #define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5
5070 Package. Uncore C-box 5 perfmon event select MSR.
5072 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)
5073 @param EAX Lower 32-bits of MSR value.
5074 @param EDX Upper 32-bits of MSR value.
5076 <b>Example usage</b>
5080 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
5081 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);
5083 @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.
5085 #define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6
5088 Package. Uncore C-box 5 perfmon counter MSR.
5090 @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)
5091 @param EAX Lower 32-bits of MSR value.
5092 @param EDX Upper 32-bits of MSR value.
5094 <b>Example usage</b>
5098 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
5099 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);
5101 @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
5103 #define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7
5106 Package. Uncore C-box 5 perfmon event select MSR.
5108 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)
5109 @param EAX Lower 32-bits of MSR value.
5110 @param EDX Upper 32-bits of MSR value.
5112 <b>Example usage</b>
5116 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
5117 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);
5119 @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.
5121 #define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8
5124 Package. Uncore C-box 5 perfmon counter MSR.
5126 @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)
5127 @param EAX Lower 32-bits of MSR value.
5128 @param EDX Upper 32-bits of MSR value.
5130 <b>Example usage</b>
5134 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
5135 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);
5137 @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.
5139 #define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9
5142 Package. Uncore C-box 5 perfmon event select MSR.
5144 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)
5145 @param EAX Lower 32-bits of MSR value.
5146 @param EDX Upper 32-bits of MSR value.
5148 <b>Example usage</b>
5152 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
5153 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);
5155 @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.
5157 #define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA
5160 Package. Uncore C-box 5 perfmon counter MSR.
5162 @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)
5163 @param EAX Lower 32-bits of MSR value.
5164 @param EDX Upper 32-bits of MSR value.
5166 <b>Example usage</b>
5170 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
5171 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);
5173 @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.
5175 #define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB
5178 Package. Uncore C-box 3 perfmon local box control MSR.
5180 @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)
5181 @param EAX Lower 32-bits of MSR value.
5182 @param EDX Upper 32-bits of MSR value.
5184 <b>Example usage</b>
5188 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
5189 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);
5191 @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.
5193 #define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0
5196 Package. Uncore C-box 3 perfmon local box status MSR.
5198 @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)
5199 @param EAX Lower 32-bits of MSR value.
5200 @param EDX Upper 32-bits of MSR value.
5202 <b>Example usage</b>
5206 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
5207 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);
5209 @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
5211 #define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1
5214 Package. Uncore C-box 3 perfmon local box overflow control MSR.
5216 @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)
5217 @param EAX Lower 32-bits of MSR value.
5218 @param EDX Upper 32-bits of MSR value.
5220 <b>Example usage</b>
5224 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
5225 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);
5227 @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.
5229 #define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2
5232 Package. Uncore C-box 3 perfmon event select MSR.
5234 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)
5235 @param EAX Lower 32-bits of MSR value.
5236 @param EDX Upper 32-bits of MSR value.
5238 <b>Example usage</b>
5242 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
5243 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);
5245 @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.
5247 #define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0
5250 Package. Uncore C-box 3 perfmon counter MSR.
5252 @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)
5253 @param EAX Lower 32-bits of MSR value.
5254 @param EDX Upper 32-bits of MSR value.
5256 <b>Example usage</b>
5260 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
5261 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);
5263 @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
5265 #define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1
5268 Package. Uncore C-box 3 perfmon event select MSR.
5270 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)
5271 @param EAX Lower 32-bits of MSR value.
5272 @param EDX Upper 32-bits of MSR value.
5274 <b>Example usage</b>
5278 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
5279 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);
5281 @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.
5283 #define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2
5286 Package. Uncore C-box 3 perfmon counter MSR.
5288 @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)
5289 @param EAX Lower 32-bits of MSR value.
5290 @param EDX Upper 32-bits of MSR value.
5292 <b>Example usage</b>
5296 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
5297 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);
5299 @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
5301 #define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3
5304 Package. Uncore C-box 3 perfmon event select MSR.
5306 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)
5307 @param EAX Lower 32-bits of MSR value.
5308 @param EDX Upper 32-bits of MSR value.
5310 <b>Example usage</b>
5314 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
5315 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);
5317 @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.
5319 #define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4
5322 Package. Uncore C-box 3 perfmon counter MSR.
5324 @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)
5325 @param EAX Lower 32-bits of MSR value.
5326 @param EDX Upper 32-bits of MSR value.
5328 <b>Example usage</b>
5332 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
5333 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);
5335 @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
5337 #define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5
5340 Package. Uncore C-box 3 perfmon event select MSR.
5342 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)
5343 @param EAX Lower 32-bits of MSR value.
5344 @param EDX Upper 32-bits of MSR value.
5346 <b>Example usage</b>
5350 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
5351 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);
5353 @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.
5355 #define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6
5358 Package. Uncore C-box 3 perfmon counter MSR.
5360 @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)
5361 @param EAX Lower 32-bits of MSR value.
5362 @param EDX Upper 32-bits of MSR value.
5364 <b>Example usage</b>
5368 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
5369 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);
5371 @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
5373 #define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7
5376 Package. Uncore C-box 3 perfmon event select MSR.
5378 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)
5379 @param EAX Lower 32-bits of MSR value.
5380 @param EDX Upper 32-bits of MSR value.
5382 <b>Example usage</b>
5386 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
5387 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);
5389 @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.
5391 #define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8
5394 Package. Uncore C-box 3 perfmon counter MSR.
5396 @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)
5397 @param EAX Lower 32-bits of MSR value.
5398 @param EDX Upper 32-bits of MSR value.
5400 <b>Example usage</b>
5404 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
5405 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);
5407 @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.
5409 #define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9
5412 Package. Uncore C-box 3 perfmon event select MSR.
5414 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)
5415 @param EAX Lower 32-bits of MSR value.
5416 @param EDX Upper 32-bits of MSR value.
5418 <b>Example usage</b>
5422 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
5423 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);
5425 @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.
5427 #define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA
5430 Package. Uncore C-box 3 perfmon counter MSR.
5432 @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)
5433 @param EAX Lower 32-bits of MSR value.
5434 @param EDX Upper 32-bits of MSR value.
5436 <b>Example usage</b>
5440 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
5441 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);
5443 @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.
5445 #define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB
5448 Package. Uncore C-box 7 perfmon local box control MSR.
5450 @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)
5451 @param EAX Lower 32-bits of MSR value.
5452 @param EDX Upper 32-bits of MSR value.
5454 <b>Example usage</b>
5458 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
5459 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);
5461 @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.
5463 #define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0
5466 Package. Uncore C-box 7 perfmon local box status MSR.
5468 @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)
5469 @param EAX Lower 32-bits of MSR value.
5470 @param EDX Upper 32-bits of MSR value.
5472 <b>Example usage</b>
5476 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
5477 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);
5479 @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
5481 #define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1
5484 Package. Uncore C-box 7 perfmon local box overflow control MSR.
5486 @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)
5487 @param EAX Lower 32-bits of MSR value.
5488 @param EDX Upper 32-bits of MSR value.
5490 <b>Example usage</b>
5494 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
5495 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);
5497 @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.
5499 #define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2
5502 Package. Uncore C-box 7 perfmon event select MSR.
5504 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)
5505 @param EAX Lower 32-bits of MSR value.
5506 @param EDX Upper 32-bits of MSR value.
5508 <b>Example usage</b>
5512 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
5513 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);
5515 @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.
5517 #define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0
5520 Package. Uncore C-box 7 perfmon counter MSR.
5522 @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)
5523 @param EAX Lower 32-bits of MSR value.
5524 @param EDX Upper 32-bits of MSR value.
5526 <b>Example usage</b>
5530 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
5531 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);
5533 @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
5535 #define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1
5538 Package. Uncore C-box 7 perfmon event select MSR.
5540 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)
5541 @param EAX Lower 32-bits of MSR value.
5542 @param EDX Upper 32-bits of MSR value.
5544 <b>Example usage</b>
5548 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
5549 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);
5551 @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.
5553 #define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2
5556 Package. Uncore C-box 7 perfmon counter MSR.
5558 @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)
5559 @param EAX Lower 32-bits of MSR value.
5560 @param EDX Upper 32-bits of MSR value.
5562 <b>Example usage</b>
5566 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
5567 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);
5569 @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
5571 #define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3
5574 Package. Uncore C-box 7 perfmon event select MSR.
5576 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)
5577 @param EAX Lower 32-bits of MSR value.
5578 @param EDX Upper 32-bits of MSR value.
5580 <b>Example usage</b>
5584 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
5585 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);
5587 @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.
5589 #define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4
5592 Package. Uncore C-box 7 perfmon counter MSR.
5594 @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)
5595 @param EAX Lower 32-bits of MSR value.
5596 @param EDX Upper 32-bits of MSR value.
5598 <b>Example usage</b>
5602 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
5603 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);
5605 @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
5607 #define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5
5610 Package. Uncore C-box 7 perfmon event select MSR.
5612 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)
5613 @param EAX Lower 32-bits of MSR value.
5614 @param EDX Upper 32-bits of MSR value.
5616 <b>Example usage</b>
5620 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
5621 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);
5623 @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.
5625 #define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6
5628 Package. Uncore C-box 7 perfmon counter MSR.
5630 @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)
5631 @param EAX Lower 32-bits of MSR value.
5632 @param EDX Upper 32-bits of MSR value.
5634 <b>Example usage</b>
5638 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
5639 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);
5641 @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
5643 #define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7
5646 Package. Uncore C-box 7 perfmon event select MSR.
5648 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)
5649 @param EAX Lower 32-bits of MSR value.
5650 @param EDX Upper 32-bits of MSR value.
5652 <b>Example usage</b>
5656 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
5657 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);
5659 @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.
5661 #define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8
5664 Package. Uncore C-box 7 perfmon counter MSR.
5666 @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)
5667 @param EAX Lower 32-bits of MSR value.
5668 @param EDX Upper 32-bits of MSR value.
5670 <b>Example usage</b>
5674 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
5675 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);
5677 @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.
5679 #define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9
5682 Package. Uncore C-box 7 perfmon event select MSR.
5684 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)
5685 @param EAX Lower 32-bits of MSR value.
5686 @param EDX Upper 32-bits of MSR value.
5688 <b>Example usage</b>
5692 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
5693 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);
5695 @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.
5697 #define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA
5700 Package. Uncore C-box 7 perfmon counter MSR.
5702 @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)
5703 @param EAX Lower 32-bits of MSR value.
5704 @param EDX Upper 32-bits of MSR value.
5706 <b>Example usage</b>
5710 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
5711 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);
5713 @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.
5715 #define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB
5718 Package. Uncore R-box 0 perfmon local box control MSR.
5720 @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)
5721 @param EAX Lower 32-bits of MSR value.
5722 @param EDX Upper 32-bits of MSR value.
5724 <b>Example usage</b>
5728 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
5729 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);
5731 @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.
5733 #define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00
5736 Package. Uncore R-box 0 perfmon local box status MSR.
5738 @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)
5739 @param EAX Lower 32-bits of MSR value.
5740 @param EDX Upper 32-bits of MSR value.
5742 <b>Example usage</b>
5746 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
5747 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);
5749 @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.
5751 #define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01
5754 Package. Uncore R-box 0 perfmon local box overflow control MSR.
5756 @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)
5757 @param EAX Lower 32-bits of MSR value.
5758 @param EDX Upper 32-bits of MSR value.
5760 <b>Example usage</b>
5764 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
5765 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);
5767 @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.
5769 #define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02
5772 Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
5774 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)
5775 @param EAX Lower 32-bits of MSR value.
5776 @param EDX Upper 32-bits of MSR value.
5778 <b>Example usage</b>
5782 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
5783 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);
5785 @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.
5787 #define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04
5790 Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
5792 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)
5793 @param EAX Lower 32-bits of MSR value.
5794 @param EDX Upper 32-bits of MSR value.
5796 <b>Example usage</b>
5800 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
5801 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);
5803 @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.
5805 #define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05
5808 Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
5810 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)
5811 @param EAX Lower 32-bits of MSR value.
5812 @param EDX Upper 32-bits of MSR value.
5814 <b>Example usage</b>
5818 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
5819 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);
5821 @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.
5823 #define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06
5826 Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
5828 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)
5829 @param EAX Lower 32-bits of MSR value.
5830 @param EDX Upper 32-bits of MSR value.
5832 <b>Example usage</b>
5836 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
5837 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);
5839 @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.
5841 #define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07
5844 Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
5846 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)
5847 @param EAX Lower 32-bits of MSR value.
5848 @param EDX Upper 32-bits of MSR value.
5850 <b>Example usage</b>
5854 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
5855 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);
5857 @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.
5859 #define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08
5862 Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
5864 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)
5865 @param EAX Lower 32-bits of MSR value.
5866 @param EDX Upper 32-bits of MSR value.
5868 <b>Example usage</b>
5872 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
5873 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);
5875 @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.
5877 #define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09
5880 Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
5882 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)
5883 @param EAX Lower 32-bits of MSR value.
5884 @param EDX Upper 32-bits of MSR value.
5886 <b>Example usage</b>
5890 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
5891 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);
5893 @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.
5895 #define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A
5898 Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
5900 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)
5901 @param EAX Lower 32-bits of MSR value.
5902 @param EDX Upper 32-bits of MSR value.
5904 <b>Example usage</b>
5908 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
5909 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);
5911 @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.
5913 #define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B
5916 Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
5918 @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)
5919 @param EAX Lower 32-bits of MSR value.
5920 @param EDX Upper 32-bits of MSR value.
5922 <b>Example usage</b>
5926 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
5927 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);
5929 @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.
5931 #define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C
5934 Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
5936 @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)
5937 @param EAX Lower 32-bits of MSR value.
5938 @param EDX Upper 32-bits of MSR value.
5940 <b>Example usage</b>
5944 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
5945 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);
5947 @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.
5949 #define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D
5952 Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
5954 @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)
5955 @param EAX Lower 32-bits of MSR value.
5956 @param EDX Upper 32-bits of MSR value.
5958 <b>Example usage</b>
5962 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
5963 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);
5965 @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.
5967 #define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E
5970 Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
5972 @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)
5973 @param EAX Lower 32-bits of MSR value.
5974 @param EDX Upper 32-bits of MSR value.
5976 <b>Example usage</b>
5980 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
5981 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);
5983 @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.
5985 #define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F
5988 Package. Uncore R-box 0 perfmon event select MSR.
5990 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)
5991 @param EAX Lower 32-bits of MSR value.
5992 @param EDX Upper 32-bits of MSR value.
5994 <b>Example usage</b>
5998 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
5999 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);
6001 @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.
6003 #define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10
6006 Package. Uncore R-box 0 perfmon counter MSR.
6008 @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)
6009 @param EAX Lower 32-bits of MSR value.
6010 @param EDX Upper 32-bits of MSR value.
6012 <b>Example usage</b>
6016 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
6017 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);
6019 @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.
6021 #define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11
6024 Package. Uncore R-box 0 perfmon event select MSR.
6026 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)
6027 @param EAX Lower 32-bits of MSR value.
6028 @param EDX Upper 32-bits of MSR value.
6030 <b>Example usage</b>
6034 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
6035 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);
6037 @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.
6039 #define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12
6042 Package. Uncore R-box 0 perfmon counter MSR.
6044 @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)
6045 @param EAX Lower 32-bits of MSR value.
6046 @param EDX Upper 32-bits of MSR value.
6048 <b>Example usage</b>
6052 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
6053 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);
6055 @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.
6057 #define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13
6060 Package. Uncore R-box 0 perfmon event select MSR.
6062 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)
6063 @param EAX Lower 32-bits of MSR value.
6064 @param EDX Upper 32-bits of MSR value.
6066 <b>Example usage</b>
6070 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
6071 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);
6073 @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.
6075 #define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14
6078 Package. Uncore R-box 0 perfmon counter MSR.
6080 @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)
6081 @param EAX Lower 32-bits of MSR value.
6082 @param EDX Upper 32-bits of MSR value.
6084 <b>Example usage</b>
6088 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
6089 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);
6091 @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.
6093 #define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15
6096 Package. Uncore R-box 0 perfmon event select MSR.
6098 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)
6099 @param EAX Lower 32-bits of MSR value.
6100 @param EDX Upper 32-bits of MSR value.
6102 <b>Example usage</b>
6106 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
6107 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);
6109 @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.
6111 #define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16
6114 Package. Uncore R-box 0 perfmon counter MSR.
6116 @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)
6117 @param EAX Lower 32-bits of MSR value.
6118 @param EDX Upper 32-bits of MSR value.
6120 <b>Example usage</b>
6124 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
6125 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);
6127 @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.
6129 #define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17
6132 Package. Uncore R-box 0 perfmon event select MSR.
6134 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)
6135 @param EAX Lower 32-bits of MSR value.
6136 @param EDX Upper 32-bits of MSR value.
6138 <b>Example usage</b>
6142 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
6143 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);
6145 @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.
6147 #define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18
6150 Package. Uncore R-box 0 perfmon counter MSR.
6152 @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)
6153 @param EAX Lower 32-bits of MSR value.
6154 @param EDX Upper 32-bits of MSR value.
6156 <b>Example usage</b>
6160 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
6161 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);
6163 @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.
6165 #define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19
6168 Package. Uncore R-box 0 perfmon event select MSR.
6170 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)
6171 @param EAX Lower 32-bits of MSR value.
6172 @param EDX Upper 32-bits of MSR value.
6174 <b>Example usage</b>
6178 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
6179 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);
6181 @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.
6183 #define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A
6186 Package. Uncore R-box 0 perfmon counter MSR.
6188 @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)
6189 @param EAX Lower 32-bits of MSR value.
6190 @param EDX Upper 32-bits of MSR value.
6192 <b>Example usage</b>
6196 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
6197 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);
6199 @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.
6201 #define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B
6204 Package. Uncore R-box 0 perfmon event select MSR.
6206 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)
6207 @param EAX Lower 32-bits of MSR value.
6208 @param EDX Upper 32-bits of MSR value.
6210 <b>Example usage</b>
6214 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
6215 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);
6217 @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.
6219 #define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C
6222 Package. Uncore R-box 0 perfmon counter MSR.
6224 @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)
6225 @param EAX Lower 32-bits of MSR value.
6226 @param EDX Upper 32-bits of MSR value.
6228 <b>Example usage</b>
6232 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
6233 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);
6235 @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.
6237 #define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D
6240 Package. Uncore R-box 0 perfmon event select MSR.
6242 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)
6243 @param EAX Lower 32-bits of MSR value.
6244 @param EDX Upper 32-bits of MSR value.
6246 <b>Example usage</b>
6250 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
6251 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);
6253 @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.
6255 #define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E
6258 Package. Uncore R-box 0 perfmon counter MSR.
6260 @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)
6261 @param EAX Lower 32-bits of MSR value.
6262 @param EDX Upper 32-bits of MSR value.
6264 <b>Example usage</b>
6268 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
6269 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);
6271 @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.
6273 #define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F
6276 Package. Uncore R-box 1 perfmon local box control MSR.
6278 @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)
6279 @param EAX Lower 32-bits of MSR value.
6280 @param EDX Upper 32-bits of MSR value.
6282 <b>Example usage</b>
6286 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
6287 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);
6289 @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.
6291 #define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20
6294 Package. Uncore R-box 1 perfmon local box status MSR.
6296 @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)
6297 @param EAX Lower 32-bits of MSR value.
6298 @param EDX Upper 32-bits of MSR value.
6300 <b>Example usage</b>
6304 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
6305 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);
6307 @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.
6309 #define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21
6312 Package. Uncore R-box 1 perfmon local box overflow control MSR.
6314 @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)
6315 @param EAX Lower 32-bits of MSR value.
6316 @param EDX Upper 32-bits of MSR value.
6318 <b>Example usage</b>
6322 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
6323 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);
6325 @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.
6327 #define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22
6330 Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
6332 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)
6333 @param EAX Lower 32-bits of MSR value.
6334 @param EDX Upper 32-bits of MSR value.
6336 <b>Example usage</b>
6340 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
6341 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);
6343 @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.
6345 #define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24
6348 Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
6350 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)
6351 @param EAX Lower 32-bits of MSR value.
6352 @param EDX Upper 32-bits of MSR value.
6354 <b>Example usage</b>
6358 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
6359 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);
6361 @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.
6363 #define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25
6366 Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
6368 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)
6369 @param EAX Lower 32-bits of MSR value.
6370 @param EDX Upper 32-bits of MSR value.
6372 <b>Example usage</b>
6376 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
6377 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);
6379 @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.
6381 #define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26
6384 Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
6386 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)
6387 @param EAX Lower 32-bits of MSR value.
6388 @param EDX Upper 32-bits of MSR value.
6390 <b>Example usage</b>
6394 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
6395 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);
6397 @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.
6399 #define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27
6402 Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
6404 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)
6405 @param EAX Lower 32-bits of MSR value.
6406 @param EDX Upper 32-bits of MSR value.
6408 <b>Example usage</b>
6412 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
6413 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);
6415 @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.
6417 #define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28
6420 Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
6422 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)
6423 @param EAX Lower 32-bits of MSR value.
6424 @param EDX Upper 32-bits of MSR value.
6426 <b>Example usage</b>
6430 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
6431 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);
6433 @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.
6435 #define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29
6438 Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
6440 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)
6441 @param EAX Lower 32-bits of MSR value.
6442 @param EDX Upper 32-bits of MSR value.
6444 <b>Example usage</b>
6448 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
6449 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);
6451 @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.
6453 #define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A
6456 Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
6458 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)
6459 @param EAX Lower 32-bits of MSR value.
6460 @param EDX Upper 32-bits of MSR value.
6462 <b>Example usage</b>
6466 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
6467 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);
6469 @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.
6471 #define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B
6474 Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
6476 @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)
6477 @param EAX Lower 32-bits of MSR value.
6478 @param EDX Upper 32-bits of MSR value.
6480 <b>Example usage</b>
6484 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
6485 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);
6487 @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.
6489 #define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C
6492 Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
6494 @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)
6495 @param EAX Lower 32-bits of MSR value.
6496 @param EDX Upper 32-bits of MSR value.
6498 <b>Example usage</b>
6502 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
6503 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);
6505 @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.
6507 #define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D
6510 Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
6512 @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)
6513 @param EAX Lower 32-bits of MSR value.
6514 @param EDX Upper 32-bits of MSR value.
6516 <b>Example usage</b>
6520 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
6521 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);
6523 @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.
6525 #define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E
6528 Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
6530 @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)
6531 @param EAX Lower 32-bits of MSR value.
6532 @param EDX Upper 32-bits of MSR value.
6534 <b>Example usage</b>
6538 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
6539 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);
6541 @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.
6543 #define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F
6546 Package. Uncore R-box 1 perfmon event select MSR.
6548 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)
6549 @param EAX Lower 32-bits of MSR value.
6550 @param EDX Upper 32-bits of MSR value.
6552 <b>Example usage</b>
6556 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
6557 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);
6559 @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.
6561 #define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30
6564 Package. Uncore R-box 1 perfmon counter MSR.
6566 @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)
6567 @param EAX Lower 32-bits of MSR value.
6568 @param EDX Upper 32-bits of MSR value.
6570 <b>Example usage</b>
6574 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
6575 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);
6577 @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.
6579 #define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31
6582 Package. Uncore R-box 1 perfmon event select MSR.
6584 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)
6585 @param EAX Lower 32-bits of MSR value.
6586 @param EDX Upper 32-bits of MSR value.
6588 <b>Example usage</b>
6592 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
6593 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);
6595 @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.
6597 #define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32
6600 Package. Uncore R-box 1 perfmon counter MSR.
6602 @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)
6603 @param EAX Lower 32-bits of MSR value.
6604 @param EDX Upper 32-bits of MSR value.
6606 <b>Example usage</b>
6610 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
6611 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);
6613 @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.
6615 #define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33
6618 Package. Uncore R-box 1 perfmon event select MSR.
6620 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)
6621 @param EAX Lower 32-bits of MSR value.
6622 @param EDX Upper 32-bits of MSR value.
6624 <b>Example usage</b>
6628 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
6629 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);
6631 @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.
6633 #define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34
6636 Package. Uncore R-box 1 perfmon counter MSR.
6638 @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)
6639 @param EAX Lower 32-bits of MSR value.
6640 @param EDX Upper 32-bits of MSR value.
6642 <b>Example usage</b>
6646 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
6647 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);
6649 @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.
6651 #define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35
6654 Package. Uncore R-box 1 perfmon event select MSR.
6656 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)
6657 @param EAX Lower 32-bits of MSR value.
6658 @param EDX Upper 32-bits of MSR value.
6660 <b>Example usage</b>
6664 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
6665 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);
6667 @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.
6669 #define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36
6672 Package. Uncore R-box 1 perfmon counter MSR.
6674 @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)
6675 @param EAX Lower 32-bits of MSR value.
6676 @param EDX Upper 32-bits of MSR value.
6678 <b>Example usage</b>
6682 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
6683 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);
6685 @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.
6687 #define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37
6690 Package. Uncore R-box 1 perfmon event select MSR.
6692 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)
6693 @param EAX Lower 32-bits of MSR value.
6694 @param EDX Upper 32-bits of MSR value.
6696 <b>Example usage</b>
6700 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
6701 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);
6703 @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.
6705 #define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38
6708 Package. Uncore R-box 1 perfmon counter MSR.
6710 @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)
6711 @param EAX Lower 32-bits of MSR value.
6712 @param EDX Upper 32-bits of MSR value.
6714 <b>Example usage</b>
6718 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
6719 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);
6721 @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.
6723 #define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39
6726 Package. Uncore R-box 1 perfmon event select MSR.
6728 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)
6729 @param EAX Lower 32-bits of MSR value.
6730 @param EDX Upper 32-bits of MSR value.
6732 <b>Example usage</b>
6736 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
6737 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);
6739 @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.
6741 #define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A
6744 Package. Uncore R-box 1perfmon counter MSR.
6746 @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)
6747 @param EAX Lower 32-bits of MSR value.
6748 @param EDX Upper 32-bits of MSR value.
6750 <b>Example usage</b>
6754 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
6755 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);
6757 @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.
6759 #define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B
6762 Package. Uncore R-box 1 perfmon event select MSR.
6764 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)
6765 @param EAX Lower 32-bits of MSR value.
6766 @param EDX Upper 32-bits of MSR value.
6768 <b>Example usage</b>
6772 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
6773 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);
6775 @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.
6777 #define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C
6780 Package. Uncore R-box 1 perfmon counter MSR.
6782 @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)
6783 @param EAX Lower 32-bits of MSR value.
6784 @param EDX Upper 32-bits of MSR value.
6786 <b>Example usage</b>
6790 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
6791 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);
6793 @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.
6795 #define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D
6798 Package. Uncore R-box 1 perfmon event select MSR.
6800 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)
6801 @param EAX Lower 32-bits of MSR value.
6802 @param EDX Upper 32-bits of MSR value.
6804 <b>Example usage</b>
6808 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
6809 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);
6811 @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.
6813 #define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E
6816 Package. Uncore R-box 1 perfmon counter MSR.
6818 @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)
6819 @param EAX Lower 32-bits of MSR value.
6820 @param EDX Upper 32-bits of MSR value.
6822 <b>Example usage</b>
6826 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
6827 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);
6829 @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.
6831 #define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F
6834 Package. Uncore B-box 0 perfmon local box match MSR.
6836 @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)
6837 @param EAX Lower 32-bits of MSR value.
6838 @param EDX Upper 32-bits of MSR value.
6840 <b>Example usage</b>
6844 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
6845 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);
6847 @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.
6849 #define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45
6852 Package. Uncore B-box 0 perfmon local box mask MSR.
6854 @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)
6855 @param EAX Lower 32-bits of MSR value.
6856 @param EDX Upper 32-bits of MSR value.
6858 <b>Example usage</b>
6862 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
6863 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);
6865 @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.
6867 #define MSR_NEHALEM_B0_PMON_MASK 0x00000E46
6870 Package. Uncore S-box 0 perfmon local box match MSR.
6872 @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)
6873 @param EAX Lower 32-bits of MSR value.
6874 @param EDX Upper 32-bits of MSR value.
6876 <b>Example usage</b>
6880 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
6881 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);
6883 @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.
6885 #define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49
6888 Package. Uncore S-box 0 perfmon local box mask MSR.
6890 @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)
6891 @param EAX Lower 32-bits of MSR value.
6892 @param EDX Upper 32-bits of MSR value.
6894 <b>Example usage</b>
6898 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
6899 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);
6901 @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.
6903 #define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A
6906 Package. Uncore B-box 1 perfmon local box match MSR.
6908 @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)
6909 @param EAX Lower 32-bits of MSR value.
6910 @param EDX Upper 32-bits of MSR value.
6912 <b>Example usage</b>
6916 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
6917 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);
6919 @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.
6921 #define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D
6924 Package. Uncore B-box 1 perfmon local box mask MSR.
6926 @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)
6927 @param EAX Lower 32-bits of MSR value.
6928 @param EDX Upper 32-bits of MSR value.
6930 <b>Example usage</b>
6934 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
6935 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);
6937 @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.
6939 #define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E
6942 Package. Uncore M-box 0 perfmon local box address match/mask config MSR.
6944 @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)
6945 @param EAX Lower 32-bits of MSR value.
6946 @param EDX Upper 32-bits of MSR value.
6948 <b>Example usage</b>
6952 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
6953 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);
6955 @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.
6957 #define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54
6960 Package. Uncore M-box 0 perfmon local box address match MSR.
6962 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)
6963 @param EAX Lower 32-bits of MSR value.
6964 @param EDX Upper 32-bits of MSR value.
6966 <b>Example usage</b>
6970 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
6971 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);
6973 @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.
6975 #define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55
6978 Package. Uncore M-box 0 perfmon local box address mask MSR.
6980 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)
6981 @param EAX Lower 32-bits of MSR value.
6982 @param EDX Upper 32-bits of MSR value.
6984 <b>Example usage</b>
6988 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
6989 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);
6991 @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.
6993 #define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56
6996 Package. Uncore S-box 1 perfmon local box match MSR.
6998 @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)
6999 @param EAX Lower 32-bits of MSR value.
7000 @param EDX Upper 32-bits of MSR value.
7002 <b>Example usage</b>
7006 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
7007 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);
7009 @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.
7011 #define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59
7014 Package. Uncore S-box 1 perfmon local box mask MSR.
7016 @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)
7017 @param EAX Lower 32-bits of MSR value.
7018 @param EDX Upper 32-bits of MSR value.
7020 <b>Example usage</b>
7024 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
7025 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);
7027 @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.
7029 #define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A
7032 Package. Uncore M-box 1 perfmon local box address match/mask config MSR.
7034 @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)
7035 @param EAX Lower 32-bits of MSR value.
7036 @param EDX Upper 32-bits of MSR value.
7038 <b>Example usage</b>
7042 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
7043 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);
7045 @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.
7047 #define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C
7050 Package. Uncore M-box 1 perfmon local box address match MSR.
7052 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)
7053 @param EAX Lower 32-bits of MSR value.
7054 @param EDX Upper 32-bits of MSR value.
7056 <b>Example usage</b>
7060 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
7061 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);
7063 @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.
7065 #define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D
7068 Package. Uncore M-box 1 perfmon local box address mask MSR.
7070 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)
7071 @param EAX Lower 32-bits of MSR value.
7072 @param EDX Upper 32-bits of MSR value.
7074 <b>Example usage</b>
7078 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
7079 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);
7081 @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.
7083 #define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E