2 MSR Definitions for Pentium M Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __PENTIUM_M_MSR_H__
19 #define __PENTIUM_M_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Pentium M Processors?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x0D \
40 See Section 2.22, "MSRs in Pentium Processors.".
42 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
43 @param EAX Lower 32-bits of MSR value.
44 @param EDX Upper 32-bits of MSR value.
50 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
51 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
53 @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
55 #define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
59 See Section 2.22, "MSRs in Pentium Processors.".
61 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
62 @param EAX Lower 32-bits of MSR value.
63 @param EDX Upper 32-bits of MSR value.
69 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
70 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
72 @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
74 #define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
78 Processor Hard Power-On Configuration (R/W) Enables and disables processor
79 features. (R) Indicates current processor configuration.
81 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
82 @param EAX Lower 32-bits of MSR value.
83 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
84 @param EDX Upper 32-bits of MSR value.
85 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
89 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
91 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
92 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
94 @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
96 #define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
99 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
103 /// Individual bit fields
108 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
109 /// Pentium M processor.
111 UINT32 DataErrorCheckingEnable
:1;
113 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
114 /// the Pentium M processor.
116 UINT32 ResponseErrorCheckingEnable
:1;
118 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
121 UINT32 MCERR_DriveEnable
:1;
123 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
126 UINT32 AddressParityEnable
:1;
129 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
130 /// the Pentium M processor.
132 UINT32 BINIT_DriverEnable
:1;
134 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
136 UINT32 OutputTriStateEnable
:1;
138 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
140 UINT32 ExecuteBIST
:1;
142 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
143 /// Always 0 on the Pentium M processor.
145 UINT32 MCERR_ObservationEnabled
:1;
148 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
149 /// Always 0 on the Pentium M processor.
151 UINT32 BINIT_ObservationEnabled
:1;
154 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
155 /// Always 0 on the Pentium M processor.
157 UINT32 ResetVector
:1;
160 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
163 UINT32 APICClusterID
:2;
165 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
166 /// 0 on the Pentium M processor.
168 UINT32 SystemBusFrequency
:1;
171 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
174 UINT32 SymmetricArbitrationID
:2;
176 /// [Bits 26:22] Clock Frequency Ratio (R/O).
178 UINT32 ClockFrequencyRatio
:5;
183 /// All bit fields as a 32-bit value
187 /// All bit fields as a 64-bit value
190 } MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
;
194 Last Branch Record n (R/W) One of 8 last branch record registers on the last
195 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
196 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
197 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
200 @param ECX MSR_PENTIUM_M_LASTBRANCH_n
201 @param EAX Lower 32-bits of MSR value.
202 @param EDX Upper 32-bits of MSR value.
208 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
209 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
211 @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
212 MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
213 MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
214 MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
215 MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
216 MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
217 MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
218 MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
221 #define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
222 #define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
223 #define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
224 #define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
225 #define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
226 #define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
227 #define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
228 #define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
235 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
236 @param EAX Lower 32-bits of MSR value.
237 @param EDX Upper 32-bits of MSR value.
243 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
244 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
246 @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
248 #define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
254 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
255 @param EAX Lower 32-bits of MSR value.
256 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
257 @param EDX Upper 32-bits of MSR value.
258 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
262 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
264 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
265 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
267 @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
269 #define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
272 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
276 /// Individual bit fields
280 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
281 /// Indicates if the L2 is hardware-disabled.
283 UINT32 L2HardwareEnabled
:1;
286 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
287 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled
288 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on
289 /// the cache data bus is always enabled.
291 UINT32 ECCCheckEnable
:1;
294 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
295 /// Disabled (default) Until this bit is set the processor will not
296 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
301 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
303 UINT32 L2NotPresent
:1;
308 /// All bit fields as a 32-bit value
312 /// All bit fields as a 64-bit value
315 } MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
;
321 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
322 @param EAX Lower 32-bits of MSR value.
323 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
324 @param EDX Upper 32-bits of MSR value.
325 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
329 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
331 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
332 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
334 @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
336 #define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
339 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
343 /// Individual bit fields
348 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
349 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
350 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
351 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
352 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
359 /// All bit fields as a 32-bit value
363 /// All bit fields as a 64-bit value
366 } MSR_PENTIUM_M_THERM2_CTL_REGISTER
;
370 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
371 functions to be enabled and disabled.
373 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
374 @param EAX Lower 32-bits of MSR value.
375 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
376 @param EDX Upper 32-bits of MSR value.
377 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
381 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
383 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
384 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
386 @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
388 #define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
391 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
395 /// Individual bit fields
400 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
401 /// this bit enables the thermal control circuit (TCC) portion of the
402 /// Intel Thermal Monitor feature. This allows processor clocks to be
403 /// automatically modulated based on the processor's thermal sensor
404 /// operation. 0 = Disabled (default). The automatic thermal control
405 /// circuit enable bit determines if the thermal control circuit (TCC)
406 /// will be activated when the processor's internal thermal sensor
407 /// determines the processor is about to exceed its maximum operating
408 /// temperature. When the TCC is activated and TM1 is enabled, the
409 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable
410 /// this feature. The bit should not be confused with the on-demand
411 /// thermal control circuit enable bit.
413 UINT32 AutomaticThermalControlCircuit
:1;
416 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
417 /// monitoring enabled 0 = Performance monitoring disabled.
419 UINT32 PerformanceMonitoring
:1;
422 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
423 /// processor to indicate a pending break event within the processor 0 =
424 /// Indicates compatible FERR# signaling behavior This bit must be set to
425 /// 1 to support XAPIC interrupt model usage.
426 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
427 /// support branch trace storage (BTS) 0 = BTS is supported
431 /// [Bit 11] Branch Trace Storage Unavailable (RO)
432 /// 1 = Processor doesn't support branch trace storage (BTS)
433 /// 0 = BTS is supported
437 /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
438 /// Processor does not support processor event based sampling (PEBS); 0 =
439 /// PEBS is supported. The Pentium M processor does not support PEBS.
444 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
445 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
446 /// processor, this bit may be configured to be read-only.
451 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
452 /// disabled. xTPR messages are optional messages that allow the processor
453 /// to inform the chipset of its priority. The default is processor
456 UINT32 xTPR_Message_Disable
:1;
461 /// All bit fields as a 32-bit value
465 /// All bit fields as a 64-bit value
468 } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
;
472 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
473 to the MSR containing the most recent branch record. See also: -
474 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
475 and Exception Recording (Pentium M Processors)".
477 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
478 @param EAX Lower 32-bits of MSR value.
479 @param EDX Upper 32-bits of MSR value.
485 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
486 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
488 @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
490 #define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
494 Debug Control (R/W) Controls how several debug features are used. Bit
495 definitions are discussed in the referenced section. See Section 17.15,
496 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
498 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
499 @param EAX Lower 32-bits of MSR value.
500 @param EDX Upper 32-bits of MSR value.
506 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
507 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
509 @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
511 #define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
515 Last Exception Record To Linear IP (R) This area contains a pointer to the
516 target of the last branch instruction that the processor executed prior to
517 the last exception that was generated or the last interrupt that was
518 handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording
519 (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception
522 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
523 @param EAX Lower 32-bits of MSR value.
524 @param EDX Upper 32-bits of MSR value.
530 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
532 @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
534 #define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
538 Last Exception Record From Linear IP (R) Contains a pointer to the last
539 branch instruction that the processor executed prior to the last exception
540 that was generated or the last interrupt that was handled. See Section
541 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
542 Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".
544 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
545 @param EAX Lower 32-bits of MSR value.
546 @param EDX Upper 32-bits of MSR value.
552 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
554 @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
556 #define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
560 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
562 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
563 @param EAX Lower 32-bits of MSR value.
564 @param EDX Upper 32-bits of MSR value.
570 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
571 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
573 @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
575 #define MSR_PENTIUM_M_MC4_CTL 0x0000040C
579 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
581 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
582 @param EAX Lower 32-bits of MSR value.
583 @param EDX Upper 32-bits of MSR value.
589 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
590 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
592 @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
594 #define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
598 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
599 either not implemented or contains no address if the ADDRV flag in the
600 MSR_MC4_STATUS register is clear. When not implemented in the processor, all
601 reads and writes to this MSR will cause a general-protection exception.
603 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
604 @param EAX Lower 32-bits of MSR value.
605 @param EDX Upper 32-bits of MSR value.
611 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
612 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
614 @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
616 #define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
620 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
622 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
623 @param EAX Lower 32-bits of MSR value.
624 @param EDX Upper 32-bits of MSR value.
630 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
631 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
633 @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
635 #define MSR_PENTIUM_M_MC3_CTL 0x00000410
639 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
641 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
642 @param EAX Lower 32-bits of MSR value.
643 @param EDX Upper 32-bits of MSR value.
649 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
650 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
652 @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
654 #define MSR_PENTIUM_M_MC3_STATUS 0x00000411
658 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
659 either not implemented or contains no address if the ADDRV flag in the
660 MSR_MC3_STATUS register is clear. When not implemented in the processor, all
661 reads and writes to this MSR will cause a general-protection exception.
663 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
664 @param EAX Lower 32-bits of MSR value.
665 @param EDX Upper 32-bits of MSR value.
671 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
672 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
674 @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
676 #define MSR_PENTIUM_M_MC3_ADDR 0x00000412