2 MSR Definitions for Intel(R) Xeon(R) Processor D product Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __XEON_D_MSR_H__
19 #define __XEON_D_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel(R) Xeon(R) Processor D product Family?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x4F || \
36 DisplayModel == 0x56 \
41 Package. Protected Processor Inventory Number Enable Control (R/W).
43 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)
44 @param EAX Lower 32-bits of MSR value.
45 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
46 @param EDX Upper 32-bits of MSR value.
47 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
51 MSR_XEON_D_PPIN_CTL_REGISTER Msr;
53 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
54 AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
56 @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
58 #define MSR_XEON_D_PPIN_CTL 0x0000004E
61 MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL
65 /// Individual bit fields
69 /// [Bit 0] LockOut (R/WO) See Table 2-25.
73 /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
80 /// All bit fields as a 32-bit value
84 /// All bit fields as a 64-bit value
87 } MSR_XEON_D_PPIN_CTL_REGISTER
;
91 Package. Protected Processor Inventory Number (R/O). Protected Processor
92 Inventory Number (R/O) See Table 2-25.
94 @param ECX MSR_XEON_D_PPIN (0x0000004F)
95 @param EAX Lower 32-bits of MSR value.
96 @param EDX Upper 32-bits of MSR value.
102 Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
104 @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.
106 #define MSR_XEON_D_PPIN 0x0000004F
110 Package. See http://biosbits.org.
112 @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)
113 @param EAX Lower 32-bits of MSR value.
114 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
115 @param EDX Upper 32-bits of MSR value.
116 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
120 MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;
122 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
123 AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
125 @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
127 #define MSR_XEON_D_PLATFORM_INFO 0x000000CE
130 MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO
134 /// Individual bit fields
139 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
141 UINT32 MaximumNonTurboRatio
:8;
144 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
149 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
154 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
159 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
165 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
167 UINT32 MaximumEfficiencyRatio
:8;
171 /// All bit fields as a 64-bit value
174 } MSR_XEON_D_PLATFORM_INFO_REGISTER
;
178 Core. C-State Configuration Control (R/W) Note: C-state values are processor
179 specific C-state code names, unrelated to MWAIT extension C-state parameters
180 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
182 @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)
183 @param EAX Lower 32-bits of MSR value.
184 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
185 @param EDX Upper 32-bits of MSR value.
186 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
190 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
192 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);
193 AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
195 @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
197 #define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2
200 MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL
204 /// Individual bit fields
208 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
209 /// processor-specific C-state code name (consuming the least power) for
210 /// the package. The default is set as factory-configured package C-state
211 /// limit. The following C-state code name encodings are supported: 000b:
212 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
213 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
214 /// supported by the processor are available.
219 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
224 /// [Bit 15] CFG Lock (R/WO).
228 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
229 /// will convert HALT or MWAT(C1) to MWAIT(C6).
231 UINT32 CStateConversion
:1;
234 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
236 UINT32 C3AutoDemotion
:1;
238 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
240 UINT32 C1AutoDemotion
:1;
242 /// [Bit 27] Enable C3 Undemotion (R/W).
244 UINT32 C3Undemotion
:1;
246 /// [Bit 28] Enable C1 Undemotion (R/W).
248 UINT32 C1Undemotion
:1;
250 /// [Bit 29] Package C State Demotion Enable (R/W).
252 UINT32 CStateDemotion
:1;
254 /// [Bit 30] Package C State UnDemotion Enable (R/W).
256 UINT32 CStateUndemotion
:1;
261 /// All bit fields as a 32-bit value
265 /// All bit fields as a 64-bit value
268 } MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
;
272 Thread. Global Machine Check Capability (R/O).
274 @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)
275 @param EAX Lower 32-bits of MSR value.
276 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
277 @param EDX Upper 32-bits of MSR value.
278 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
282 MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;
284 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);
286 @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
288 #define MSR_XEON_D_IA32_MCG_CAP 0x00000179
291 MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP
295 /// Individual bit fields
299 /// [Bits 7:0] Count.
303 /// [Bit 8] MCG_CTL_P.
307 /// [Bit 9] MCG_EXT_P.
311 /// [Bit 10] MCP_CMCI_P.
315 /// [Bit 11] MCG_TES_P.
320 /// [Bits 23:16] MCG_EXT_CNT.
322 UINT32 MCG_EXT_CNT
:8;
324 /// [Bit 24] MCG_SER_P.
328 /// [Bit 25] MCG_EM_P.
332 /// [Bit 26] MCG_ELOG_P.
339 /// All bit fields as a 32-bit value
343 /// All bit fields as a 64-bit value
346 } MSR_XEON_D_IA32_MCG_CAP_REGISTER
;
350 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
351 Enhancement. Accessible only while in SMM.
353 @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)
354 @param EAX Lower 32-bits of MSR value.
355 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
356 @param EDX Upper 32-bits of MSR value.
357 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
361 MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;
363 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);
364 AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);
366 @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
368 #define MSR_XEON_D_SMM_MCA_CAP 0x0000017D
371 MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP
375 /// Individual bit fields
381 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
382 /// SMM code access restriction is supported and a host-space interface
383 /// available to SMM handler.
385 UINT32 SMM_Code_Access_Chk
:1;
387 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
388 /// SMM long flow indicator is supported and a host-space interface
389 /// available to SMM handler.
391 UINT32 Long_Flow_Indication
:1;
395 /// All bit fields as a 64-bit value
398 } MSR_XEON_D_SMM_MCA_CAP_REGISTER
;
404 @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)
405 @param EAX Lower 32-bits of MSR value.
406 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
407 @param EDX Upper 32-bits of MSR value.
408 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
412 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;
414 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);
415 AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);
417 @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
419 #define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2
422 MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET
426 /// Individual bit fields
431 /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
433 UINT32 TemperatureTarget
:8;
435 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
437 UINT32 TCCActivationOffset
:4;
442 /// All bit fields as a 32-bit value
446 /// All bit fields as a 64-bit value
449 } MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
;
453 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
454 RW if MSR_PLATFORM_INFO.[28] = 1.
456 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)
457 @param EAX Lower 32-bits of MSR value.
458 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
459 @param EDX Upper 32-bits of MSR value.
460 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
464 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;
466 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);
468 @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
470 #define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD
473 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT
477 /// Individual bit fields
481 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.
485 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.
489 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.
493 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.
497 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.
501 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.
505 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.
509 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.
514 /// All bit fields as a 64-bit value
517 } MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
;
521 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
522 RW if MSR_PLATFORM_INFO.[28] = 1.
524 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)
525 @param EAX Lower 32-bits of MSR value.
526 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
527 @param EDX Upper 32-bits of MSR value.
528 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
532 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;
534 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);
536 @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
538 #define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE
541 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1
545 /// Individual bit fields
549 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.
553 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.
557 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.
561 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.
565 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.
569 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.
573 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.
577 /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.
582 /// All bit fields as a 64-bit value
585 } MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
;
589 Package. Unit Multipliers used in RAPL Interfaces (R/O).
591 @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)
592 @param EAX Lower 32-bits of MSR value.
593 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
594 @param EDX Upper 32-bits of MSR value.
595 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
599 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;
601 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);
603 @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
605 #define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606
608 MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT
612 /// Individual bit fields
616 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
621 /// [Bits 12:8] Package. Energy Status Units Energy related information
622 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
623 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
626 UINT32 EnergyStatusUnits
:5;
629 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
637 /// All bit fields as a 32-bit value
641 /// All bit fields as a 64-bit value
644 } MSR_XEON_D_RAPL_POWER_UNIT_REGISTER
;
648 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
651 @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)
652 @param EAX Lower 32-bits of MSR value.
653 @param EDX Upper 32-bits of MSR value.
659 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);
660 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);
662 @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
664 #define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618
668 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
670 @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)
671 @param EAX Lower 32-bits of MSR value.
672 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
673 @param EDX Upper 32-bits of MSR value.
674 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
678 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;
680 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
682 @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
684 #define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619
687 MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS
691 /// Individual bit fields
695 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
696 /// to enable DRAM RAPL mode 0 (Direct VR).
702 /// All bit fields as a 32-bit value
706 /// All bit fields as a 64-bit value
709 } MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER
;
713 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
716 @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)
717 @param EAX Lower 32-bits of MSR value.
718 @param EDX Upper 32-bits of MSR value.
724 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);
726 @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
728 #define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B
732 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
734 @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)
735 @param EAX Lower 32-bits of MSR value.
736 @param EDX Upper 32-bits of MSR value.
742 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);
743 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);
745 @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
747 #define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C
751 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
752 fields represent the widest possible range of uncore frequencies. Writing to
753 these fields allows software to control the minimum and the maximum
754 frequency that hardware will select.
756 @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)
757 @param EAX Lower 32-bits of MSR value.
758 Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
759 @param EDX Upper 32-bits of MSR value.
760 Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
764 MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
766 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);
767 AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
770 #define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620
773 MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT
777 /// Individual bit fields
781 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
787 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
788 /// possible ratio of the LLC/Ring.
795 /// All bit fields as a 32-bit value
799 /// All bit fields as a 64-bit value
802 } MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER
;
805 Package. Reserved (R/O) Reads return 0.
807 @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)
808 @param EAX Lower 32-bits of MSR value.
809 @param EDX Upper 32-bits of MSR value.
815 Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);
817 @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
819 #define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639
823 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
824 refers to processor core frequency).
826 @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)
827 @param EAX Lower 32-bits of MSR value.
828 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
829 @param EDX Upper 32-bits of MSR value.
830 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
834 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
836 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);
837 AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
839 @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
841 #define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690
844 MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS
848 /// Individual bit fields
852 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
853 /// reduced below the operating system request due to assertion of
854 /// external PROCHOT.
856 UINT32 PROCHOT_Status
:1;
858 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
859 /// operating system request due to a thermal event.
861 UINT32 ThermalStatus
:1;
863 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
864 /// reduced below the operating system request due to PBM limit.
866 UINT32 PowerBudgetManagementStatus
:1;
868 /// [Bit 3] Platform Configuration Services Status (R0) When set,
869 /// frequency is reduced below the operating system request due to PCS
872 UINT32 PlatformConfigurationServicesStatus
:1;
875 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
876 /// When set, frequency is reduced below the operating system request
877 /// because the processor has detected that utilization is low.
879 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
881 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
882 /// below the operating system request due to a thermal alert from the
883 /// Voltage Regulator.
885 UINT32 VRThermAlertStatus
:1;
888 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
889 /// reduced below the operating system request due to electrical design
890 /// point constraints (e.g. maximum electrical current consumption).
892 UINT32 ElectricalDesignPointStatus
:1;
895 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
896 /// below the operating system request due to Multi-Core Turbo limits.
898 UINT32 MultiCoreTurboStatus
:1;
901 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
902 /// below max non-turbo P1.
904 UINT32 FrequencyP1Status
:1;
906 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
907 /// set, frequency is reduced below max n-core turbo frequency.
909 UINT32 TurboFrequencyLimitingStatus
:1;
911 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
912 /// reduced below the operating system request.
914 UINT32 FrequencyLimitingStatus
:1;
916 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
917 /// has asserted since the log bit was last cleared. This log bit will
918 /// remain set until cleared by software writing 0.
920 UINT32 PROCHOT_Log
:1;
922 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
923 /// has asserted since the log bit was last cleared. This log bit will
924 /// remain set until cleared by software writing 0.
928 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
929 /// Status bit has asserted since the log bit was last cleared. This log
930 /// bit will remain set until cleared by software writing 0.
932 UINT32 PowerBudgetManagementLog
:1;
934 /// [Bit 19] Platform Configuration Services Log When set, indicates that
935 /// the PCS Status bit has asserted since the log bit was last cleared.
936 /// This log bit will remain set until cleared by software writing 0.
938 UINT32 PlatformConfigurationServicesLog
:1;
941 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
942 /// indicates that the AUBFC Status bit has asserted since the log bit was
943 /// last cleared. This log bit will remain set until cleared by software
946 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
948 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
949 /// Alert Status bit has asserted since the log bit was last cleared. This
950 /// log bit will remain set until cleared by software writing 0.
952 UINT32 VRThermAlertLog
:1;
955 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
956 /// Status bit has asserted since the log bit was last cleared. This log
957 /// bit will remain set until cleared by software writing 0.
959 UINT32 ElectricalDesignPointLog
:1;
962 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
963 /// Turbo Status bit has asserted since the log bit was last cleared. This
964 /// log bit will remain set until cleared by software writing 0.
966 UINT32 MultiCoreTurboLog
:1;
969 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
970 /// Frequency P1 Status bit has asserted since the log bit was last
971 /// cleared. This log bit will remain set until cleared by software
974 UINT32 CoreFrequencyP1Log
:1;
976 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
977 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
978 /// has asserted since the log bit was last cleared. This log bit will
979 /// remain set until cleared by software writing 0.
981 UINT32 TurboFrequencyLimitingLog
:1;
983 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
984 /// Frequency Limiting Status bit has asserted since the log bit was last
985 /// cleared. This log bit will remain set until cleared by software
988 UINT32 CoreFrequencyLimitingLog
:1;
992 /// All bit fields as a 32-bit value
996 /// All bit fields as a 64-bit value
999 } MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
;
1003 THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,
1004 ECX=0):EBX.RDT-M[bit 12] = 1.
1006 @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)
1007 @param EAX Lower 32-bits of MSR value.
1008 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
1009 @param EDX Upper 32-bits of MSR value.
1010 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
1012 <b>Example usage</b>
1014 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;
1016 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);
1017 AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);
1019 @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
1021 #define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D
1024 MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL
1028 /// Individual bit fields
1032 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3
1033 /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:
1034 /// Local memory bandwidth monitoring All other encoding reserved.
1037 UINT32 Reserved1
:24;
1039 /// [Bits 41:32] RMID (RW).
1042 UINT32 Reserved2
:22;
1045 /// All bit fields as a 64-bit value
1048 } MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
;
1052 THREAD. Resource Association Register (R/W).
1054 @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)
1055 @param EAX Lower 32-bits of MSR value.
1056 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
1057 @param EDX Upper 32-bits of MSR value.
1058 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
1060 <b>Example usage</b>
1062 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;
1064 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);
1065 AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);
1067 @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
1069 #define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F
1072 MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC
1076 /// Individual bit fields
1080 /// [Bits 9:0] RMID.
1083 UINT32 Reserved1
:22;
1085 /// [Bits 51:32] COS (R/W).
1088 UINT32 Reserved2
:12;
1091 /// All bit fields as a 64-bit value
1094 } MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
;
1098 Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
1099 ECX=1):EDX.COS_MAX[15:0] >= n.
1101 @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n
1102 @param EAX Lower 32-bits of MSR value.
1103 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
1104 @param EDX Upper 32-bits of MSR value.
1105 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
1107 <b>Example usage</b>
1109 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
1111 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
1112 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
1114 @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM.
1115 MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM.
1116 MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM.
1117 MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM.
1118 MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM.
1119 MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM.
1120 MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM.
1121 MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM.
1122 MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM.
1123 MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM.
1124 MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.
1125 MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.
1126 MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.
1127 MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.
1128 MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.
1129 MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
1132 #define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90
1133 #define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91
1134 #define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92
1135 #define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93
1136 #define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94
1137 #define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95
1138 #define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96
1139 #define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97
1140 #define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98
1141 #define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99
1142 #define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A
1143 #define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B
1144 #define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C
1145 #define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D
1146 #define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E
1147 #define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F
1151 MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0
1152 to #MSR_XEON_D_IA32_L3_QOS_MASK_15.
1156 /// Individual bit fields
1160 /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.
1163 UINT32 Reserved2
:12;
1164 UINT32 Reserved3
:32;
1167 /// All bit fields as a 32-bit value
1171 /// All bit fields as a 64-bit value
1174 } MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
;
1178 Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1179 RW if MSR_PLATFORM_INFO.[28] = 1.
1181 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)
1182 @param EAX Lower 32-bits of MSR value.
1183 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
1184 @param EDX Upper 32-bits of MSR value.
1185 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
1187 <b>Example usage</b>
1189 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;
1191 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);
1193 @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.
1195 #define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC
1198 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3
1202 /// Individual bit fields
1205 UINT32 Reserved1
:32;
1206 UINT32 Reserved2
:31;
1208 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
1209 /// the processor uses override configuration specified in
1210 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor
1211 /// uses factory-set configuration (Default).
1213 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
1216 /// All bit fields as a 64-bit value
1219 } MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
;
1223 Package. Cache Allocation Technology Configuration (R/W).
1225 @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)
1226 @param EAX Lower 32-bits of MSR value.
1227 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
1228 @param EDX Upper 32-bits of MSR value.
1229 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
1231 <b>Example usage</b>
1233 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;
1235 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);
1236 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);
1238 @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
1240 #define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81
1243 MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG
1247 /// Individual bit fields
1251 /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.
1254 UINT32 Reserved1
:31;
1255 UINT32 Reserved2
:32;
1258 /// All bit fields as a 32-bit value
1262 /// All bit fields as a 64-bit value
1265 } MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER
;