2 Cache Maintenance Functions.
4 Copyright (c) 2006 - 2008, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/CacheMaintenanceLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/DebugLib.h>
19 #include <Library/PalLib.h>
22 Invalidates the entire instruction cache in cache coherency domain of the
25 Invalidates the entire instruction cache in cache coherency domain of the
31 InvalidateInstructionCache (
35 PalCall (PAL_CACHE_FLUSH
, PAL_CACHE_FLUSH_INSTRUCTION_ALL
, PAL_CACHE_FLUSH_INVALIDATE_LINES
| PAL_CACHE_FLUSH_NO_INTERRUPT
, 0);
39 Invalidates a range of instruction cache lines in the cache coherency domain
42 Invalidates the instruction cache lines specified by Address and Length. If
43 Address is not aligned on a cache line boundary, then entire instruction
44 cache line containing Address is invalidated. If Address + Length is not
45 aligned on a cache line boundary, then the entire instruction cache line
46 containing Address + Length -1 is invalidated. This function may choose to
47 invalidate the entire instruction cache if that is more efficient than
48 invalidating the specified range. If Length is 0, the no instruction cache
49 lines are invalidated. Address is returned.
51 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
53 @param Address The base address of the instruction cache lines to
54 invalidate. If the CPU is in a physical addressing mode, then
55 Address is a physical address. If the CPU is in a virtual
56 addressing mode, then Address is a virtual address.
58 @param Length The number of bytes to invalidate from the instruction cache.
65 InvalidateInstructionCacheRange (
70 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
71 return AsmFlushCacheRange (Address
, Length
);
75 Writes Back and Invalidates the entire data cache in cache coherency domain
78 Writes Back and Invalidates the entire data cache in cache coherency domain
79 of the calling CPU. This function guarantees that all dirty cache lines are
80 written back to system memory, and also invalidates all the data cache lines
81 in the cache coherency domain of the calling CPU.
86 WriteBackInvalidateDataCache (
90 PalCall (PAL_CACHE_FLUSH
, PAL_CACHE_FLUSH_DATA_ALL
, PAL_CACHE_FLUSH_INVALIDATE_LINES
| PAL_CACHE_FLUSH_NO_INTERRUPT
, 0);
94 Writes Back and Invalidates a range of data cache lines in the cache
95 coherency domain of the calling CPU.
97 Writes Back and Invalidate the data cache lines specified by Address and
98 Length. If Address is not aligned on a cache line boundary, then entire data
99 cache line containing Address is written back and invalidated. If Address +
100 Length is not aligned on a cache line boundary, then the entire data cache
101 line containing Address + Length -1 is written back and invalidated. This
102 function may choose to write back and invalidate the entire data cache if
103 that is more efficient than writing back and invalidating the specified
104 range. If Length is 0, the no data cache lines are written back and
105 invalidated. Address is returned.
107 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
109 @param Address The base address of the data cache lines to write back and
110 invalidate. If the CPU is in a physical addressing mode, then
111 Address is a physical address. If the CPU is in a virtual
112 addressing mode, then Address is a virtual address.
113 @param Length The number of bytes to write back and invalidate from the
116 @return Address of cache invalidation.
121 WriteBackInvalidateDataCacheRange (
126 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
128 return AsmFlushCacheRange (Address
, Length
);
132 Writes Back the entire data cache in cache coherency domain of the calling
135 Writes Back the entire data cache in cache coherency domain of the calling
136 CPU. This function guarantees that all dirty cache lines are written back to
137 system memory. This function may also invalidate all the data cache lines in
138 the cache coherency domain of the calling CPU.
147 PalCall (PAL_CACHE_FLUSH
, PAL_CACHE_FLUSH_DATA_ALL
, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES
| PAL_CACHE_FLUSH_NO_INTERRUPT
, 0);
151 Writes Back a range of data cache lines in the cache coherency domain of the
154 Writes Back the data cache lines specified by Address and Length. If Address
155 is not aligned on a cache line boundary, then entire data cache line
156 containing Address is written back. If Address + Length is not aligned on a
157 cache line boundary, then the entire data cache line containing Address +
158 Length -1 is written back. This function may choose to write back the entire
159 data cache if that is more efficient than writing back the specified range.
160 If Length is 0, the no data cache lines are written back. This function may
161 also invalidate all the data cache lines in the specified range of the cache
162 coherency domain of the calling CPU. Address is returned.
164 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
166 @param Address The base address of the data cache lines to write back. If
167 the CPU is in a physical addressing mode, then Address is a
168 physical address. If the CPU is in a virtual addressing
169 mode, then Address is a virtual address.
170 @param Length The number of bytes to write back from the data cache.
172 @return Address of cache written in main memory.
177 WriteBackDataCacheRange (
182 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
184 return AsmFlushCacheRange (Address
, Length
);
188 Invalidates the entire data cache in cache coherency domain of the calling
191 Invalidates the entire data cache in cache coherency domain of the calling
192 CPU. This function must be used with care because dirty cache lines are not
193 written back to system memory. It is typically used for cache diagnostics. If
194 the CPU does not support invalidation of the entire data cache, then a write
195 back and invalidate operation should be performed on the entire data cache.
200 InvalidateDataCache (
205 // Invalidation of entire data cache without writing back is not supported on
206 // IPF architecture, so write back and invalidate operation is performed.
208 WriteBackInvalidateDataCache ();
212 Invalidates a range of data cache lines in the cache coherency domain of the
215 Invalidates the data cache lines specified by Address and Length. If Address
216 is not aligned on a cache line boundary, then entire data cache line
217 containing Address is invalidated. If Address + Length is not aligned on a
218 cache line boundary, then the entire data cache line containing Address +
219 Length -1 is invalidated. This function must never invalidate any cache lines
220 outside the specified range. If Length is 0, the no data cache lines are
221 invalidated. Address is returned. This function must be used with care
222 because dirty cache lines are not written back to system memory. It is
223 typically used for cache diagnostics. If the CPU does not support
224 invalidation of a data cache range, then a write back and invalidate
225 operation should be performed on the data cache range.
227 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
229 @param Address The base address of the data cache lines to invalidate. If
230 the CPU is in a physical addressing mode, then Address is a
231 physical address. If the CPU is in a virtual addressing mode,
232 then Address is a virtual address.
233 @param Length The number of bytes to invalidate from the data cache.
240 InvalidateDataCacheRange (
245 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
247 // Invalidation of a data cache range without writing back is not supported on
248 // IPF architecture, so write back and invalidate operation is performed.
250 return AsmFlushCacheRange (Address
, Length
);