MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006 - 2008, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14 **/
  15
  16 #include <Base.h>
  17 #include <Library/BaseLib.h>
  18 #include <Library/DebugLib.h>
  19
  20 //
  21 // This size must be at or below the smallest cache size possible among all
  22 // supported processors
  23 //
  24 #define CACHE_LINE_SIZE             0x20
  25
  26 /**
  27   Invalidates the entire instruction cache in cache coherency domain of the
  28   calling CPU.
  29
  30   Invalidates the entire instruction cache in cache coherency domain of the
  31   calling CPU.
  32
  33 **/
  34 VOID
  35 EFIAPI
  36 InvalidateInstructionCache (
  37   VOID
  38   )
  39 {
  40 }
  41
  42 /**
  43   Invalidates a range of instruction cache lines in the cache coherency domain
  44   of the calling CPU.
  45
  46   Invalidates the instruction cache lines specified by Address and Length. If
  47   Address is not aligned on a cache line boundary, then entire instruction
  48   cache line containing Address is invalidated. If Address + Length is not
  49   aligned on a cache line boundary, then the entire instruction cache line
  50   containing Address + Length -1 is invalidated. This function may choose to
  51   invalidate the entire instruction cache if that is more efficient than
  52   invalidating the specified range. If Length is 0, the no instruction cache
  53   lines are invalidated. Address is returned.
  54
  55   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  56
  57   @param  Address The base address of the instruction cache lines to
  58                   invalidate. If the CPU is in a physical addressing mode, then
  59                   Address is a physical address. If the CPU is in a virtual
  60                   addressing mode, then Address is a virtual address.
  61
  62   @param  Length  The number of bytes to invalidate from the instruction cache.
  63
  64   @return Address.
  65
  66 **/
  67 VOID *
  68 EFIAPI
  69 InvalidateInstructionCacheRange (
  70   IN      VOID                      *Address,
  71   IN      UINTN                     Length
  72   )
  73 {
  74   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  75   return Address;
  76 }
  77
  78 /**
  79   Writes Back and Invalidates the entire data cache in cache coherency domain
  80   of the calling CPU.
  81
  82   Writes Back and Invalidates the entire data cache in cache coherency domain
  83   of the calling CPU. This function guarantees that all dirty cache lines are
  84   written back to system memory, and also invalidates all the data cache lines
  85   in the cache coherency domain of the calling CPU.
  86
  87 **/
  88 VOID
  89 EFIAPI
  90 WriteBackInvalidateDataCache (
  91   VOID
  92   )
  93 {
  94   AsmWbinvd ();
  95 }
  96
  97 /**
  98   Writes Back and Invalidates a range of data cache lines in the cache
  99   coherency domain of the calling CPU.
 100
 101   Writes Back and Invalidate the data cache lines specified by Address and
 102   Length. If Address is not aligned on a cache line boundary, then entire data
 103   cache line containing Address is written back and invalidated. If Address +
 104   Length is not aligned on a cache line boundary, then the entire data cache
 105   line containing Address + Length -1 is written back and invalidated. This
 106   function may choose to write back and invalidate the entire data cache if
 107   that is more efficient than writing back and invalidating the specified
 108   range. If Length is 0, the no data cache lines are written back and
 109   invalidated. Address is returned.
 110
 111   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 112
 113   @param  Address The base address of the data cache lines to write back and
 114                   invalidate. If the CPU is in a physical addressing mode, then
 115                   Address is a physical address. If the CPU is in a virtual
 116                   addressing mode, then Address is a virtual address.
 117   @param  Length  The number of bytes to write back and invalidate from the
 118                   data cache.
 119
 120   @return Address of cache invalidation.
 121
 122 **/
 123 VOID *
 124 EFIAPI
 125 WriteBackInvalidateDataCacheRange (
 126   IN      VOID                      *Address,
 127   IN      UINTN                     Length
 128   )
 129 {
 130   UINTN                             Start;
 131   UINTN                             End;
 132
 133   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 134
 135   if (Length == 0) {
 136     return Address;
 137   }
 138
 139   Start = (UINTN)Address;
 140   //
 141   // Calculate the cache line alignment
 142   //
 143   End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
 144   Start &= ~(CACHE_LINE_SIZE - 1);
 145
 146   do {
 147     Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
 148   } while (Start != End);
 149   return Address;
 150 }
 151
 152 /**
 153   Writes Back the entire data cache in cache coherency domain of the calling
 154   CPU.
 155
 156   Writes Back the entire data cache in cache coherency domain of the calling
 157   CPU. This function guarantees that all dirty cache lines are written back to
 158   system memory. This function may also invalidate all the data cache lines in
 159   the cache coherency domain of the calling CPU.
 160
 161 **/
 162 VOID
 163 EFIAPI
 164 WriteBackDataCache (
 165   VOID
 166   )
 167 {
 168   WriteBackInvalidateDataCache ();
 169 }
 170
 171 /**
 172   Writes Back a range of data cache lines in the cache coherency domain of the
 173   calling CPU.
 174
 175   Writes Back the data cache lines specified by Address and Length. If Address
 176   is not aligned on a cache line boundary, then entire data cache line
 177   containing Address is written back. If Address + Length is not aligned on a
 178   cache line boundary, then the entire data cache line containing Address +
 179   Length -1 is written back. This function may choose to write back the entire
 180   data cache if that is more efficient than writing back the specified range.
 181   If Length is 0, the no data cache lines are written back. This function may
 182   also invalidate all the data cache lines in the specified range of the cache
 183   coherency domain of the calling CPU. Address is returned.
 184
 185   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 186
 187   @param  Address The base address of the data cache lines to write back. If
 188                   the CPU is in a physical addressing mode, then Address is a
 189                   physical address. If the CPU is in a virtual addressing
 190                   mode, then Address is a virtual address.
 191   @param  Length  The number of bytes to write back from the data cache.
 192
 193   @return Address of cache written in main memory.
 194
 195 **/
 196 VOID *
 197 EFIAPI
 198 WriteBackDataCacheRange (
 199   IN      VOID                      *Address,
 200   IN      UINTN                     Length
 201   )
 202 {
 203   return WriteBackInvalidateDataCacheRange (Address, Length);
 204 }
 205
 206 /**
 207   Invalidates the entire data cache in cache coherency domain of the calling
 208   CPU.
 209
 210   Invalidates the entire data cache in cache coherency domain of the calling
 211   CPU. This function must be used with care because dirty cache lines are not
 212   written back to system memory. It is typically used for cache diagnostics. If
 213   the CPU does not support invalidation of the entire data cache, then a write
 214   back and invalidate operation should be performed on the entire data cache.
 215
 216 **/
 217 VOID
 218 EFIAPI
 219 InvalidateDataCache (
 220   VOID
 221   )
 222 {
 223   AsmInvd ();
 224 }
 225
 226 /**
 227   Invalidates a range of data cache lines in the cache coherency domain of the
 228   calling CPU.
 229
 230   Invalidates the data cache lines specified by Address and Length. If Address
 231   is not aligned on a cache line boundary, then entire data cache line
 232   containing Address is invalidated. If Address + Length is not aligned on a
 233   cache line boundary, then the entire data cache line containing Address +
 234   Length -1 is invalidated. This function must never invalidate any cache lines
 235   outside the specified range. If Length is 0, the no data cache lines are
 236   invalidated. Address is returned. This function must be used with care
 237   because dirty cache lines are not written back to system memory. It is
 238   typically used for cache diagnostics. If the CPU does not support
 239   invalidation of a data cache range, then a write back and invalidate
 240   operation should be performed on the data cache range.
 241
 242   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 243
 244   @param  Address The base address of the data cache lines to invalidate. If
 245                   the CPU is in a physical addressing mode, then Address is a
 246                   physical address. If the CPU is in a virtual addressing mode,
 247                   then Address is a virtual address.
 248   @param  Length  The number of bytes to invalidate from the data cache.
 249
 250   @return Address.
 251
 252 **/
 253 VOID *
 254 EFIAPI
 255 InvalidateDataCacheRange (
 256   IN      VOID                      *Address,
 257   IN      UINTN                     Length
 258   )
 259 {
 260   //
 261   // Invalidation of a data cache range without writing back is not supported on
 262   // x86 architecture, so write back and invalidate operation is performed.
 263   //
 264   return WriteBackInvalidateDataCacheRange (Address, Length);
 265 }