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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c
2 Cache Maintenance Functions.
4 Copyright (c) 2006 - 2008, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/BaseLib.h>
18 #include <Library/DebugLib.h>
21 // This size must be at or below the smallest cache size possible among all
22 // supported processors
24 #define CACHE_LINE_SIZE 0x20
27 Invalidates the entire instruction cache in cache coherency domain of the
30 Invalidates the entire instruction cache in cache coherency domain of the
36 InvalidateInstructionCache (
43 Invalidates a range of instruction cache lines in the cache coherency domain
46 Invalidates the instruction cache lines specified by Address and Length. If
47 Address is not aligned on a cache line boundary, then entire instruction
48 cache line containing Address is invalidated. If Address + Length is not
49 aligned on a cache line boundary, then the entire instruction cache line
50 containing Address + Length -1 is invalidated. This function may choose to
51 invalidate the entire instruction cache if that is more efficient than
52 invalidating the specified range. If Length is 0, the no instruction cache
53 lines are invalidated. Address is returned.
55 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
57 @param Address The base address of the instruction cache lines to
58 invalidate. If the CPU is in a physical addressing mode, then
59 Address is a physical address. If the CPU is in a virtual
60 addressing mode, then Address is a virtual address.
62 @param Length The number of bytes to invalidate from the instruction cache.
69 InvalidateInstructionCacheRange (
74 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
79 Writes Back and Invalidates the entire data cache in cache coherency domain
82 Writes Back and Invalidates the entire data cache in cache coherency domain
83 of the calling CPU. This function guarantees that all dirty cache lines are
84 written back to system memory, and also invalidates all the data cache lines
85 in the cache coherency domain of the calling CPU.
90 WriteBackInvalidateDataCache (
98 Writes Back and Invalidates a range of data cache lines in the cache
99 coherency domain of the calling CPU.
101 Writes Back and Invalidate the data cache lines specified by Address and
102 Length. If Address is not aligned on a cache line boundary, then entire data
103 cache line containing Address is written back and invalidated. If Address +
104 Length is not aligned on a cache line boundary, then the entire data cache
105 line containing Address + Length -1 is written back and invalidated. This
106 function may choose to write back and invalidate the entire data cache if
107 that is more efficient than writing back and invalidating the specified
108 range. If Length is 0, the no data cache lines are written back and
109 invalidated. Address is returned.
111 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
113 @param Address The base address of the data cache lines to write back and
114 invalidate. If the CPU is in a physical addressing mode, then
115 Address is a physical address. If the CPU is in a virtual
116 addressing mode, then Address is a virtual address.
117 @param Length The number of bytes to write back and invalidate from the
120 @return Address of cache invalidation.
125 WriteBackInvalidateDataCacheRange (
133 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
139 Start
= (UINTN
)Address
;
141 // Calculate the cache line alignment
143 End
= (Start
+ Length
+ (CACHE_LINE_SIZE
- 1)) & ~(CACHE_LINE_SIZE
- 1);
144 Start
&= ~(CACHE_LINE_SIZE
- 1);
147 Start
= (UINTN
)AsmFlushCacheLine ((VOID
*)Start
) + CACHE_LINE_SIZE
;
148 } while (Start
!= End
);
153 Writes Back the entire data cache in cache coherency domain of the calling
156 Writes Back the entire data cache in cache coherency domain of the calling
157 CPU. This function guarantees that all dirty cache lines are written back to
158 system memory. This function may also invalidate all the data cache lines in
159 the cache coherency domain of the calling CPU.
168 WriteBackInvalidateDataCache ();
172 Writes Back a range of data cache lines in the cache coherency domain of the
175 Writes Back the data cache lines specified by Address and Length. If Address
176 is not aligned on a cache line boundary, then entire data cache line
177 containing Address is written back. If Address + Length is not aligned on a
178 cache line boundary, then the entire data cache line containing Address +
179 Length -1 is written back. This function may choose to write back the entire
180 data cache if that is more efficient than writing back the specified range.
181 If Length is 0, the no data cache lines are written back. This function may
182 also invalidate all the data cache lines in the specified range of the cache
183 coherency domain of the calling CPU. Address is returned.
185 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
187 @param Address The base address of the data cache lines to write back. If
188 the CPU is in a physical addressing mode, then Address is a
189 physical address. If the CPU is in a virtual addressing
190 mode, then Address is a virtual address.
191 @param Length The number of bytes to write back from the data cache.
193 @return Address of cache written in main memory.
198 WriteBackDataCacheRange (
203 return WriteBackInvalidateDataCacheRange (Address
, Length
);
207 Invalidates the entire data cache in cache coherency domain of the calling
210 Invalidates the entire data cache in cache coherency domain of the calling
211 CPU. This function must be used with care because dirty cache lines are not
212 written back to system memory. It is typically used for cache diagnostics. If
213 the CPU does not support invalidation of the entire data cache, then a write
214 back and invalidate operation should be performed on the entire data cache.
219 InvalidateDataCache (
227 Invalidates a range of data cache lines in the cache coherency domain of the
230 Invalidates the data cache lines specified by Address and Length. If Address
231 is not aligned on a cache line boundary, then entire data cache line
232 containing Address is invalidated. If Address + Length is not aligned on a
233 cache line boundary, then the entire data cache line containing Address +
234 Length -1 is invalidated. This function must never invalidate any cache lines
235 outside the specified range. If Length is 0, the no data cache lines are
236 invalidated. Address is returned. This function must be used with care
237 because dirty cache lines are not written back to system memory. It is
238 typically used for cache diagnostics. If the CPU does not support
239 invalidation of a data cache range, then a write back and invalidate
240 operation should be performed on the data cache range.
242 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
244 @param Address The base address of the data cache lines to invalidate. If
245 the CPU is in a physical addressing mode, then Address is a
246 physical address. If the CPU is in a virtual addressing mode,
247 then Address is a virtual address.
248 @param Length The number of bytes to invalidate from the data cache.
255 InvalidateDataCacheRange (
261 // Invalidation of a data cache range without writing back is not supported on
262 // x86 architecture, so write back and invalidate operation is performed.
264 return WriteBackInvalidateDataCacheRange (Address
, Length
);